lane_value        222 drivers/gpu/drm/gma500/cdv_intel_display.c 	u32 lane_reg, lane_value;
lane_value        336 drivers/gpu/drm/gma500/cdv_intel_display.c 			cdv_sb_read(dev, lane_reg, &lane_value);
lane_value        337 drivers/gpu/drm/gma500/cdv_intel_display.c 			lane_value &= ~(LANE_PLL_MASK);
lane_value        338 drivers/gpu/drm/gma500/cdv_intel_display.c 			lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
lane_value        339 drivers/gpu/drm/gma500/cdv_intel_display.c 			cdv_sb_write(dev, lane_reg, lane_value);
lane_value        342 drivers/gpu/drm/gma500/cdv_intel_display.c 			cdv_sb_read(dev, lane_reg, &lane_value);
lane_value        343 drivers/gpu/drm/gma500/cdv_intel_display.c 			lane_value &= ~(LANE_PLL_MASK);
lane_value        344 drivers/gpu/drm/gma500/cdv_intel_display.c 			lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
lane_value        345 drivers/gpu/drm/gma500/cdv_intel_display.c 			cdv_sb_write(dev, lane_reg, lane_value);
lane_value        348 drivers/gpu/drm/gma500/cdv_intel_display.c 			cdv_sb_read(dev, lane_reg, &lane_value);
lane_value        349 drivers/gpu/drm/gma500/cdv_intel_display.c 			lane_value &= ~(LANE_PLL_MASK);
lane_value        350 drivers/gpu/drm/gma500/cdv_intel_display.c 			lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
lane_value        351 drivers/gpu/drm/gma500/cdv_intel_display.c 			cdv_sb_write(dev, lane_reg, lane_value);
lane_value        354 drivers/gpu/drm/gma500/cdv_intel_display.c 			cdv_sb_read(dev, lane_reg, &lane_value);
lane_value        355 drivers/gpu/drm/gma500/cdv_intel_display.c 			lane_value &= ~(LANE_PLL_MASK);
lane_value        356 drivers/gpu/drm/gma500/cdv_intel_display.c 			lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
lane_value        357 drivers/gpu/drm/gma500/cdv_intel_display.c 			cdv_sb_write(dev, lane_reg, lane_value);