lane_swp          202 arch/mips/include/asm/octeon/cvmx-pescx-defs.h 		uint64_t lane_swp:1;
lane_swp          226 arch/mips/include/asm/octeon/cvmx-pescx-defs.h 		uint64_t lane_swp:1;
lane_swp          617 arch/mips/pci/pcie-octeon.c 		pescx_ctl_status.s.lane_swp = 1;