lane_reversal     216 drivers/gpu/drm/i915/display/intel_combo_phy.c 				    int lane_count, bool lane_reversal)
lane_reversal     222 drivers/gpu/drm/i915/display/intel_combo_phy.c 		WARN_ON(lane_reversal);
lane_reversal     244 drivers/gpu/drm/i915/display/intel_combo_phy.c 			lane_mask = lane_reversal ? PWR_DOWN_LN_2_1_0 :
lane_reversal     248 drivers/gpu/drm/i915/display/intel_combo_phy.c 			lane_mask = lane_reversal ? PWR_DOWN_LN_1_0 :
lane_reversal      18 drivers/gpu/drm/i915/display/intel_combo_phy.h 				    int lane_count, bool lane_reversal);
lane_reversal    3207 drivers/gpu/drm/i915/display/intel_ddi.c 		bool lane_reversal =
lane_reversal    3212 drivers/gpu/drm/i915/display/intel_ddi.c 					       lane_reversal);
lane_reversal      99 drivers/gpu/drm/i915/display/intel_tc.c 	bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
lane_reversal     103 drivers/gpu/drm/i915/display/intel_tc.c 	WARN_ON(lane_reversal && dig_port->tc_mode != TC_PORT_LEGACY);
lane_reversal     111 drivers/gpu/drm/i915/display/intel_tc.c 		val |= lane_reversal ? DFLEXDPMLE1_DPMLETC_ML3(tc_port) :
lane_reversal     115 drivers/gpu/drm/i915/display/intel_tc.c 		val |= lane_reversal ? DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) :
lane_reversal     394 drivers/gpu/drm/i915/display/intel_vbt_defs.h 			u8 lane_reversal:1;			/* 184 */
lane_reversal      94 drivers/gpu/drm/i915/gvt/opregion.c 	u8 lane_reversal:1; /* 184 */
lane_reversal    8458 include/linux/mlx5/mlx5_ifc.h 	u8         lane_reversal[0x1];