lane_mask 119 arch/arm/mach-omap2/display.c static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask) lane_mask 122 arch/arm/mach-omap2/display.c return omap4_dsi_mux_pads(dsi_id, lane_mask); lane_mask 127 arch/arm/mach-omap2/display.c static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask) lane_mask 218 drivers/gpu/drm/i915/display/intel_combo_phy.c u8 lane_mask; lane_mask 226 drivers/gpu/drm/i915/display/intel_combo_phy.c lane_mask = PWR_DOWN_LN_3_1_0; lane_mask 229 drivers/gpu/drm/i915/display/intel_combo_phy.c lane_mask = PWR_DOWN_LN_3_1; lane_mask 232 drivers/gpu/drm/i915/display/intel_combo_phy.c lane_mask = PWR_DOWN_LN_3; lane_mask 238 drivers/gpu/drm/i915/display/intel_combo_phy.c lane_mask = PWR_UP_ALL_LANES; lane_mask 244 drivers/gpu/drm/i915/display/intel_combo_phy.c lane_mask = lane_reversal ? PWR_DOWN_LN_2_1_0 : lane_mask 248 drivers/gpu/drm/i915/display/intel_combo_phy.c lane_mask = lane_reversal ? PWR_DOWN_LN_1_0 : lane_mask 255 drivers/gpu/drm/i915/display/intel_combo_phy.c lane_mask = PWR_UP_ALL_LANES; lane_mask 262 drivers/gpu/drm/i915/display/intel_combo_phy.c val |= lane_mask << PWR_DOWN_LN_SHIFT; lane_mask 3064 drivers/gpu/drm/i915/display/intel_ddi.c u32 ln0, ln1, lane_mask; lane_mask 3077 drivers/gpu/drm/i915/display/intel_ddi.c lane_mask = intel_tc_port_get_lane_mask(intel_dig_port); lane_mask 3079 drivers/gpu/drm/i915/display/intel_ddi.c switch (lane_mask) { lane_mask 3104 drivers/gpu/drm/i915/display/intel_ddi.c MISSING_CASE(lane_mask); lane_mask 3436 drivers/gpu/drm/i915/display/intel_dp.c unsigned int lane_mask = 0x0; lane_mask 3439 drivers/gpu/drm/i915/display/intel_dp.c lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count); lane_mask 3442 drivers/gpu/drm/i915/display/intel_dp.c lane_mask); lane_mask 789 drivers/gpu/drm/i915/display/intel_dpio_phy.c unsigned int lane_mask = lane_mask 801 drivers/gpu/drm/i915/display/intel_dpio_phy.c chv_phy_powergate_lanes(encoder, true, lane_mask); lane_mask 53 drivers/gpu/drm/i915/display/intel_tc.c u32 lane_mask; lane_mask 55 drivers/gpu/drm/i915/display/intel_tc.c lane_mask = intel_uncore_read(uncore, lane_mask 58 drivers/gpu/drm/i915/display/intel_tc.c WARN_ON(lane_mask == 0xffffffff); lane_mask 60 drivers/gpu/drm/i915/display/intel_tc.c return (lane_mask & DP_LANE_ASSIGNMENT_MASK(tc_port)) >> lane_mask 68 drivers/gpu/drm/i915/display/intel_tc.c u32 lane_mask; lane_mask 73 drivers/gpu/drm/i915/display/intel_tc.c lane_mask = 0; lane_mask 75 drivers/gpu/drm/i915/display/intel_tc.c lane_mask = intel_tc_port_get_lane_mask(dig_port); lane_mask 77 drivers/gpu/drm/i915/display/intel_tc.c switch (lane_mask) { lane_mask 79 drivers/gpu/drm/i915/display/intel_tc.c MISSING_CASE(lane_mask); lane_mask 1991 drivers/gpu/drm/omapdrm/dss/dsi.c static int dsi_enable_pads(struct dsi_data *dsi, unsigned int lane_mask) lane_mask 1994 drivers/gpu/drm/omapdrm/dss/dsi.c return dsi_omap4_mux_pads(dsi, lane_mask); lane_mask 1996 drivers/gpu/drm/omapdrm/dss/dsi.c return dsi_omap5_mux_pads(dsi, lane_mask); lane_mask 86 drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c u32 pixel_clock, u8 bpp, u8 lane_mask) lane_mask 102 drivers/media/platform/qcom/camss/camss-csiphy-2ph-1-0.c val |= lane_mask << 1; lane_mask 138 drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c u32 pixel_clock, u8 bpp, u8 lane_mask) lane_mask 218 drivers/media/platform/qcom/camss/camss-csiphy.c u8 lane_mask; lane_mask 221 drivers/media/platform/qcom/camss/camss-csiphy.c lane_mask = 1 << lane_cfg->clk.pos; lane_mask 224 drivers/media/platform/qcom/camss/camss-csiphy.c lane_mask |= 1 << lane_cfg->data[i].pos; lane_mask 226 drivers/media/platform/qcom/camss/camss-csiphy.c return lane_mask; lane_mask 242 drivers/media/platform/qcom/camss/camss-csiphy.c u8 lane_mask = csiphy_get_lane_mask(&cfg->csi2->lane_cfg); lane_mask 261 drivers/media/platform/qcom/camss/camss-csiphy.c if (cfg->combo_mode && (lane_mask & 0x18) == 0x18) { lane_mask 271 drivers/media/platform/qcom/camss/camss-csiphy.c csiphy->ops->lanes_enable(csiphy, cfg, pixel_clock, bpp, lane_mask); lane_mask 53 drivers/media/platform/qcom/camss/camss-csiphy.h u32 pixel_clock, u8 bpp, u8 lane_mask); lane_mask 417 drivers/media/platform/rcar-vin/rcar-csi2.c const u32 lane_mask = (1 << priv->lanes) - 1; lane_mask 420 drivers/media/platform/rcar-vin/rcar-csi2.c (rcsi2_read(priv, PHDLM_REG) & lane_mask) == lane_mask) lane_mask 600 drivers/media/platform/ti-vpe/cal.c u32 lane_mask = CAL_CSI2_COMPLEXIO_CFG_CLOCK_POSITION_MASK; lane_mask 606 drivers/media/platform/ti-vpe/cal.c set_field(&val, mipi_csi2->clock_lane + 1, lane_mask); lane_mask 613 drivers/media/platform/ti-vpe/cal.c lane_mask <<= 4; lane_mask 615 drivers/media/platform/ti-vpe/cal.c set_field(&val, mipi_csi2->data_lanes[lane] + 1, lane_mask); lane_mask 2037 drivers/pci/controller/pci-tegra.c static int tegra_pcie_get_regulators(struct tegra_pcie *pcie, u32 lane_mask) lane_mask 2091 drivers/pci/controller/pci-tegra.c if (lane_mask & 0x0f) lane_mask 2095 drivers/pci/controller/pci-tegra.c if (lane_mask & 0x30) lane_mask 60 drivers/video/fbdev/omap2/omapfb/dss/core.c int dss_dsi_enable_pads(int dsi_id, unsigned lane_mask) lane_mask 67 drivers/video/fbdev/omap2/omapfb/dss/core.c return board_data->dsi_enable_pads(dsi_id, lane_mask); lane_mask 70 drivers/video/fbdev/omap2/omapfb/dss/core.c void dss_dsi_disable_pads(int dsi_id, unsigned lane_mask) lane_mask 77 drivers/video/fbdev/omap2/omapfb/dss/core.c return board_data->dsi_disable_pads(dsi_id, lane_mask); lane_mask 203 drivers/video/fbdev/omap2/omapfb/dss/dss.h int dss_dsi_enable_pads(int dsi_id, unsigned lane_mask); lane_mask 204 drivers/video/fbdev/omap2/omapfb/dss/dss.h void dss_dsi_disable_pads(int dsi_id, unsigned lane_mask); lane_mask 26 include/linux/platform_data/omapdss.h int (*dsi_enable_pads)(int dsi_id, unsigned int lane_mask); lane_mask 27 include/linux/platform_data/omapdss.h void (*dsi_disable_pads)(int dsi_id, unsigned int lane_mask);