lane_idx           15 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c 				     int lane_idx)
lane_idx           18 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c 	bool clk_ln = (lane_idx == PHY_14NM_CKLN_IDX);
lane_idx           27 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c 	dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(lane_idx),
lane_idx           29 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c 	dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(lane_idx),
lane_idx           31 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c 	dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(lane_idx),
lane_idx           33 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c 	dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(lane_idx),
lane_idx           35 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c 	dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(lane_idx),
lane_idx           37 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c 	dsi_phy_write(base + REG_DSI_14nm_PHY_LN_CFG0(lane_idx),
lane_idx           39 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c 	dsi_phy_write(base + REG_DSI_14nm_PHY_LN_CFG1(lane_idx),
lane_idx           41 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c 	dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(lane_idx),
lane_idx           44 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c 	dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(lane_idx),
lane_idx           46 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c 	dsi_phy_write(base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(lane_idx),