lane_count 439 drivers/edac/ppc4xx_edac.c const unsigned int lane_count = 16; lane_count 450 drivers/edac/ppc4xx_edac.c for (lanes = 0, lane = first_lane; lane < lane_count; lane++) { lane_count 207 drivers/gpu/drm/amd/amdgpu/atombios_dp.c int lane_count, lane_count 214 drivers/gpu/drm/amd/amdgpu/atombios_dp.c for (lane = 0; lane < lane_count; lane++) { lane_count 1634 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) || lane_count 4088 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c link->verified_link_cap.lane_count = LANE_COUNT_FOUR; lane_count 100 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c link->cur_link_settings.lane_count, lane_count 107 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c link->verified_link_cap.lane_count, lane_count 114 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c link->reported_link_cap.lane_count, lane_count 121 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c link->preferred_link_setting.lane_count, lane_count 230 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c prefer_link_settings.lane_count = param[0]; lane_count 390 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c link_lane_settings.link_settings.lane_count = lane_count 391 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c link->preferred_link_setting.lane_count; lane_count 397 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c link_lane_settings.link_settings.lane_count = lane_count 398 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c link->cur_link_settings.lane_count; lane_count 406 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c for (r = 0; r < link_lane_settings.link_settings.lane_count; r++) { lane_count 635 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c prefer_link_settings.lane_count = link->verified_link_cap.lane_count; lane_count 639 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c cur_link_settings.lane_count = link->cur_link_settings.lane_count; lane_count 647 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c if (prefer_link_settings.lane_count != LANE_COUNT_UNKNOWN && lane_count 649 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c (prefer_link_settings.lane_count != cur_link_settings.lane_count || lane_count 654 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c for (i = 0; i < (unsigned int)(link_training_settings.link_settings.lane_count); i++) lane_count 382 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c aconnector->dc_link->cur_link_settings.lane_count = 0; lane_count 155 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c cfg->link_settings.lane_count = lane_count 156 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c stream->link->cur_link_settings.lane_count; lane_count 546 drivers/gpu/drm/amd/display/dc/core/dc_link.c link->cur_link_settings.lane_count = lane_count_set.bits.LANE_COUNT_SET; lane_count 1482 drivers/gpu/drm/amd/display/dc/core/dc_link.c (link->cur_link_settings.lane_count != link_settings.lane_count || lane_count 1564 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) lane_count 3038 drivers/gpu/drm/amd/display/dc/core/dc_link.c if ((store_settings.lane_count != LANE_COUNT_UNKNOWN) && lane_count 3057 drivers/gpu/drm/amd/display/dc/core/dc_link.c link->preferred_link_setting.lane_count = LANE_COUNT_UNKNOWN; lane_count 3099 drivers/gpu/drm/amd/display/dc/core/dc_link.c link_bw_kbps *= link_setting->lane_count; lane_count 3135 drivers/gpu/drm/amd/display/dc/core/dc_link.c if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN && lane_count 141 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c lt_settings->link_settings.lane_count; lane_count 176 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c lt_settings->link_settings.lane_count, lane_count 186 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c lt_settings->link_settings.lane_count, lane_count 256 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c (uint32_t)(lt_settings->link_settings.lane_count); lane++) { lane_count 273 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c size_in_bytes = lt_settings->link_settings.lane_count * sizeof(dpcd_lane[0]); lane_count 354 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c for (lane = 0; lane < src.link_settings.lane_count; lane++) { lane_count 416 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c for (lane = 1; lane < link_training_setting->link_settings.lane_count; lane_count 474 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c max_lt_setting->link_settings.lane_count = lane_count 475 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c link_training_setting->link_settings.lane_count; lane_count 480 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c link_training_setting->link_settings.lane_count; lane_count 514 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c (uint32_t)(link_training_setting->link_settings.lane_count); lane_count 538 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c request_settings.link_settings.lane_count = lane_count 539 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c link_training_setting->link_settings.lane_count; lane_count 546 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c (uint32_t)(link_training_setting->link_settings.lane_count); lane_count 581 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c link_settings.lane_count); lane_count 602 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c link_training_setting->link_settings.lane_count); lane_count 640 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c (uint32_t)(lt_settings->link_settings.lane_count); lane_count 665 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c enum dc_lane_count lane_count = lane_count 666 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c lt_settings->link_settings.lane_count; lane_count 699 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c if (!is_cr_done(lane_count, dpcd_lane_status)) lane_count 703 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c lane_count, lane_count 708 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c for (lane = 0; lane < (uint32_t)(lane_count); lane++) { lane_count 773 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; lane_count 811 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c if (!is_cr_done(lane_count, dpcd_lane_status)) lane_count 815 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c if (is_ch_eq_done(lane_count, lane_count 835 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; lane_count 891 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c if (is_cr_done(lane_count, dpcd_lane_status)) lane_count 921 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c return get_cr_failure(lane_count, dpcd_lane_status); lane_count 952 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c lane_count_set.bits.LANE_COUNT_SET = lt_settings->link_settings.lane_count; lane_count 984 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN) lane_count 985 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c lt_settings->link_settings.lane_count = link->preferred_link_setting.lane_count; lane_count 987 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c lt_settings->link_settings.lane_count = link_setting->lane_count; lane_count 1129 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c lt_settings->link_settings.lane_count, lane_count 1413 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c if (link->reported_link_cap.lane_count < max_link_cap.lane_count) lane_count 1414 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c max_link_cap.lane_count = lane_count 1415 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c link->reported_link_cap.lane_count; lane_count 1486 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c if (link->cur_link_settings.lane_count == 0) lane_count 1492 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) { lane_count 1635 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c link->verified_link_cap.lane_count = LANE_COUNT_ONE; lane_count 1679 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c link_settings.lane_count = lane_count 1680 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c (link_setting_a.lane_count <= lane_count 1681 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c link_setting_b.lane_count) ? lane_count 1682 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c link_setting_a.lane_count : lane_count 1683 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c link_setting_b.lane_count; lane_count 1714 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count) lane_count 1716 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c return lane_count <= LANE_COUNT_ONE; lane_count 1724 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count) lane_count 1726 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c switch (lane_count) { lane_count 1754 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count) lane_count 1756 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c switch (lane_count) { lane_count 1808 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c (current_link_setting->lane_count)) { lane_count 1814 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c current_link_setting->lane_count = lane_count 1818 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c current_link_setting->lane_count = lane_count 1821 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c current_link_setting->lane_count = lane_count 1823 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c current_link_setting->lane_count); lane_count 1832 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c (current_link_setting->lane_count)) { lane_count 1833 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c current_link_setting->lane_count = lane_count 1835 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c current_link_setting->lane_count); lane_count 1931 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c if (current_link_setting.lane_count < lane_count 1932 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c link->verified_link_cap.lane_count) { lane_count 1933 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c current_link_setting.lane_count = lane_count 1935 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c current_link_setting.lane_count); lane_count 1940 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c current_link_setting.lane_count = lane_count 1941 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c initial_link_setting.lane_count; lane_count 1961 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c initial_link_setting.lane_count = LANE_COUNT_ONE; lane_count 1982 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c if (current_link_setting.lane_count < lane_count 1983 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c link->verified_link_cap.lane_count) { lane_count 1984 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c current_link_setting.lane_count = lane_count 1986 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c current_link_setting.lane_count); lane_count 1992 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c current_link_setting.lane_count = lane_count 1993 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c initial_link_setting.lane_count; lane_count 2014 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c if (link->preferred_link_setting.lane_count != lane_count 2037 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c ASSERT(link->verified_link_cap.lane_count != LANE_COUNT_UNKNOWN); lane_count 2052 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) || lane_count 2127 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c (unsigned char *)(&link_settings.lane_count), lane_count 2136 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c link->verified_link_cap.lane_count = link_settings.lane_count; lane_count 2234 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c (unsigned int)(link->cur_link_settings.lane_count); lane_count 2842 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c link->reported_link_cap.lane_count = lane_count 101 drivers/gpu/drm/amd/display/dc/dc_dp_types.h enum dc_lane_count lane_count; lane_count 527 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c cfg->link_settings.lane_count = lane_count 528 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c stream->link->cur_link_settings.lane_count; lane_count 486 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE); lane_count 1007 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c cntl.lanes_number = link_settings->lane_count; lane_count 1046 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c cntl.lanes_number = link_settings->lane_count; lane_count 1125 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c cntl.lanes_number = link_settings->link_settings.lane_count; lane_count 1130 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) { lane_count 652 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c enum dc_lane_count lane_count = lane_count 653 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c pipe_ctx->stream->link->cur_link_settings.lane_count; lane_count 678 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c if (lane_count != 0) lane_count 679 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c early_control = active_total_with_borders % lane_count; lane_count 682 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c early_control = lane_count; lane_count 496 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE); lane_count 969 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c cntl.lanes_number = link_settings->lane_count; lane_count 1008 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c cntl.lanes_number = link_settings->lane_count; lane_count 1091 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c cntl.lanes_number = link_settings->link_settings.lane_count; lane_count 1096 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) { lane_count 1923 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c enum dc_lane_count lane_count = lane_count 1924 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c pipe_ctx->stream->link->cur_link_settings.lane_count; lane_count 1952 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c if (lane_count != 0) lane_count 1953 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c early_control = active_total_with_borders % lane_count; lane_count 1956 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c early_control = lane_count; lane_count 218 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c for (i = 0; i < link_settings->lane_count; i++) lane_count 260 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c int lane, lane_count, pll_tries, retval; lane_count 262 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c lane_count = dp->link_train.lane_count; lane_count 267 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c for (lane = 0; lane < lane_count; lane++) lane_count 272 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c analogix_dp_set_lane_count(dp, dp->link_train.lane_count); lane_count 276 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c buf[1] = dp->link_train.lane_count; lane_count 288 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c for (lane = 0; lane < lane_count; lane++) lane_count 314 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c for (lane = 0; lane < lane_count; lane++) lane_count 319 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c lane_count); lane_count 334 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count) lane_count 339 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c for (lane = 0; lane < lane_count; lane++) { lane_count 348 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c int lane_count) lane_count 356 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c for (lane = 0; lane < lane_count; lane++) { lane_count 444 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c int lane, lane_count; lane_count 447 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c lane_count = dp->link_train.lane_count; lane_count 448 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c for (lane = 0; lane < lane_count; lane++) { lane_count 467 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c int lane, lane_count, retval; lane_count 473 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c lane_count = dp->link_train.lane_count; lane_count 484 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) { lane_count 497 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c for (lane = 0; lane < lane_count; lane++) { lane_count 525 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c for (lane = 0; lane < lane_count; lane++) lane_count 530 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c dp->link_train.training_lane, lane_count); lane_count 539 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c int lane, lane_count, retval; lane_count 545 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c lane_count = dp->link_train.lane_count; lane_count 551 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c if (analogix_dp_clock_recovery_ok(link_status, lane_count)) { lane_count 568 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) { lane_count 581 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c dp->link_train.lane_count = reg; lane_count 583 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c dp->link_train.lane_count); lane_count 599 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c for (lane = 0; lane < lane_count; lane++) lane_count 604 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c dp->link_train.training_lane, lane_count); lane_count 627 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c u8 *lane_count) lane_count 636 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c *lane_count = DPCD_MAX_LANE_COUNT(data); lane_count 653 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); lane_count 663 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c if (dp->link_train.lane_count == 0) { lane_count 665 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c dp->link_train.lane_count); lane_count 666 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c dp->link_train.lane_count = (u8)LANE_COUNT1; lane_count 670 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c if (dp->link_train.lane_count > max_lanes) lane_count 671 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c dp->link_train.lane_count = max_lanes; lane_count 720 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c analogix_dp_set_lane_count(dp, dp->link_train.lane_count); lane_count 722 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c for (i = 0; i < dp->link_train.lane_count; i++) { lane_count 769 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c dp->link_train.lane_count)) { lane_count 776 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c dp->link_train.lane_count)) { lane_count 151 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h u8 lane_count; lane_count 55 drivers/gpu/drm/bridge/parade-ps8622.c u32 lane_count; lane_count 191 drivers/gpu/drm/bridge/parade-ps8622.c err = ps8622_set(cl, 0x01, 0x21, 0x80 | ps8622->lane_count); lane_count 568 drivers/gpu/drm/bridge/parade-ps8622.c &ps8622->lane_count)) { lane_count 569 drivers/gpu/drm/bridge/parade-ps8622.c ps8622->lane_count = ps8622->max_lane_count; lane_count 570 drivers/gpu/drm/bridge/parade-ps8622.c } else if (ps8622->lane_count > ps8622->max_lane_count) { lane_count 573 drivers/gpu/drm/bridge/parade-ps8622.c ps8622->lane_count = ps8622->max_lane_count; lane_count 63 drivers/gpu/drm/drm_dp_helper.c int lane_count) lane_count 73 drivers/gpu/drm/drm_dp_helper.c for (lane = 0; lane < lane_count; lane++) { lane_count 83 drivers/gpu/drm/drm_dp_helper.c int lane_count) lane_count 88 drivers/gpu/drm/drm_dp_helper.c for (lane = 0; lane < lane_count; lane++) { lane_count 265 drivers/gpu/drm/gma500/cdv_intel_dp.c uint8_t lane_count; lane_count 901 drivers/gpu/drm/gma500/cdv_intel_dp.c int lane_count, clock; lane_count 914 drivers/gpu/drm/gma500/cdv_intel_dp.c for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { lane_count 916 drivers/gpu/drm/gma500/cdv_intel_dp.c int link_avail = cdv_intel_dp_max_data_rate(cdv_intel_dp_link_clock(bws[clock]), lane_count); lane_count 920 drivers/gpu/drm/gma500/cdv_intel_dp.c intel_dp->lane_count = lane_count; lane_count 924 drivers/gpu/drm/gma500/cdv_intel_dp.c intel_dp->link_bw, intel_dp->lane_count, lane_count 932 drivers/gpu/drm/gma500/cdv_intel_dp.c intel_dp->lane_count = max_lane_count; lane_count 937 drivers/gpu/drm/gma500/cdv_intel_dp.c intel_dp->link_bw, intel_dp->lane_count, lane_count 994 drivers/gpu/drm/gma500/cdv_intel_dp.c int lane_count = 4, bpp = 24; lane_count 1011 drivers/gpu/drm/gma500/cdv_intel_dp.c lane_count = intel_dp->lane_count; lane_count 1014 drivers/gpu/drm/gma500/cdv_intel_dp.c lane_count = intel_dp->lane_count; lane_count 1025 drivers/gpu/drm/gma500/cdv_intel_dp.c cdv_intel_dp_compute_m_n(bpp, lane_count, lane_count 1058 drivers/gpu/drm/gma500/cdv_intel_dp.c switch (intel_dp->lane_count) { lane_count 1074 drivers/gpu/drm/gma500/cdv_intel_dp.c intel_dp->link_configuration[1] = intel_dp->lane_count; lane_count 1313 drivers/gpu/drm/gma500/cdv_intel_dp.c for (lane = 0; lane < intel_dp->lane_count; lane++) { lane_count 1347 drivers/gpu/drm/gma500/cdv_intel_dp.c cdv_intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count) lane_count 1352 drivers/gpu/drm/gma500/cdv_intel_dp.c for (lane = 0; lane < lane_count; lane++) { lane_count 1376 drivers/gpu/drm/gma500/cdv_intel_dp.c for (lane = 0; lane < intel_dp->lane_count; lane++) { lane_count 1422 drivers/gpu/drm/gma500/cdv_intel_dp.c intel_dp->lane_count); lane_count 1424 drivers/gpu/drm/gma500/cdv_intel_dp.c if (ret != intel_dp->lane_count) { lane_count 1426 drivers/gpu/drm/gma500/cdv_intel_dp.c intel_dp->train_set[0], intel_dp->lane_count); lane_count 1558 drivers/gpu/drm/gma500/cdv_intel_dp.c if (cdv_intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) { lane_count 1565 drivers/gpu/drm/gma500/cdv_intel_dp.c for (i = 0; i < intel_dp->lane_count; i++) lane_count 1568 drivers/gpu/drm/gma500/cdv_intel_dp.c if (i == intel_dp->lane_count) lane_count 1643 drivers/gpu/drm/gma500/cdv_intel_dp.c if (!cdv_intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) { lane_count 472 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c int lane_count = dsi_config->lane_count; lane_count 487 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c val = lane_count; lane_count 508 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c (8 * lane_count)) & DSI_HS_TX_TIMEOUT_MASK); lane_count 525 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c dsi_config->lane_count, dsi_config->bpp); lane_count 751 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c dsi_config->lane_count, lane_count 775 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c int lane_count = dsi_config->lane_count; lane_count 789 drivers/gpu/drm/gma500/mdfld_dsi_dpi.c REG_WRITE(MIPI_DSI_FUNC_PRG_REG(pipe), 0x00000200 | lane_count); lane_count 419 drivers/gpu/drm/gma500/mdfld_dsi_output.c config->lane_count = 4; lane_count 421 drivers/gpu/drm/gma500/mdfld_dsi_output.c config->lane_count = 2; lane_count 260 drivers/gpu/drm/gma500/mdfld_dsi_output.h int lane_count; lane_count 314 drivers/gpu/drm/i915/display/icl_dsi.c intel_dsi->lane_count); lane_count 370 drivers/gpu/drm/i915/display/icl_dsi.c intel_dsi->lane_count, false); lane_count 731 drivers/gpu/drm/i915/display/icl_dsi.c tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count); lane_count 2240 drivers/gpu/drm/i915/display/intel_cdclk.c crtc_state->lane_count == 4) { lane_count 216 drivers/gpu/drm/i915/display/intel_combo_phy.c int lane_count, bool lane_reversal) lane_count 224 drivers/gpu/drm/i915/display/intel_combo_phy.c switch (lane_count) { lane_count 235 drivers/gpu/drm/i915/display/intel_combo_phy.c MISSING_CASE(lane_count); lane_count 242 drivers/gpu/drm/i915/display/intel_combo_phy.c switch (lane_count) { lane_count 252 drivers/gpu/drm/i915/display/intel_combo_phy.c MISSING_CASE(lane_count); lane_count 18 drivers/gpu/drm/i915/display/intel_combo_phy.h int lane_count, bool lane_reversal); lane_count 1205 drivers/gpu/drm/i915/display/intel_ddi.c intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); lane_count 1842 drivers/gpu/drm/i915/display/intel_ddi.c temp |= DDI_PORT_WIDTH(crtc_state->lane_count); lane_count 1845 drivers/gpu/drm/i915/display/intel_ddi.c temp |= DDI_PORT_WIDTH(crtc_state->lane_count); lane_count 2406 drivers/gpu/drm/i915/display/intel_ddi.c width = intel_dp->lane_count; lane_count 2532 drivers/gpu/drm/i915/display/intel_ddi.c width = intel_dp->lane_count; lane_count 3182 drivers/gpu/drm/i915/display/intel_ddi.c crtc_state->lane_count, is_mst); lane_count 3211 drivers/gpu/drm/i915/display/intel_ddi.c crtc_state->lane_count, lane_count 3696 drivers/gpu/drm/i915/display/intel_ddi.c int required_lanes = crtc_state ? crtc_state->lane_count : 1; lane_count 3724 drivers/gpu/drm/i915/display/intel_ddi.c intel_tc_port_get_link(dig_port, crtc_state->lane_count); lane_count 3735 drivers/gpu/drm/i915/display/intel_ddi.c intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); lane_count 3885 drivers/gpu/drm/i915/display/intel_ddi.c pipe_config->lane_count = 4; lane_count 3895 drivers/gpu/drm/i915/display/intel_ddi.c pipe_config->lane_count = lane_count 3901 drivers/gpu/drm/i915/display/intel_ddi.c pipe_config->lane_count = lane_count 4001 drivers/gpu/drm/i915/display/intel_ddi.c bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); lane_count 11965 drivers/gpu/drm/i915/display/intel_display.c const char *id, unsigned int lane_count, lane_count 11969 drivers/gpu/drm/i915/display/intel_display.c id, lane_count, lane_count 12105 drivers/gpu/drm/i915/display/intel_display.c pipe_config->lane_count, &pipe_config->dp_m_n); lane_count 12108 drivers/gpu/drm/i915/display/intel_display.c pipe_config->lane_count, lane_count 12704 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_I(lane_count); lane_count 879 drivers/gpu/drm/i915/display/intel_display_types.h u8 lane_count; lane_count 1151 drivers/gpu/drm/i915/display/intel_display_types.h u8 lane_count; lane_count 427 drivers/gpu/drm/i915/display/intel_dp.c u8 lane_count) lane_count 438 drivers/gpu/drm/i915/display/intel_dp.c if (lane_count == 0 || lane_count 439 drivers/gpu/drm/i915/display/intel_dp.c lane_count > intel_dp_max_lane_count(intel_dp)) lane_count 447 drivers/gpu/drm/i915/display/intel_dp.c u8 lane_count) lane_count 454 drivers/gpu/drm/i915/display/intel_dp.c max_rate = intel_dp_max_data_rate(link_rate, lane_count); lane_count 462 drivers/gpu/drm/i915/display/intel_dp.c int link_rate, u8 lane_count) lane_count 473 drivers/gpu/drm/i915/display/intel_dp.c lane_count)) { lane_count 478 drivers/gpu/drm/i915/display/intel_dp.c intel_dp->max_link_lane_count = lane_count; lane_count 479 drivers/gpu/drm/i915/display/intel_dp.c } else if (lane_count > 1) { lane_count 483 drivers/gpu/drm/i915/display/intel_dp.c lane_count >> 1)) { lane_count 488 drivers/gpu/drm/i915/display/intel_dp.c intel_dp->max_link_lane_count = lane_count >> 1; lane_count 503 drivers/gpu/drm/i915/display/intel_dp.c static u16 intel_dp_dsc_get_output_bpp(u32 link_clock, u32 lane_count, lane_count 515 drivers/gpu/drm/i915/display/intel_dp.c bits_per_pixel = (link_clock * lane_count * 8) / lane_count 1949 drivers/gpu/drm/i915/display/intel_dp.c int bpp, clock, lane_count; lane_count 1959 drivers/gpu/drm/i915/display/intel_dp.c for (lane_count = limits->min_lane_count; lane_count 1960 drivers/gpu/drm/i915/display/intel_dp.c lane_count <= limits->max_lane_count; lane_count 1961 drivers/gpu/drm/i915/display/intel_dp.c lane_count <<= 1) { lane_count 1964 drivers/gpu/drm/i915/display/intel_dp.c lane_count); lane_count 1967 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->lane_count = lane_count; lane_count 2029 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->lane_count = limits->max_lane_count; lane_count 2044 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->lane_count, lane_count 2164 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->lane_count, pipe_config->port_clock, lane_count 2172 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->lane_count)); lane_count 2175 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->lane_count, pipe_config->port_clock, lane_count 2182 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->lane_count)); lane_count 2320 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->lane_count, lane_count 2330 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->lane_count, lane_count 2346 drivers/gpu/drm/i915/display/intel_dp.c int link_rate, u8 lane_count, lane_count 2351 drivers/gpu/drm/i915/display/intel_dp.c intel_dp->lane_count = lane_count; lane_count 2365 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->lane_count, lane_count 2393 drivers/gpu/drm/i915/display/intel_dp.c intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count); lane_count 3189 drivers/gpu/drm/i915/display/intel_dp.c pipe_config->lane_count = lane_count 3439 drivers/gpu/drm/i915/display/intel_dp.c lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count); lane_count 4720 drivers/gpu/drm/i915/display/intel_dp.c !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) { lane_count 4786 drivers/gpu/drm/i915/display/intel_dp.c intel_dp->lane_count)) lane_count 4790 drivers/gpu/drm/i915/display/intel_dp.c return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count); lane_count 46 drivers/gpu/drm/i915/display/intel_dp.h int link_rate, u8 lane_count, lane_count 49 drivers/gpu/drm/i915/display/intel_dp.h int link_rate, u8 lane_count); lane_count 112 drivers/gpu/drm/i915/display/intel_dp.h static inline unsigned int intel_dp_unused_lane_mask(int lane_count) lane_count 114 drivers/gpu/drm/i915/display/intel_dp.h return ~((1 << lane_count) - 1) & 0xf; lane_count 47 drivers/gpu/drm/i915/display/intel_dp_link_training.c for (lane = 0; lane < intel_dp->lane_count; lane++) { lane_count 85 drivers/gpu/drm/i915/display/intel_dp_link_training.c memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); lane_count 86 drivers/gpu/drm/i915/display/intel_dp_link_training.c len = intel_dp->lane_count + 1; lane_count 112 drivers/gpu/drm/i915/display/intel_dp_link_training.c intel_dp->train_set, intel_dp->lane_count); lane_count 114 drivers/gpu/drm/i915/display/intel_dp_link_training.c return ret == intel_dp->lane_count; lane_count 121 drivers/gpu/drm/i915/display/intel_dp_link_training.c for (lane = 0; lane < intel_dp->lane_count; lane++) lane_count 152 drivers/gpu/drm/i915/display/intel_dp_link_training.c link_config[1] = intel_dp->lane_count; lane_count 200 drivers/gpu/drm/i915/display/intel_dp_link_training.c if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { lane_count 312 drivers/gpu/drm/i915/display/intel_dp_link_training.c intel_dp->lane_count)) { lane_count 320 drivers/gpu/drm/i915/display/intel_dp_link_training.c intel_dp->lane_count)) { lane_count 368 drivers/gpu/drm/i915/display/intel_dp_link_training.c intel_dp->link_rate, intel_dp->lane_count); lane_count 375 drivers/gpu/drm/i915/display/intel_dp_link_training.c intel_dp->link_rate, intel_dp->lane_count); lane_count 378 drivers/gpu/drm/i915/display/intel_dp_link_training.c intel_dp->lane_count)) lane_count 57 drivers/gpu/drm/i915/display/intel_dp_mst.c crtc_state->lane_count = limits->max_lane_count; lane_count 80 drivers/gpu/drm/i915/display/intel_dp_mst.c crtc_state->lane_count, lane_count 153 drivers/gpu/drm/i915/display/intel_dp_mst.c bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); lane_count 574 drivers/gpu/drm/i915/display/intel_dpio_phy.c bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count) lane_count 576 drivers/gpu/drm/i915/display/intel_dpio_phy.c switch (lane_count) { lane_count 584 drivers/gpu/drm/i915/display/intel_dpio_phy.c MISSING_CASE(lane_count); lane_count 661 drivers/gpu/drm/i915/display/intel_dpio_phy.c if (intel_crtc->config->lane_count > 2) { lane_count 674 drivers/gpu/drm/i915/display/intel_dpio_phy.c if (intel_crtc->config->lane_count > 2) { lane_count 682 drivers/gpu/drm/i915/display/intel_dpio_phy.c for (i = 0; i < intel_crtc->config->lane_count; i++) { lane_count 690 drivers/gpu/drm/i915/display/intel_dpio_phy.c for (i = 0; i < intel_crtc->config->lane_count; i++) { lane_count 713 drivers/gpu/drm/i915/display/intel_dpio_phy.c for (i = 0; i < intel_crtc->config->lane_count; i++) { lane_count 727 drivers/gpu/drm/i915/display/intel_dpio_phy.c if (intel_crtc->config->lane_count > 2) { lane_count 753 drivers/gpu/drm/i915/display/intel_dpio_phy.c if (crtc_state->lane_count > 2) { lane_count 770 drivers/gpu/drm/i915/display/intel_dpio_phy.c if (crtc_state->lane_count > 2) { lane_count 790 drivers/gpu/drm/i915/display/intel_dpio_phy.c intel_dp_unused_lane_mask(crtc_state->lane_count); lane_count 836 drivers/gpu/drm/i915/display/intel_dpio_phy.c if (crtc_state->lane_count > 2) { lane_count 880 drivers/gpu/drm/i915/display/intel_dpio_phy.c if (crtc_state->lane_count > 2) { lane_count 887 drivers/gpu/drm/i915/display/intel_dpio_phy.c for (i = 0; i < crtc_state->lane_count; i++) { lane_count 889 drivers/gpu/drm/i915/display/intel_dpio_phy.c if (crtc_state->lane_count == 1) lane_count 913 drivers/gpu/drm/i915/display/intel_dpio_phy.c if (crtc_state->lane_count > 2) { lane_count 926 drivers/gpu/drm/i915/display/intel_dpio_phy.c if (crtc_state->lane_count > 2) { lane_count 29 drivers/gpu/drm/i915/display/intel_dpio_phy.h u8 bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count); lane_count 16 drivers/gpu/drm/i915/display/intel_dsi.c return intel_dsi->pclk * bpp / intel_dsi->lane_count; lane_count 69 drivers/gpu/drm/i915/display/intel_dsi.h unsigned int lane_count; lane_count 537 drivers/gpu/drm/i915/display/intel_dsi_vbt.c DRM_DEBUG_KMS("Lane count %d\n", intel_dsi->lane_count); lane_count 585 drivers/gpu/drm/i915/display/intel_dsi_vbt.c intel_dsi->lane_count = mipi_config->lane_cnt + 1; lane_count 1828 drivers/gpu/drm/i915/display/intel_hdmi.c pipe_config->lane_count = 4; lane_count 2399 drivers/gpu/drm/i915/display/intel_hdmi.c pipe_config->lane_count = 4; lane_count 44 drivers/gpu/drm/i915/display/vlv_dsi.c static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, lane_count 48 drivers/gpu/drm/i915/display/vlv_dsi.c 8 * 100), lane_count); lane_count 52 drivers/gpu/drm/i915/display/vlv_dsi.c static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count, lane_count 55 drivers/gpu/drm/i915/display/vlv_dsi.c return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100), lane_count 1039 drivers/gpu/drm/i915/display/vlv_dsi.c unsigned int lane_count = intel_dsi->lane_count; lane_count 1088 drivers/gpu/drm/i915/display/vlv_dsi.c hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count, lane_count 1090 drivers/gpu/drm/i915/display/vlv_dsi.c hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count, lane_count 1092 drivers/gpu/drm/i915/display/vlv_dsi.c hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count, lane_count 1142 drivers/gpu/drm/i915/display/vlv_dsi.c hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count, lane_count 1144 drivers/gpu/drm/i915/display/vlv_dsi.c hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count, lane_count 1146 drivers/gpu/drm/i915/display/vlv_dsi.c hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count, lane_count 1150 drivers/gpu/drm/i915/display/vlv_dsi.c hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count, lane_count 1152 drivers/gpu/drm/i915/display/vlv_dsi.c hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count, lane_count 1154 drivers/gpu/drm/i915/display/vlv_dsi.c hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count, lane_count 1234 drivers/gpu/drm/i915/display/vlv_dsi.c unsigned int lane_count = intel_dsi->lane_count; lane_count 1257 drivers/gpu/drm/i915/display/vlv_dsi.c hactive = txbyteclkhs(hactive, bpp, lane_count, lane_count 1259 drivers/gpu/drm/i915/display/vlv_dsi.c hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio); lane_count 1260 drivers/gpu/drm/i915/display/vlv_dsi.c hsync = txbyteclkhs(hsync, bpp, lane_count, lane_count 1262 drivers/gpu/drm/i915/display/vlv_dsi.c hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); lane_count 1375 drivers/gpu/drm/i915/display/vlv_dsi.c val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; lane_count 1420 drivers/gpu/drm/i915/display/vlv_dsi.c intel_dsi->lane_count, lane_count 1426 drivers/gpu/drm/i915/display/vlv_dsi.c bpp, intel_dsi->lane_count, lane_count 1666 drivers/gpu/drm/i915/display/vlv_dsi.c switch (intel_dsi->lane_count) { lane_count 44 drivers/gpu/drm/i915/display/vlv_dsi_pll.c int lane_count) lane_count 51 drivers/gpu/drm/i915/display/vlv_dsi_pll.c dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count); lane_count 125 drivers/gpu/drm/i915/display/vlv_dsi_pll.c intel_dsi->lane_count); lane_count 313 drivers/gpu/drm/i915/display/vlv_dsi_pll.c pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, bpp); lane_count 334 drivers/gpu/drm/i915/display/vlv_dsi_pll.c pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, bpp); lane_count 463 drivers/gpu/drm/i915/display/vlv_dsi_pll.c intel_dsi->lane_count); lane_count 257 drivers/gpu/drm/radeon/atombios_dp.c int lane_count, lane_count 264 drivers/gpu/drm/radeon/atombios_dp.c for (lane = 0; lane < lane_count; lane++) { lane_count 1045 include/drm/drm_dp_helper.h int lane_count); lane_count 1047 include/drm/drm_dp_helper.h int lane_count);