lane_byte_clk_kHz 72 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c u32 lane_byte_clk_kHz; lane_byte_clk_kHz 283 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c phy->lane_byte_clk_kHz = phy_rate_kHz / 8; lane_byte_clk_kHz 285 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c DIV_ROUND_UP(phy->lane_byte_clk_kHz, MAX_TX_ESC_CLK); lane_byte_clk_kHz 447 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c u32 lane_byte_clk_kHz, lane_byte_clk_kHz 488 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c hsa_time = (hsw * lane_byte_clk_kHz) / pixel_clk_kHz; lane_byte_clk_kHz 489 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c hbp_time = (hbp * lane_byte_clk_kHz) / pixel_clk_kHz; lane_byte_clk_kHz 490 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c tmp = (u64)htot * (u64)lane_byte_clk_kHz; lane_byte_clk_kHz 558 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c dsi_set_mode_timing(base, phy->lane_byte_clk_kHz, mode, dsi->format); lane_byte_clk_kHz 567 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c dsi->lanes, mode->clock, phy->lane_byte_clk_kHz); lane_byte_clk_kHz 614 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c u32 req_kHz, act_kHz, lane_byte_clk_kHz; lane_byte_clk_kHz 620 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c lane_byte_clk_kHz = act_kHz / 8; lane_byte_clk_kHz 630 drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c if (mode->clock/dsi->lanes == lane_byte_clk_kHz/3) {