lane_base 79 drivers/gpu/drm/msm/dsi/phy/dsi_phy.h void __iomem *lane_base; lane_base 24 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c void __iomem *lane_base = phy->lane_base; lane_base 32 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(lane_base + lane_base 35 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(lane_base + lane_base 43 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c void __iomem *lane_base = phy->lane_base; lane_base 50 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(i), lane_base 57 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_LPRX_CTRL(i), 0); lane_base 58 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_PIN_SWAP(i), 0x0); lane_base 59 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL(i), lane_base 67 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_CFG0(i), 0x0); lane_base 68 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_CFG1(i), 0x0); lane_base 69 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_CFG2(i), 0x0); lane_base 70 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_CFG3(i), lane_base 72 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(lane_base + lane_base 74 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(lane_base + lane_base 76 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(i), lane_base 82 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(3), 0x05); lane_base 83 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(3), 0x04); lane_base 201 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c phy->lane_base = msm_ioremap(pdev, "dsi_phy_lane", lane_base 203 drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c if (IS_ERR(phy->lane_base)) { lane_base 17 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c void __iomem *base = phy->lane_base; lane_base 58 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c void __iomem *lane_base = phy->lane_base; lane_base 75 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_VREG_CNTRL(i), lane_base 78 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(lane_base + lane_base 80 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(lane_base + lane_base 84 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_CFG3(i), lane_base 86 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_CFG2(i), 0x10); lane_base 87 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_TEST_DATAPATH(i), lane_base 89 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c dsi_phy_write(lane_base + REG_DSI_14nm_PHY_LN_TEST_STR(i), lane_base 136 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c phy->lane_base = msm_ioremap(pdev, "dsi_phy_lane", lane_base 138 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c if (IS_ERR(phy->lane_base)) {