lane 21 arch/arm/mach-mv78xx0/pcie.c #define MV78XX0_MBUS_PCIE_MEM_TARGET(port, lane) ((port) ? 8 : 4) lane 22 arch/arm/mach-mv78xx0/pcie.c #define MV78XX0_MBUS_PCIE_MEM_ATTR(port, lane) (0xf8 & ~(0x10 << (lane))) lane 23 arch/arm/mach-mv78xx0/pcie.c #define MV78XX0_MBUS_PCIE_IO_TARGET(port, lane) ((port) ? 8 : 4) lane 24 arch/arm/mach-mv78xx0/pcie.c #define MV78XX0_MBUS_PCIE_IO_ATTR(port, lane) (0xf0 & ~(0x10 << (lane))) lane 51 arch/mips/cavium-octeon/executive/cvmx-helper-errata.c int lane; lane 54 arch/mips/cavium-octeon/executive/cvmx-helper-errata.c for (lane = 0; lane < 4; lane++) { lane 181 arch/sh/drivers/pci/pcie-sh7786.c unsigned int lane, unsigned int data) lane 185 arch/sh/drivers/pci/pcie-sh7786.c phyaddr = (1 << BITS_CMD) + ((lane & 0xf) << BITS_LANE) + lane 2438 drivers/acpi/nfit/core.c unsigned int lane) lane 2446 drivers/acpi/nfit/core.c + lane * mmio->size; lane 2447 drivers/acpi/nfit/core.c write_blk_ctl(nfit_blk, lane, dpa, len, rw); lane 2481 drivers/acpi/nfit/core.c rc = read_blk_stat(nfit_blk, lane) ? -EIO : 0; lane 2491 drivers/acpi/nfit/core.c unsigned int lane, copied = 0; lane 2494 drivers/acpi/nfit/core.c lane = nd_region_acquire_lane(nd_region); lane 2499 drivers/acpi/nfit/core.c iobuf + copied, c, rw, lane); lane 2506 drivers/acpi/nfit/core.c nd_region_release_lane(nd_region, lane); lane 259 drivers/ata/sata_highbank.c u8 lane = port_data[sata_port].lane_mapping; lane 263 drivers/ata/sata_highbank.c tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + lane * SPHY_LANE); lane 265 drivers/ata/sata_highbank.c combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp); lane 270 drivers/ata/sata_highbank.c u8 lane = port_data[sata_port].lane_mapping; lane 276 drivers/ata/sata_highbank.c tmp = combo_phy_read(sata_port, CPHY_TX_INPUT_STS + lane * SPHY_LANE); lane 278 drivers/ata/sata_highbank.c combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp); lane 281 drivers/ata/sata_highbank.c combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp); lane 284 drivers/ata/sata_highbank.c combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp); lane 289 drivers/ata/sata_highbank.c u8 lane = port_data[sata_port].lane_mapping; lane 291 drivers/ata/sata_highbank.c tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + lane * SPHY_LANE); lane 293 drivers/ata/sata_highbank.c combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp); lane 296 drivers/ata/sata_highbank.c combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp); lane 300 drivers/ata/sata_highbank.c combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp); lane 303 drivers/ata/sata_highbank.c combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp); lane 306 drivers/ata/sata_highbank.c combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp); lane 313 drivers/ata/sata_highbank.c u8 lane = port_data[sata_port].lane_mapping; lane 320 drivers/ata/sata_highbank.c lane * SPHY_LANE); lane 437 drivers/edac/ppc4xx_edac.c unsigned int lane, lanes; lane 450 drivers/edac/ppc4xx_edac.c for (lanes = 0, lane = first_lane; lane < lane_count; lane++) { lane 451 drivers/edac/ppc4xx_edac.c if ((status->ecces & SDRAM_ECCES_BNCE_ENCODE(lane)) != 0) { lane 454 drivers/edac/ppc4xx_edac.c (lanes++ ? ", " : ""), lane); lane 154 drivers/edac/ppc4xx_edac.h #define SDRAM_ECCES_BNCE_ENCODE(lane) PPC_REG_VAL(((lane) & 0xF), 1) lane 1081 drivers/edac/thunderx_edac.c int lane; lane 1088 drivers/edac/thunderx_edac.c for (lane = 0; lane < OCX_RX_LANES; lane++) { lane 1089 drivers/edac/thunderx_edac.c ctx->reg_lane_int[lane] = lane 1090 drivers/edac/thunderx_edac.c readq(ocx->regs + OCX_LNE_INT(lane)); lane 1091 drivers/edac/thunderx_edac.c ctx->reg_lane_stat11[lane] = lane 1092 drivers/edac/thunderx_edac.c readq(ocx->regs + OCX_LNE_STAT(lane, 11)); lane 1094 drivers/edac/thunderx_edac.c writeq(ctx->reg_lane_int[lane], ocx->regs + OCX_LNE_INT(lane)); lane 1114 drivers/edac/thunderx_edac.c int lane; lane 1138 drivers/edac/thunderx_edac.c for (lane = 0; lane < OCX_RX_LANES; lane++) lane 1139 drivers/edac/thunderx_edac.c if (ctx->reg_com_int & BIT(lane)) { lane 1142 drivers/edac/thunderx_edac.c lane, ctx->reg_lane_int[lane], lane 1143 drivers/edac/thunderx_edac.c lane, ctx->reg_lane_stat11[lane]); lane 1149 drivers/edac/thunderx_edac.c ctx->reg_lane_int[lane]); lane 1329 drivers/edac/thunderx_edac.c int lane, stat, cfg; lane 1331 drivers/edac/thunderx_edac.c for (lane = 0; lane < OCX_RX_LANES; lane++) { lane 1332 drivers/edac/thunderx_edac.c cfg = readq(ocx->regs + OCX_LNE_CFG(lane)); lane 1335 drivers/edac/thunderx_edac.c writeq(cfg, ocx->regs + OCX_LNE_CFG(lane)); lane 1338 drivers/edac/thunderx_edac.c readq(ocx->regs + OCX_LNE_STAT(lane, stat)); lane 212 drivers/gpu/drm/amd/amdgpu/atombios_dp.c int lane; lane 214 drivers/gpu/drm/amd/amdgpu/atombios_dp.c for (lane = 0; lane < lane_count; lane++) { lane 215 drivers/gpu/drm/amd/amdgpu/atombios_dp.c u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane); lane 216 drivers/gpu/drm/amd/amdgpu/atombios_dp.c u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); lane 219 drivers/gpu/drm/amd/amdgpu/atombios_dp.c lane, lane 239 drivers/gpu/drm/amd/amdgpu/atombios_dp.c for (lane = 0; lane < 4; lane++) lane 240 drivers/gpu/drm/amd/amdgpu/atombios_dp.c train_set[lane] = v | p; lane 234 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c uint32_t lane; lane 255 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c for (lane = 0; lane < lane 256 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c (uint32_t)(lt_settings->link_settings.lane_count); lane++) { lane 258 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c dpcd_lane[lane].bits.VOLTAGE_SWING_SET = lane 259 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c (uint8_t)(lt_settings->lane_settings[lane].VOLTAGE_SWING); lane 260 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c dpcd_lane[lane].bits.PRE_EMPHASIS_SET = lane 261 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c (uint8_t)(lt_settings->lane_settings[lane].PRE_EMPHASIS); lane 263 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c dpcd_lane[lane].bits.MAX_SWING_REACHED = lane 264 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c (lt_settings->lane_settings[lane].VOLTAGE_SWING == lane 266 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED = lane 267 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c (lt_settings->lane_settings[lane].PRE_EMPHASIS == lane 320 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c uint32_t lane; lane 322 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c for (lane = 0; lane < (uint32_t)(ln_count); lane++) { lane 323 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c if (!dpcd_lane_status[lane].bits.CR_DONE_0) lane 335 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c uint32_t lane; lane 339 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c for (lane = 0; lane < (uint32_t)(ln_count); lane++) { lane 340 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c if (!dpcd_lane_status[lane].bits.SYMBOL_LOCKED_0 || lane 341 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c !dpcd_lane_status[lane].bits.CHANNEL_EQ_DONE_0) lane 353 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c uint32_t lane; lane 354 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c for (lane = 0; lane < src.link_settings.lane_count; lane++) { lane 356 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c dest->lane_settings[lane].VOLTAGE_SWING = src.lane_settings[lane].VOLTAGE_SWING; lane 358 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c dest->lane_settings[lane].VOLTAGE_SWING = *dest->voltage_swing; lane 361 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c dest->lane_settings[lane].PRE_EMPHASIS = src.lane_settings[lane].PRE_EMPHASIS; lane 363 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c dest->lane_settings[lane].PRE_EMPHASIS = *dest->pre_emphasis; lane 366 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c dest->lane_settings[lane].POST_CURSOR2 = src.lane_settings[lane].POST_CURSOR2; lane 368 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c dest->lane_settings[lane].POST_CURSOR2 = *dest->post_cursor2; lane 403 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c uint32_t lane; lane 416 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c for (lane = 1; lane < link_training_setting->link_settings.lane_count; lane 417 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c lane++) { lane 418 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c if (link_training_setting->lane_settings[lane].VOLTAGE_SWING > lane 423 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c lane_settings[lane].VOLTAGE_SWING; lane 425 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c if (link_training_setting->lane_settings[lane].PRE_EMPHASIS > lane 429 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c lane_settings[lane].PRE_EMPHASIS; lane 479 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c for (lane = 0; lane < lane 481 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c lane++) { lane 482 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c max_lt_setting->lane_settings[lane].VOLTAGE_SWING = lane 484 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c max_lt_setting->lane_settings[lane].PRE_EMPHASIS = lane 503 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c uint32_t lane; lane 513 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c for (lane = 0; lane < lane 515 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c lane++) { lane 517 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c ln_status[lane].raw = lane 518 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c get_nibble_at_index(&dpcd_buf[0], lane); lane 519 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c dpcd_lane_adjust[lane].raw = lane 520 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c get_nibble_at_index(&dpcd_buf[4], lane); lane 545 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c for (lane = 0; lane < lane 547 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c lane++) { lane 549 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c request_settings.lane_settings[lane].VOLTAGE_SWING = lane 550 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c (enum dc_voltage_swing)(dpcd_lane_adjust[lane].bits. lane 552 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c request_settings.lane_settings[lane].PRE_EMPHASIS = lane 553 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c (enum dc_pre_emphasis)(dpcd_lane_adjust[lane].bits. lane 577 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c uint32_t lane; lane 579 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c for (lane = 0; lane < lane 582 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c lane++) { lane 583 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c dpcd_lane[lane].bits.VOLTAGE_SWING_SET = lane 585 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c lane_settings[lane].VOLTAGE_SWING); lane 586 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c dpcd_lane[lane].bits.PRE_EMPHASIS_SET = lane 588 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c lane_settings[lane].PRE_EMPHASIS); lane 589 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c dpcd_lane[lane].bits.MAX_SWING_REACHED = lane 591 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c lane_settings[lane].VOLTAGE_SWING == lane 593 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED = lane 595 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c lane_settings[lane].PRE_EMPHASIS == lane 638 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c uint32_t lane; lane 639 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c for (lane = 0; lane < lane 641 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c lane++) { lane 642 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c if (lt_settings->lane_settings[lane].VOLTAGE_SWING lane 671 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c uint32_t lane; lane 708 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c for (lane = 0; lane < (uint32_t)(lane_count); lane++) { lane 711 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c lane_settings[lane].VOLTAGE_SWING != lane 712 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c req_settings.lane_settings[lane]. lane 714 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c lt_settings->lane_settings[lane].PRE_EMPHASIS != lane 715 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c req_settings.lane_settings[lane].PRE_EMPHASIS) { lane 971 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c uint32_t lane; lane 1020 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { lane 1021 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c lt_settings->lane_settings[lane].VOLTAGE_SWING = lane 1025 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c lt_settings->lane_settings[lane].PRE_EMPHASIS = lane 1029 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c lt_settings->lane_settings[lane].POST_CURSOR2 = lane 1479 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c uint32_t lane; lane 1492 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) { lane 1498 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c lane); lane 2157 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c unsigned int lane; lane 2233 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c for (lane = 0; lane < lane 2235 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c lane++) { lane 2237 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c get_nibble_at_index(&dpcd_lane_adjustment[0].raw, lane); lane 2238 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c link_settings.lane_settings[lane].VOLTAGE_SWING = lane 2241 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c link_settings.lane_settings[lane].PRE_EMPHASIS = lane 2244 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c link_settings.lane_settings[lane].POST_CURSOR2 = lane 2246 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c ((dpcd_post_cursor_2_adjustment >> (lane * 2)) & 0x03); lane 3195 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c unsigned int lane; lane 3305 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) lane 3306 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c link_qual_pattern[lane] = lane 1114 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c int32_t lane = 0; lane 1130 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) { lane 1134 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c link_settings->lane_settings[lane].VOLTAGE_SWING; lane 1136 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c link_settings->lane_settings[lane].PRE_EMPHASIS; lane 1144 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c link_settings->lane_settings[lane].POST_CURSOR2; lane 1147 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c cntl.lane_select = lane; lane 1080 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c int32_t lane = 0; lane 1096 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) { lane 1100 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c link_settings->lane_settings[lane].VOLTAGE_SWING; lane 1102 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c link_settings->lane_settings[lane].PRE_EMPHASIS; lane 1110 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c link_settings->lane_settings[lane].POST_CURSOR2; lane 1113 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c cntl.lane_select = lane; lane 237 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c int pre_emphasis, int lane) lane 239 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c switch (lane) { lane 260 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c int lane, lane_count, pll_tries, retval; lane 267 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c for (lane = 0; lane < lane_count; lane++) lane 268 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c dp->link_train.cr_loop[lane] = 0; lane 288 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c for (lane = 0; lane < lane_count; lane++) lane 290 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c PRE_EMPHASIS_LEVEL_0, lane); lane 314 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c for (lane = 0; lane < lane_count; lane++) lane 315 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 | lane 326 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane) lane 328 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c int shift = (lane & 1) * 4; lane 329 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c u8 link_value = link_status[lane >> 1]; lane 336 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c int lane; lane 339 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c for (lane = 0; lane < lane_count; lane++) { lane 340 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c lane_status = analogix_dp_get_lane_status(link_status, lane); lane 350 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c int lane; lane 356 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c for (lane = 0; lane < lane_count; lane++) { lane 357 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c lane_status = analogix_dp_get_lane_status(link_status, lane); lane 367 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane) lane 369 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c int shift = (lane & 1) * 4; lane 370 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c u8 link_value = adjust_request[lane >> 1]; lane 377 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c int lane) lane 379 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c int shift = (lane & 1) * 4; lane 380 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c u8 link_value = adjust_request[lane >> 1]; lane 386 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c u8 training_lane_set, int lane) lane 388 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c switch (lane) { lane 408 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c int lane) lane 412 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c switch (lane) { lane 444 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c int lane, lane_count; lane 448 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c for (lane = 0; lane < lane_count; lane++) { lane 450 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c adjust_request, lane); lane 452 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c adjust_request, lane); lane 461 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c dp->link_train.training_lane[lane] = training_lane; lane 467 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c int lane, lane_count, retval; lane 497 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c for (lane = 0; lane < lane_count; lane++) { lane 499 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c dp, lane); lane 501 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c adjust_request, lane); lane 503 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c adjust_request, lane); lane 509 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c dp->link_train.cr_loop[lane]++; lane 511 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP || lane 515 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c dp->link_train.cr_loop[lane], lane 525 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c for (lane = 0; lane < lane_count; lane++) lane 527 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c dp->link_train.training_lane[lane], lane); lane 539 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c int lane, lane_count, retval; lane 599 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c for (lane = 0; lane < lane_count; lane++) lane 601 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c dp->link_train.training_lane[lane], lane); lane 54 drivers/gpu/drm/drm_dp_helper.c int lane) lane 56 drivers/gpu/drm/drm_dp_helper.c int i = DP_LANE0_1_STATUS + (lane >> 1); lane 57 drivers/gpu/drm/drm_dp_helper.c int s = (lane & 1) * 4; lane 67 drivers/gpu/drm/drm_dp_helper.c int lane; lane 73 drivers/gpu/drm/drm_dp_helper.c for (lane = 0; lane < lane_count; lane++) { lane 74 drivers/gpu/drm/drm_dp_helper.c lane_status = dp_get_lane_status(link_status, lane); lane 85 drivers/gpu/drm/drm_dp_helper.c int lane; lane 88 drivers/gpu/drm/drm_dp_helper.c for (lane = 0; lane < lane_count; lane++) { lane 89 drivers/gpu/drm/drm_dp_helper.c lane_status = dp_get_lane_status(link_status, lane); lane 98 drivers/gpu/drm/drm_dp_helper.c int lane) lane 100 drivers/gpu/drm/drm_dp_helper.c int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); lane 101 drivers/gpu/drm/drm_dp_helper.c int s = ((lane & 1) ? lane 111 drivers/gpu/drm/drm_dp_helper.c int lane) lane 113 drivers/gpu/drm/drm_dp_helper.c int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); lane 114 drivers/gpu/drm/drm_dp_helper.c int s = ((lane & 1) ? lane 759 drivers/gpu/drm/exynos/exynos_drm_dsi.c static void exynos_dsi_enable_lane(struct exynos_dsi *dsi, u32 lane) lane 763 drivers/gpu/drm/exynos/exynos_drm_dsi.c DSIM_LANE_EN(lane)); lane 1250 drivers/gpu/drm/gma500/cdv_intel_dp.c int lane) lane 1252 drivers/gpu/drm/gma500/cdv_intel_dp.c int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); lane 1253 drivers/gpu/drm/gma500/cdv_intel_dp.c int s = ((lane & 1) ? lane 1263 drivers/gpu/drm/gma500/cdv_intel_dp.c int lane) lane 1265 drivers/gpu/drm/gma500/cdv_intel_dp.c int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); lane 1266 drivers/gpu/drm/gma500/cdv_intel_dp.c int s = ((lane & 1) ? lane 1311 drivers/gpu/drm/gma500/cdv_intel_dp.c int lane; lane 1313 drivers/gpu/drm/gma500/cdv_intel_dp.c for (lane = 0; lane < intel_dp->lane_count; lane++) { lane 1314 drivers/gpu/drm/gma500/cdv_intel_dp.c uint8_t this_v = cdv_intel_get_adjust_request_voltage(intel_dp->link_status, lane); lane 1315 drivers/gpu/drm/gma500/cdv_intel_dp.c uint8_t this_p = cdv_intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane); lane 1329 drivers/gpu/drm/gma500/cdv_intel_dp.c for (lane = 0; lane < 4; lane++) lane 1330 drivers/gpu/drm/gma500/cdv_intel_dp.c intel_dp->train_set[lane] = v | p; lane 1336 drivers/gpu/drm/gma500/cdv_intel_dp.c int lane) lane 1338 drivers/gpu/drm/gma500/cdv_intel_dp.c int i = DP_LANE0_1_STATUS + (lane >> 1); lane 1339 drivers/gpu/drm/gma500/cdv_intel_dp.c int s = (lane & 1) * 4; lane 1349 drivers/gpu/drm/gma500/cdv_intel_dp.c int lane; lane 1352 drivers/gpu/drm/gma500/cdv_intel_dp.c for (lane = 0; lane < lane_count; lane++) { lane 1353 drivers/gpu/drm/gma500/cdv_intel_dp.c lane_status = cdv_intel_get_lane_status(link_status, lane); lane 1370 drivers/gpu/drm/gma500/cdv_intel_dp.c int lane; lane 1376 drivers/gpu/drm/gma500/cdv_intel_dp.c for (lane = 0; lane < intel_dp->lane_count; lane++) { lane 1377 drivers/gpu/drm/gma500/cdv_intel_dp.c lane_status = cdv_intel_get_lane_status(intel_dp->link_status, lane); lane 207 drivers/gpu/drm/i915/display/icl_dsi.c int lane; lane 252 drivers/gpu/drm/i915/display/icl_dsi.c for (lane = 0; lane <= 3; lane++) { lane 254 drivers/gpu/drm/i915/display/icl_dsi.c tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, phy)); lane 260 drivers/gpu/drm/i915/display/icl_dsi.c I915_WRITE(ICL_PORT_TX_DW4_LN(lane, phy), tmp); lane 379 drivers/gpu/drm/i915/display/icl_dsi.c int lane; lane 386 drivers/gpu/drm/i915/display/icl_dsi.c for (lane = 0; lane <= 3; lane++) { lane 387 drivers/gpu/drm/i915/display/icl_dsi.c tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, phy)); lane 389 drivers/gpu/drm/i915/display/icl_dsi.c if (lane != 2) lane 391 drivers/gpu/drm/i915/display/icl_dsi.c I915_WRITE(ICL_PORT_TX_DW4_LN(lane, phy), tmp); lane 7259 drivers/gpu/drm/i915/display/intel_display.c int lane, link_bw, fdi_dotclock, ret; lane 7274 drivers/gpu/drm/i915/display/intel_display.c lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, lane 7277 drivers/gpu/drm/i915/display/intel_display.c pipe_config->fdi_lanes = lane; lane 7279 drivers/gpu/drm/i915/display/intel_display.c intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, lane 43 drivers/gpu/drm/i915/display/intel_dp_link_training.c int lane; lane 47 drivers/gpu/drm/i915/display/intel_dp_link_training.c for (lane = 0; lane < intel_dp->lane_count; lane++) { lane 48 drivers/gpu/drm/i915/display/intel_dp_link_training.c u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane); lane 49 drivers/gpu/drm/i915/display/intel_dp_link_training.c u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); lane 65 drivers/gpu/drm/i915/display/intel_dp_link_training.c for (lane = 0; lane < 4; lane++) lane 66 drivers/gpu/drm/i915/display/intel_dp_link_training.c intel_dp->train_set[lane] = v | p; lane 119 drivers/gpu/drm/i915/display/intel_dp_link_training.c int lane; lane 121 drivers/gpu/drm/i915/display/intel_dp_link_training.c for (lane = 0; lane < intel_dp->lane_count; lane++) lane 122 drivers/gpu/drm/i915/display/intel_dp_link_training.c if ((intel_dp->train_set[lane] & lane 597 drivers/gpu/drm/i915/display/intel_dpio_phy.c int lane; lane 601 drivers/gpu/drm/i915/display/intel_dpio_phy.c for (lane = 0; lane < 4; lane++) { lane 602 drivers/gpu/drm/i915/display/intel_dpio_phy.c u32 val = I915_READ(BXT_PORT_TX_DW14_LN(phy, ch, lane)); lane 609 drivers/gpu/drm/i915/display/intel_dpio_phy.c if (lane_lat_optim_mask & BIT(lane)) lane 612 drivers/gpu/drm/i915/display/intel_dpio_phy.c I915_WRITE(BXT_PORT_TX_DW14_LN(phy, ch, lane), val); lane 623 drivers/gpu/drm/i915/display/intel_dpio_phy.c int lane; lane 629 drivers/gpu/drm/i915/display/intel_dpio_phy.c for (lane = 0; lane < 4; lane++) { lane 630 drivers/gpu/drm/i915/display/intel_dpio_phy.c u32 val = I915_READ(BXT_PORT_TX_DW14_LN(phy, ch, lane)); lane 633 drivers/gpu/drm/i915/display/intel_dpio_phy.c mask |= BIT(lane); lane 1599 drivers/gpu/drm/i915/i915_reg.h #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \ lane 1600 drivers/gpu/drm/i915/i915_reg.h (lane) * 0x200 + (offset)) lane 1602 drivers/gpu/drm/i915/i915_reg.h #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80) lane 1603 drivers/gpu/drm/i915/i915_reg.h #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84) lane 1604 drivers/gpu/drm/i915/i915_reg.h #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88) lane 1605 drivers/gpu/drm/i915/i915_reg.h #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c) lane 1606 drivers/gpu/drm/i915/i915_reg.h #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90) lane 1607 drivers/gpu/drm/i915/i915_reg.h #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94) lane 1608 drivers/gpu/drm/i915/i915_reg.h #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98) lane 1609 drivers/gpu/drm/i915/i915_reg.h #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c) lane 1610 drivers/gpu/drm/i915/i915_reg.h #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0) lane 1611 drivers/gpu/drm/i915/i915_reg.h #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4) lane 1612 drivers/gpu/drm/i915/i915_reg.h #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8) lane 1613 drivers/gpu/drm/i915/i915_reg.h #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac) lane 1615 drivers/gpu/drm/i915/i915_reg.h #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8) lane 2245 drivers/gpu/drm/i915/i915_reg.h #define _BXT_LANE_OFFSET(lane) (((lane) >> 1) * 0x200 + \ lane 2246 drivers/gpu/drm/i915/i915_reg.h ((lane) & 1) * 0x80) lane 2315 drivers/gpu/drm/i915/i915_reg.h #define BXT_PORT_TX_DW14_LN(phy, ch, lane) \ lane 2318 drivers/gpu/drm/i915/i915_reg.h _BXT_LANE_OFFSET(lane)) lane 407 drivers/gpu/drm/msm/edp/edp_ctrl.c u8 lane; lane 425 drivers/gpu/drm/msm/edp/edp_ctrl.c for (lane = 1; lane <= max_lane; lane <<= 1) { lane 431 drivers/gpu/drm/msm/edp/edp_ctrl.c ctrl->lane_cnt = lane; lane 699 drivers/gpu/drm/msm/edp/edp_ctrl.c u8 rate, lane, max_lane; lane 703 drivers/gpu/drm/msm/edp/edp_ctrl.c lane = ctrl->lane_cnt; lane 717 drivers/gpu/drm/msm/edp/edp_ctrl.c if (lane >= 1 && lane < max_lane) lane 718 drivers/gpu/drm/msm/edp/edp_ctrl.c lane <<= 1; /* increase lane */ lane 723 drivers/gpu/drm/msm/edp/edp_ctrl.c lrate *= lane; lane 726 drivers/gpu/drm/msm/edp/edp_ctrl.c lrate, prate, rate, lane, lane 732 drivers/gpu/drm/msm/edp/edp_ctrl.c ctrl->lane_cnt = lane; lane 733 drivers/gpu/drm/msm/edp/edp_ctrl.c DBG("new rate=%d %d", rate, lane); lane 86 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c u8 lane = (lt->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf; lane 88 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c u8 lpre = (lane & 0x0c) >> 2; lane 89 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c u8 lvsw = (lane & 0x03) >> 0; lane 173 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c u8 lane = (lt->stat[i >> 1] >> ((i & 1) * 4)) & 0xf; lane 174 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c if (!(lane & DPCD_LS02_LANE0_CR_DONE)) lane 176 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c if (!(lane & DPCD_LS02_LANE0_CHANNEL_EQ_DONE) || lane 177 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c !(lane & DPCD_LS02_LANE0_SYMBOL_LOCKED)) lane 201 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c u8 lane = (lt->stat[i >> 1] >> ((i & 1) * 4)) & 0xf; lane 202 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c if (!(lane & DPCD_LS02_LANE0_CR_DONE)) { lane 487 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c u8 lane = (stat[i >> 1] >> ((i & 1) * 4)) & 0x0f; lane 488 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c if (!(lane & DPCD_LS02_LANE0_CR_DONE) || lane 489 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c !(lane & DPCD_LS02_LANE0_CHANNEL_EQ_DONE) || lane 490 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c !(lane & DPCD_LS02_LANE0_SYMBOL_LOCKED)) { lane 492 drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.c "lane %d not equalised", lane); lane 3692 drivers/gpu/drm/omapdrm/dss/dsi.c u8 lane, pol; lane 3714 drivers/gpu/drm/omapdrm/dss/dsi.c lane = dx / 2; lane 3716 drivers/gpu/drm/omapdrm/dss/dsi.c lanes[lane].function = functions[i / 2]; lane 3717 drivers/gpu/drm/omapdrm/dss/dsi.c lanes[lane].polarity = pol; lane 37 drivers/gpu/drm/omapdrm/dss/hdmi_phy.c u8 lane, pol; lane 59 drivers/gpu/drm/omapdrm/dss/hdmi_phy.c lane = dx / 2; lane 61 drivers/gpu/drm/omapdrm/dss/hdmi_phy.c phy->lane_function[lane] = i / 2; lane 62 drivers/gpu/drm/omapdrm/dss/hdmi_phy.c phy->lane_polarity[lane] = pol; lane 262 drivers/gpu/drm/radeon/atombios_dp.c int lane; lane 264 drivers/gpu/drm/radeon/atombios_dp.c for (lane = 0; lane < lane_count; lane++) { lane 265 drivers/gpu/drm/radeon/atombios_dp.c u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane); lane 266 drivers/gpu/drm/radeon/atombios_dp.c u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); lane 269 drivers/gpu/drm/radeon/atombios_dp.c lane, lane 289 drivers/gpu/drm/radeon/atombios_dp.c for (lane = 0; lane < 4; lane++) lane 290 drivers/gpu/drm/radeon/atombios_dp.c train_set[lane] = v | p; lane 653 drivers/gpu/drm/tegra/sor.c unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | lane 656 drivers/gpu/drm/tegra/sor.c value = (value << 8) | lane; lane 674 drivers/gpu/drm/tegra/sor.c unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | lane 677 drivers/gpu/drm/tegra/sor.c value = (value << 8) | lane; lane 689 drivers/gpu/drm/tegra/sor.c unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | lane 692 drivers/gpu/drm/tegra/sor.c value = (value << 8) | lane; lane 1883 drivers/gpu/drm/tegra/sor.c unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | lane 1886 drivers/gpu/drm/tegra/sor.c value = (value << 8) | lane; lane 1928 drivers/gpu/drm/tegra/sor.c unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | lane 1931 drivers/gpu/drm/tegra/sor.c value = (value << 8) | lane; lane 54 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_REG_CSIRX_DLY_CNT_TERMEN(lane) \ lane 55 drivers/media/pci/intel/ipu3/ipu3-cio2.h (CIO2_REG_CSIRX_BASE + 0x2c + 8 * (lane)) lane 56 drivers/media/pci/intel/ipu3/ipu3-cio2.h #define CIO2_REG_CSIRX_DLY_CNT_SETTLE(lane) \ lane 57 drivers/media/pci/intel/ipu3/ipu3-cio2.h (CIO2_REG_CSIRX_BASE + 0x30 + 8 * (lane)) lane 289 drivers/media/platform/marvell-ccic/mcam-core.c if (mcam->lane > 4 || mcam->lane <= 0) { lane 291 drivers/media/platform/marvell-ccic/mcam-core.c mcam->lane = 1; /* set the default value */ lane 300 drivers/media/platform/marvell-ccic/mcam-core.c CSI2_C0_MIPI_EN | CSI2_C0_ACT_LANE(mcam->lane)); lane 125 drivers/media/platform/marvell-ccic/mcam-core.h int lane; /* lane number */ lane 242 drivers/media/platform/marvell-ccic/mmp-driver.c mcam->lane = pdata->lane; lane 604 drivers/media/platform/ti-vpe/cal.c int lane; lane 608 drivers/media/platform/ti-vpe/cal.c for (lane = 0; lane < mipi_csi2->num_data_lanes; lane++) { lane 615 drivers/media/platform/ti-vpe/cal.c set_field(&val, mipi_csi2->data_lanes[lane] + 1, lane_mask); lane 616 drivers/media/platform/ti-vpe/cal.c set_field(&val, mipi_csi2->lane_polarities[lane + 1], lane 1645 drivers/media/platform/ti-vpe/cal.c int ret, index, found_port = 0, lane; lane 1714 drivers/media/platform/ti-vpe/cal.c for (lane = 0; lane < endpoint->bus.mipi_csi2.num_data_lanes; lane++) lane 1716 drivers/media/platform/ti-vpe/cal.c endpoint->bus.mipi_csi2.data_lanes[lane]); lane 37 drivers/net/dsa/b53/b53_serdes.c static void b53_serdes_set_lane(struct b53_device *dev, u8 lane) lane 39 drivers/net/dsa/b53/b53_serdes.c if (dev->serdes_lane == lane) lane 42 drivers/net/dsa/b53/b53_serdes.c WARN_ON(lane > 1); lane 45 drivers/net/dsa/b53/b53_serdes.c SERDES_XGXSBLK0_BLOCKADDRESS, lane); lane 46 drivers/net/dsa/b53/b53_serdes.c dev->serdes_lane = lane; lane 49 drivers/net/dsa/b53/b53_serdes.c static void b53_serdes_write(struct b53_device *dev, u8 lane, lane 52 drivers/net/dsa/b53/b53_serdes.c b53_serdes_set_lane(dev, lane); lane 56 drivers/net/dsa/b53/b53_serdes.c static u16 b53_serdes_read(struct b53_device *dev, u8 lane, lane 59 drivers/net/dsa/b53/b53_serdes.c b53_serdes_set_lane(dev, lane); lane 66 drivers/net/dsa/b53/b53_serdes.c u8 lane = b53_serdes_map_lane(dev, port); lane 69 drivers/net/dsa/b53/b53_serdes.c if (lane == B53_INVALID_LANE) lane 72 drivers/net/dsa/b53/b53_serdes.c reg = b53_serdes_read(dev, lane, B53_SERDES_DIGITAL_CONTROL(1), lane 78 drivers/net/dsa/b53/b53_serdes.c b53_serdes_write(dev, lane, B53_SERDES_DIGITAL_CONTROL(1), lane 85 drivers/net/dsa/b53/b53_serdes.c u8 lane = b53_serdes_map_lane(dev, port); lane 88 drivers/net/dsa/b53/b53_serdes.c if (lane == B53_INVALID_LANE) lane 91 drivers/net/dsa/b53/b53_serdes.c reg = b53_serdes_read(dev, lane, B53_SERDES_MII_REG(MII_BMCR), lane 94 drivers/net/dsa/b53/b53_serdes.c b53_serdes_write(dev, lane, B53_SERDES_MII_REG(MII_BMCR), lane 102 drivers/net/dsa/b53/b53_serdes.c u8 lane = b53_serdes_map_lane(dev, port); lane 105 drivers/net/dsa/b53/b53_serdes.c if (lane == B53_INVALID_LANE) lane 108 drivers/net/dsa/b53/b53_serdes.c dig = b53_serdes_read(dev, lane, B53_SERDES_DIGITAL_STATUS, lane 110 drivers/net/dsa/b53/b53_serdes.c bmsr = b53_serdes_read(dev, lane, B53_SERDES_MII_REG(MII_BMSR), lane 144 drivers/net/dsa/b53/b53_serdes.c u8 lane = b53_serdes_map_lane(dev, port); lane 147 drivers/net/dsa/b53/b53_serdes.c if (lane == B53_INVALID_LANE) lane 150 drivers/net/dsa/b53/b53_serdes.c reg = b53_serdes_read(dev, lane, B53_SERDES_MII_REG(MII_BMCR), lane 156 drivers/net/dsa/b53/b53_serdes.c b53_serdes_write(dev, lane, B53_SERDES_MII_REG(MII_BMCR), lane 165 drivers/net/dsa/b53/b53_serdes.c u8 lane = b53_serdes_map_lane(dev, port); lane 167 drivers/net/dsa/b53/b53_serdes.c if (lane == B53_INVALID_LANE) lane 170 drivers/net/dsa/b53/b53_serdes.c switch (lane) { lane 185 drivers/net/dsa/b53/b53_serdes.c u8 lane = b53_serdes_map_lane(dev, port); lane 188 drivers/net/dsa/b53/b53_serdes.c if (lane == B53_INVALID_LANE) lane 191 drivers/net/dsa/b53/b53_serdes.c id0 = b53_serdes_read(dev, lane, B53_SERDES_ID0, SERDES_ID0); lane 192 drivers/net/dsa/b53/b53_serdes.c msb = b53_serdes_read(dev, lane, B53_SERDES_MII_REG(MII_PHYSID1), lane 194 drivers/net/dsa/b53/b53_serdes.c lsb = b53_serdes_read(dev, lane, B53_SERDES_MII_REG(MII_PHYSID2), lane 203 drivers/net/dsa/b53/b53_serdes.c lane, id0 & SERDES_ID0_MODEL_MASK, lane 2271 drivers/net/dsa/mv88e6xxx/chip.c u8 lane; lane 2274 drivers/net/dsa/mv88e6xxx/chip.c lane = mv88e6xxx_serdes_get_lane(chip, port); lane 2275 drivers/net/dsa/mv88e6xxx/chip.c if (lane) lane 2276 drivers/net/dsa/mv88e6xxx/chip.c ret = mv88e6xxx_serdes_irq_status(chip, port, lane); lane 2283 drivers/net/dsa/mv88e6xxx/chip.c u8 lane) lane 2304 drivers/net/dsa/mv88e6xxx/chip.c return mv88e6xxx_serdes_irq_enable(chip, port, lane); lane 2308 drivers/net/dsa/mv88e6xxx/chip.c u8 lane) lane 2318 drivers/net/dsa/mv88e6xxx/chip.c err = mv88e6xxx_serdes_irq_disable(chip, port, lane); lane 2333 drivers/net/dsa/mv88e6xxx/chip.c u8 lane; lane 2336 drivers/net/dsa/mv88e6xxx/chip.c lane = mv88e6xxx_serdes_get_lane(chip, port); lane 2337 drivers/net/dsa/mv88e6xxx/chip.c if (!lane) lane 2341 drivers/net/dsa/mv88e6xxx/chip.c err = mv88e6xxx_serdes_power_up(chip, port, lane); lane 2345 drivers/net/dsa/mv88e6xxx/chip.c err = mv88e6xxx_serdes_irq_request(chip, port, lane); lane 2347 drivers/net/dsa/mv88e6xxx/chip.c err = mv88e6xxx_serdes_irq_free(chip, port, lane); lane 2351 drivers/net/dsa/mv88e6xxx/chip.c err = mv88e6xxx_serdes_power_down(chip, port, lane); lane 479 drivers/net/dsa/mv88e6xxx/chip.h int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, u8 lane, lane 488 drivers/net/dsa/mv88e6xxx/chip.h int (*serdes_irq_enable)(struct mv88e6xxx_chip *chip, int port, u8 lane, lane 491 drivers/net/dsa/mv88e6xxx/chip.h u8 lane); lane 398 drivers/net/dsa/mv88e6xxx/port.c u8 lane; lane 434 drivers/net/dsa/mv88e6xxx/port.c lane = mv88e6xxx_serdes_get_lane(chip, port); lane 435 drivers/net/dsa/mv88e6xxx/port.c if (lane) { lane 437 drivers/net/dsa/mv88e6xxx/port.c err = mv88e6xxx_serdes_irq_disable(chip, port, lane); lane 442 drivers/net/dsa/mv88e6xxx/port.c err = mv88e6xxx_serdes_power_down(chip, port, lane); lane 463 drivers/net/dsa/mv88e6xxx/port.c lane = mv88e6xxx_serdes_get_lane(chip, port); lane 464 drivers/net/dsa/mv88e6xxx/port.c if (!lane) lane 467 drivers/net/dsa/mv88e6xxx/port.c err = mv88e6xxx_serdes_power_up(chip, port, lane); lane 472 drivers/net/dsa/mv88e6xxx/port.c err = mv88e6xxx_serdes_irq_enable(chip, port, lane); lane 37 drivers/net/dsa/mv88e6xxx/serdes.c int lane, int device, int reg, u16 *val) lane 41 drivers/net/dsa/mv88e6xxx/serdes.c return mv88e6xxx_phy_read(chip, lane, reg_c45, val); lane 45 drivers/net/dsa/mv88e6xxx/serdes.c int lane, int device, int reg, u16 val) lane 49 drivers/net/dsa/mv88e6xxx/serdes.c return mv88e6xxx_phy_write(chip, lane, reg_c45, val); lane 52 drivers/net/dsa/mv88e6xxx/serdes.c int mv88e6352_serdes_power(struct mv88e6xxx_chip *chip, int port, u8 lane, lane 76 drivers/net/dsa/mv88e6xxx/serdes.c u8 lane = 0; lane 81 drivers/net/dsa/mv88e6xxx/serdes.c lane = 0xff; /* Unused */ lane 83 drivers/net/dsa/mv88e6xxx/serdes.c return lane; lane 206 drivers/net/dsa/mv88e6xxx/serdes.c u8 lane) lane 224 drivers/net/dsa/mv88e6xxx/serdes.c int mv88e6352_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, u8 lane, lane 243 drivers/net/dsa/mv88e6xxx/serdes.c u8 lane = 0; lane 250 drivers/net/dsa/mv88e6xxx/serdes.c lane = MV88E6341_PORT5_LANE; lane 254 drivers/net/dsa/mv88e6xxx/serdes.c return lane; lane 260 drivers/net/dsa/mv88e6xxx/serdes.c u8 lane = 0; lane 267 drivers/net/dsa/mv88e6xxx/serdes.c lane = MV88E6390_PORT9_LANE0; lane 273 drivers/net/dsa/mv88e6xxx/serdes.c lane = MV88E6390_PORT10_LANE0; lane 277 drivers/net/dsa/mv88e6xxx/serdes.c return lane; lane 285 drivers/net/dsa/mv88e6xxx/serdes.c u8 lane = 0; lane 293 drivers/net/dsa/mv88e6xxx/serdes.c lane = MV88E6390_PORT9_LANE1; lane 301 drivers/net/dsa/mv88e6xxx/serdes.c lane = MV88E6390_PORT9_LANE2; lane 309 drivers/net/dsa/mv88e6xxx/serdes.c lane = MV88E6390_PORT9_LANE3; lane 316 drivers/net/dsa/mv88e6xxx/serdes.c lane = MV88E6390_PORT10_LANE1; lane 324 drivers/net/dsa/mv88e6xxx/serdes.c lane = MV88E6390_PORT10_LANE2; lane 332 drivers/net/dsa/mv88e6xxx/serdes.c lane = MV88E6390_PORT10_LANE3; lane 340 drivers/net/dsa/mv88e6xxx/serdes.c lane = MV88E6390_PORT9_LANE0; lane 348 drivers/net/dsa/mv88e6xxx/serdes.c lane = MV88E6390_PORT10_LANE0; lane 352 drivers/net/dsa/mv88e6xxx/serdes.c return lane; lane 356 drivers/net/dsa/mv88e6xxx/serdes.c static int mv88e6390_serdes_power_10g(struct mv88e6xxx_chip *chip, u8 lane, lane 362 drivers/net/dsa/mv88e6xxx/serdes.c err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS, lane 376 drivers/net/dsa/mv88e6xxx/serdes.c err = mv88e6390_serdes_write(chip, lane, MDIO_MMD_PHYXS, lane 383 drivers/net/dsa/mv88e6xxx/serdes.c static int mv88e6390_serdes_power_sgmii(struct mv88e6xxx_chip *chip, u8 lane, lane 389 drivers/net/dsa/mv88e6xxx/serdes.c err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS, lane 402 drivers/net/dsa/mv88e6xxx/serdes.c err = mv88e6390_serdes_write(chip, lane, MDIO_MMD_PHYXS, lane 408 drivers/net/dsa/mv88e6xxx/serdes.c int mv88e6390_serdes_power(struct mv88e6xxx_chip *chip, int port, u8 lane, lane 417 drivers/net/dsa/mv88e6xxx/serdes.c return mv88e6390_serdes_power_sgmii(chip, lane, up); lane 420 drivers/net/dsa/mv88e6xxx/serdes.c return mv88e6390_serdes_power_10g(chip, lane, up); lane 427 drivers/net/dsa/mv88e6xxx/serdes.c int port, u8 lane) lane 437 drivers/net/dsa/mv88e6xxx/serdes.c err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS, lane 494 drivers/net/dsa/mv88e6xxx/serdes.c u8 lane, bool enable) lane 502 drivers/net/dsa/mv88e6xxx/serdes.c return mv88e6390_serdes_write(chip, lane, MDIO_MMD_PHYXS, lane 506 drivers/net/dsa/mv88e6xxx/serdes.c int mv88e6390_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, u8 lane, lane 515 drivers/net/dsa/mv88e6xxx/serdes.c return mv88e6390_serdes_irq_enable_sgmii(chip, lane, enable); lane 522 drivers/net/dsa/mv88e6xxx/serdes.c u8 lane, u16 *status) lane 526 drivers/net/dsa/mv88e6xxx/serdes.c err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS, lane 533 drivers/net/dsa/mv88e6xxx/serdes.c u8 lane) lane 544 drivers/net/dsa/mv88e6xxx/serdes.c err = mv88e6390_serdes_irq_status_sgmii(chip, lane, &status); lane 550 drivers/net/dsa/mv88e6xxx/serdes.c mv88e6390_serdes_irq_link_sgmii(chip, port, lane); lane 85 drivers/net/dsa/mv88e6xxx/serdes.h int mv88e6352_serdes_power(struct mv88e6xxx_chip *chip, int port, u8 lane, lane 87 drivers/net/dsa/mv88e6xxx/serdes.h int mv88e6390_serdes_power(struct mv88e6xxx_chip *chip, int port, u8 lane, lane 89 drivers/net/dsa/mv88e6xxx/serdes.h int mv88e6352_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, u8 lane, lane 91 drivers/net/dsa/mv88e6xxx/serdes.h int mv88e6390_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, u8 lane, lane 94 drivers/net/dsa/mv88e6xxx/serdes.h u8 lane); lane 96 drivers/net/dsa/mv88e6xxx/serdes.h u8 lane); lane 114 drivers/net/dsa/mv88e6xxx/serdes.h int port, u8 lane) lane 119 drivers/net/dsa/mv88e6xxx/serdes.h return chip->info->ops->serdes_power(chip, port, lane, true); lane 123 drivers/net/dsa/mv88e6xxx/serdes.h int port, u8 lane) lane 128 drivers/net/dsa/mv88e6xxx/serdes.h return chip->info->ops->serdes_power(chip, port, lane, false); lane 141 drivers/net/dsa/mv88e6xxx/serdes.h int port, u8 lane) lane 146 drivers/net/dsa/mv88e6xxx/serdes.h return chip->info->ops->serdes_irq_enable(chip, port, lane, true); lane 150 drivers/net/dsa/mv88e6xxx/serdes.h int port, u8 lane) lane 155 drivers/net/dsa/mv88e6xxx/serdes.h return chip->info->ops->serdes_irq_enable(chip, port, lane, false); lane 159 drivers/net/dsa/mv88e6xxx/serdes.h mv88e6xxx_serdes_irq_status(struct mv88e6xxx_chip *chip, int port, u8 lane) lane 164 drivers/net/dsa/mv88e6xxx/serdes.h return chip->info->ops->serdes_irq_status(chip, port, lane); lane 3220 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u8 lane = 0; lane 3251 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c lane = (port<<1) + path; lane 3266 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c lane = path << 1 ; lane 3268 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c return lane; lane 3543 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u8 lane = bnx2x_get_warpcore_lane(phy, params); lane 3550 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c lane; lane 3715 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 lane = bnx2x_get_warpcore_lane(phy, params); lane 3717 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_AER_BLOCK_AER_REG, lane); lane 3728 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 lane, i, cl72_ctrl, an_adv = 0, val; lane 3781 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c lane = bnx2x_get_warpcore_lane(phy, params); lane 3783 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, lane 3788 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_WC_REG_TX0_TX_DRIVER + 0x10*(lane+1), lane 3833 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_AER_BLOCK_AER_REG, lane); lane 3836 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_WC_REG_RX1_PCI_CTRL + (0x10*lane), lane 3852 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4), &val); lane 3862 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c (SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED << lane)) lane 3867 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4), lane 3882 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 val16, i, lane; lane 3900 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c lane = bnx2x_get_warpcore_lane(phy, params); lane 3907 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val16 &= ~(0x0011 << lane); lane 3913 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val16 |= (0x0303 << (lane << 1)); lane 3950 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 misc1_val, tap_val, tx_driver_val, lane, val; lane 4050 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c lane = bnx2x_get_warpcore_lane(phy, params); lane 4055 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, lane 4136 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 lane) lane 4184 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, lane 4290 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 lane) lane 4318 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c lane = bnx2x_get_warpcore_lane(phy, params); lane 4320 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990); lane 4384 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 gp2_status_reg0, lane; lane 4387 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c lane = bnx2x_get_warpcore_lane(phy, params); lane 4392 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c return (gp2_status_reg0 >> (8+lane)) & 0x1; lane 4409 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 lane = bnx2x_get_warpcore_lane(phy, params); lane 4420 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */ lane 4422 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c lnkup_kr = (gp_status1 >> (12+lane)) & 0x1; lane 4451 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 lane = bnx2x_get_warpcore_lane(phy, params); lane 4453 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c bnx2x_warpcore_clear_regs(phy, params, lane); lane 4493 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 lane = bnx2x_get_warpcore_lane(phy, params); lane 4510 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c bnx2x_warpcore_clear_regs(phy, params, lane); lane 4525 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c bnx2x_warpcore_clear_regs(phy, params, lane); lane 4568 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane); lane 4598 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 val16, lane; lane 4623 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c lane = bnx2x_get_warpcore_lane(phy, params); lane 4627 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val16 |= (0x11 << lane); lane 4629 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val16 |= (0x22 << lane); lane 4635 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val16 &= ~(0x0303 << (lane << 1)); lane 4636 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val16 |= (0x0101 << (lane << 1)); lane 4638 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val16 &= ~(0x0c0c << (lane << 1)); lane 4639 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val16 |= (0x0404 << (lane << 1)); lane 4654 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u32 lane; lane 4670 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c lane = bnx2x_get_warpcore_lane(phy, params); lane 4673 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val16 |= (1<<lane); lane 4675 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val16 |= (2<<lane); lane 5693 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u8 lane; lane 5696 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c lane = bnx2x_get_warpcore_lane(phy, params); lane 5726 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c (1 << lane); lane 5742 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if (gp_status4 & ((1<<12)<<lane)) lane 5787 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if (lane < 2) { lane 5794 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed); lane 5796 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c if ((lane & 1) == 0) lane 6462 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u8 lane = bnx2x_get_warpcore_lane(int_phy, params); lane 6468 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c link_up = gp_status & (1 << lane); lane 8628 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u8 lane = bnx2x_get_warpcore_lane(phy, params); lane 8632 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val &= ~(0xf << (lane << 2)); lane 8647 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c val |= (mode << (lane << 2)); lane 13850 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c u16 base_page, next_page, not_kr2_device, lane; lane 13872 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c lane = bnx2x_get_warpcore_lane(phy, params); lane 13874 drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c MDIO_AER_BLOCK_AER_REG, lane); lane 629 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c #define RX_CSR(lane, reg) ((0x4080 + (reg) * 0x0002 + (lane) * 0x0200) * 2) lane 756 drivers/net/ethernet/mellanox/mlxsw/spectrum.c u8 module, u8 width, u8 lane) lane 766 drivers/net/ethernet/mellanox/mlxsw/spectrum.c mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */ lane 3612 drivers/net/ethernet/mellanox/mlxsw/spectrum.c bool split, u8 module, u8 width, u8 lane) lane 3620 drivers/net/ethernet/mellanox/mlxsw/spectrum.c module + 1, split, lane / width, lane 3643 drivers/net/ethernet/mellanox/mlxsw/spectrum.c mlxsw_sp_port->mapping.lane = lane; lane 3668 drivers/net/ethernet/mellanox/mlxsw/spectrum.c err = mlxsw_sp_port_module_map(mlxsw_sp_port, module, width, lane); lane 3941 drivers/net/ethernet/mellanox/mlxsw/spectrum.c u8 module, width, lane; lane 3967 drivers/net/ethernet/mellanox/mlxsw/spectrum.c &width, &lane); lane 3974 drivers/net/ethernet/mellanox/mlxsw/spectrum.c module, width, lane); lane 261 drivers/net/ethernet/mellanox/mlxsw/spectrum.h u8 lane; lane 208 drivers/net/ethernet/sfc/falcon/txc43128_phy.c int lane; lane 242 drivers/net/ethernet/sfc/falcon/txc43128_phy.c for (lane = 0; lane < 4; lane++) { lane 243 drivers/net/ethernet/sfc/falcon/txc43128_phy.c int count = ef4_mdio_read(efx, mmd, TXC_BIST_RX0ERRCNT + lane); lane 246 drivers/net/ethernet/sfc/falcon/txc43128_phy.c "Lane %d had %d errs\n", lane, count); lane 249 drivers/net/ethernet/sfc/falcon/txc43128_phy.c count = ef4_mdio_read(efx, mmd, TXC_BIST_RX0FRMCNT + lane); lane 252 drivers/net/ethernet/sfc/falcon/txc43128_phy.c "Lane %d got 0 frames\n", lane); lane 148 drivers/net/ethernet/ti/netcp_xgbepcsr.c void __iomem *serdes_regs, int lane) lane 156 drivers/net/ethernet/ti/netcp_xgbepcsr.c (0x200 * lane), lane 162 drivers/net/ethernet/ti/netcp_xgbepcsr.c reg_rmw(serdes_regs + (0x200 * lane) + 0x0380, lane 166 drivers/net/ethernet/ti/netcp_xgbepcsr.c reg_rmw(serdes_regs + (0x200 * lane) + 0x03c0, lane 182 drivers/net/ethernet/ti/netcp_xgbepcsr.c void __iomem *serdes_regs, int lane) lane 185 drivers/net/ethernet/ti/netcp_xgbepcsr.c writel(0xe0e9e038, serdes_regs + 0x1fe0 + (4 * lane)); lane 283 drivers/net/ethernet/ti/netcp_xgbepcsr.c void __iomem *sig_detect_reg, int lane) lane 289 drivers/net/ethernet/ti/netcp_xgbepcsr.c serdes_regs, lane + 1, 5); lane 298 drivers/net/ethernet/ti/netcp_xgbepcsr.c tbus = netcp_xgbe_serdes_read_select_tbus(serdes_regs, lane + lane 430 drivers/net/ethernet/ti/netcp_xgbepcsr.c int lane, int cm, int c1, int c2) lane 435 drivers/net/ethernet/ti/netcp_xgbepcsr.c reg_rmw(serdes_regs + cfg_cm_c1_c2[i].ofs + (0x200 * lane), lane 206 drivers/nvdimm/btt.c static int btt_log_group_read(struct arena_info *arena, u32 lane, lane 210 drivers/nvdimm/btt.c arena->logoff + (lane * LOG_GRP_SIZE), log, lane 327 drivers/nvdimm/btt.c static int btt_log_read(struct arena_info *arena, u32 lane, lane 334 drivers/nvdimm/btt.c ret = btt_log_group_read(arena, lane, &log); lane 342 drivers/nvdimm/btt.c old_ent, lane, log.ent[arena->log_index[0]].seq, lane 361 drivers/nvdimm/btt.c static int __btt_log_write(struct arena_info *arena, u32 lane, lane 370 drivers/nvdimm/btt.c ns_off = arena->logoff + (lane * LOG_GRP_SIZE) + lane 382 drivers/nvdimm/btt.c static int btt_flog_write(struct arena_info *arena, u32 lane, u32 sub, lane 387 drivers/nvdimm/btt.c ret = __btt_log_write(arena, lane, sub, ent, NVDIMM_IO_ATOMIC); lane 392 drivers/nvdimm/btt.c arena->freelist[lane].sub = 1 - arena->freelist[lane].sub; lane 393 drivers/nvdimm/btt.c if (++(arena->freelist[lane].seq) == 4) lane 394 drivers/nvdimm/btt.c arena->freelist[lane].seq = 1; lane 396 drivers/nvdimm/btt.c arena->freelist[lane].has_err = 1; lane 397 drivers/nvdimm/btt.c arena->freelist[lane].block = ent_lba(le32_to_cpu(ent->old_map)); lane 505 drivers/nvdimm/btt.c static int arena_clear_freelist_error(struct arena_info *arena, u32 lane) lane 509 drivers/nvdimm/btt.c if (arena->freelist[lane].has_err) { lane 511 drivers/nvdimm/btt.c u32 lba = arena->freelist[lane].block; lane 527 drivers/nvdimm/btt.c arena->freelist[lane].has_err = 0; lane 1204 drivers/nvdimm/btt.c u32 lane = 0, premap, postmap; lane 1209 drivers/nvdimm/btt.c lane = nd_region_acquire_lane(btt->nd_region); lane 1241 drivers/nvdimm/btt.c arena->rtt[lane] = RTT_VALID | postmap; lane 1278 drivers/nvdimm/btt.c arena->rtt[lane] = RTT_INVALID; lane 1279 drivers/nvdimm/btt.c nd_region_release_lane(btt->nd_region, lane); lane 1289 drivers/nvdimm/btt.c arena->rtt[lane] = RTT_INVALID; lane 1291 drivers/nvdimm/btt.c nd_region_release_lane(btt->nd_region, lane); lane 1316 drivers/nvdimm/btt.c u32 premap = 0, old_postmap, new_postmap, lane = 0, i; lane 1325 drivers/nvdimm/btt.c lane = nd_region_acquire_lane(btt->nd_region); lane 1337 drivers/nvdimm/btt.c if (btt_is_badblock(btt, arena, arena->freelist[lane].block)) lane 1338 drivers/nvdimm/btt.c arena->freelist[lane].has_err = 1; lane 1341 drivers/nvdimm/btt.c || arena->freelist[lane].has_err) { lane 1342 drivers/nvdimm/btt.c nd_region_release_lane(btt->nd_region, lane); lane 1344 drivers/nvdimm/btt.c ret = arena_clear_freelist_error(arena, lane); lane 1352 drivers/nvdimm/btt.c new_postmap = arena->freelist[lane].block; lane 1391 drivers/nvdimm/btt.c log.seq = cpu_to_le32(arena->freelist[lane].seq); lane 1392 drivers/nvdimm/btt.c sub = arena->freelist[lane].sub; lane 1393 drivers/nvdimm/btt.c ret = btt_flog_write(arena, lane, sub, &log); lane 1403 drivers/nvdimm/btt.c nd_region_release_lane(btt->nd_region, lane); lane 1406 drivers/nvdimm/btt.c ret = arena_clear_freelist_error(arena, lane); lane 1421 drivers/nvdimm/btt.c nd_region_release_lane(btt->nd_region, lane); lane 157 drivers/nvdimm/nd.h struct nd_percpu_lane __percpu *lane; lane 135 drivers/nvdimm/region_devs.c free_percpu(nd_region->lane); lane 899 drivers/nvdimm/region_devs.c unsigned int cpu, lane; lane 905 drivers/nvdimm/region_devs.c lane = cpu % nd_region->num_lanes; lane 906 drivers/nvdimm/region_devs.c ndl_count = per_cpu_ptr(nd_region->lane, cpu); lane 907 drivers/nvdimm/region_devs.c ndl_lock = per_cpu_ptr(nd_region->lane, lane); lane 911 drivers/nvdimm/region_devs.c lane = cpu; lane 913 drivers/nvdimm/region_devs.c return lane; lane 917 drivers/nvdimm/region_devs.c void nd_region_release_lane(struct nd_region *nd_region, unsigned int lane) lane 923 drivers/nvdimm/region_devs.c ndl_count = per_cpu_ptr(nd_region->lane, cpu); lane 924 drivers/nvdimm/region_devs.c ndl_lock = per_cpu_ptr(nd_region->lane, lane); lane 992 drivers/nvdimm/region_devs.c nd_region->lane = alloc_percpu(struct nd_percpu_lane); lane 993 drivers/nvdimm/region_devs.c if (!nd_region->lane) lane 999 drivers/nvdimm/region_devs.c ndl = per_cpu_ptr(nd_region->lane, i); lane 93 drivers/pci/controller/pci-mvebu.c u32 lane; lane 823 drivers/pci/controller/pci-mvebu.c if (of_property_read_u32(child, "marvell,pcie-lane", &port->lane)) lane 824 drivers/pci/controller/pci-mvebu.c port->lane = 0; lane 827 drivers/pci/controller/pci-mvebu.c port->lane); lane 2163 drivers/pci/controller/pci-tegra.c unsigned int lane = 0; lane 2269 drivers/pci/controller/pci-tegra.c lane += value; lane 2273 drivers/pci/controller/pci-tegra.c mask |= ((1 << value) - 1) << lane; lane 2274 drivers/pci/controller/pci-tegra.c lane += value; lane 516 drivers/pci/controller/pcie-rcar.c unsigned int lane, u32 data) lane 522 drivers/pci/controller/pcie-rcar.c ((lane & 0xf) << LANE_POS) | lane 24 drivers/phy/cadence/cdns-dphy.c #define DPHY_PMA_LDATA(lane, reg) (0x200 + ((lane) * 0x100) + (reg)) lane 26 drivers/phy/cadence/cdns-dphy.c #define DPHY_PMA_RDATA(lane, reg) (0x700 + ((lane) * 0x100) + (reg)) lane 118 drivers/phy/cadence/phy-cadence-dp.c unsigned int lane); lane 348 drivers/phy/cadence/phy-cadence-dp.c unsigned int lane) lane 350 drivers/phy/cadence/phy-cadence-dp.c unsigned int lane_bits = (lane & LANE_MASK) << 11; lane 45 drivers/phy/marvell/phy-armada38x-comphy.c struct a38x_comphy_lane lane[MAX_A38X_COMPHY]; lane 57 drivers/phy/marvell/phy-armada38x-comphy.c static void a38x_comphy_set_reg(struct a38x_comphy_lane *lane, lane 62 drivers/phy/marvell/phy-armada38x-comphy.c val = readl_relaxed(lane->base + offset) & ~mask; lane 63 drivers/phy/marvell/phy-armada38x-comphy.c writel(val | value, lane->base + offset); lane 66 drivers/phy/marvell/phy-armada38x-comphy.c static void a38x_comphy_set_speed(struct a38x_comphy_lane *lane, lane 69 drivers/phy/marvell/phy-armada38x-comphy.c a38x_comphy_set_reg(lane, COMPHY_CFG1, lane 75 drivers/phy/marvell/phy-armada38x-comphy.c static int a38x_comphy_poll(struct a38x_comphy_lane *lane, lane 81 drivers/phy/marvell/phy-armada38x-comphy.c ret = readl_relaxed_poll_timeout_atomic(lane->base + offset, val, lane 86 drivers/phy/marvell/phy-armada38x-comphy.c dev_err(lane->priv->dev, lane 87 drivers/phy/marvell/phy-armada38x-comphy.c "comphy%u: timed out waiting for status\n", lane->n); lane 98 drivers/phy/marvell/phy-armada38x-comphy.c struct a38x_comphy_lane *lane = phy_get_drvdata(phy); lane 118 drivers/phy/marvell/phy-armada38x-comphy.c a38x_comphy_set_speed(lane, gen, gen); lane 120 drivers/phy/marvell/phy-armada38x-comphy.c return a38x_comphy_poll(lane, COMPHY_STAT1, lane 135 drivers/phy/marvell/phy-armada38x-comphy.c struct a38x_comphy_lane *lane; lane 146 drivers/phy/marvell/phy-armada38x-comphy.c lane = phy_get_drvdata(phy); lane 147 drivers/phy/marvell/phy-armada38x-comphy.c if (lane->port >= 0) lane 150 drivers/phy/marvell/phy-armada38x-comphy.c lane->port = args->args[0]; lane 152 drivers/phy/marvell/phy-armada38x-comphy.c val = readl_relaxed(lane->priv->base + COMPHY_SELECTOR); lane 153 drivers/phy/marvell/phy-armada38x-comphy.c val = (val >> (4 * lane->n)) & 0xf; lane 155 drivers/phy/marvell/phy-armada38x-comphy.c if (!gbe_mux[lane->n][lane->port] || lane 156 drivers/phy/marvell/phy-armada38x-comphy.c val != gbe_mux[lane->n][lane->port]) { lane 157 drivers/phy/marvell/phy-armada38x-comphy.c dev_warn(lane->priv->dev, lane 158 drivers/phy/marvell/phy-armada38x-comphy.c "comphy%u: not configured for GBE\n", lane->n); lane 197 drivers/phy/marvell/phy-armada38x-comphy.c if (val >= MAX_A38X_COMPHY || priv->lane[val].base) { lane 208 drivers/phy/marvell/phy-armada38x-comphy.c priv->lane[val].base = base + 0x28 * val; lane 209 drivers/phy/marvell/phy-armada38x-comphy.c priv->lane[val].priv = priv; lane 210 drivers/phy/marvell/phy-armada38x-comphy.c priv->lane[val].n = val; lane 211 drivers/phy/marvell/phy-armada38x-comphy.c priv->lane[val].port = -1; lane 212 drivers/phy/marvell/phy-armada38x-comphy.c phy_set_drvdata(phy, &priv->lane[val]); lane 59 drivers/phy/marvell/phy-mvebu-a3700-comphy.c unsigned int lane; lane 68 drivers/phy/marvell/phy-mvebu-a3700-comphy.c .lane = _lane, \ lane 111 drivers/phy/marvell/phy-mvebu-a3700-comphy.c static int mvebu_a3700_comphy_smc(unsigned long function, unsigned long lane, lane 116 drivers/phy/marvell/phy-mvebu-a3700-comphy.c arm_smccc_smc(function, lane, mode, 0, 0, 0, 0, 0, &res); lane 121 drivers/phy/marvell/phy-mvebu-a3700-comphy.c static int mvebu_a3700_comphy_get_fw_mode(int lane, int port, lane 132 drivers/phy/marvell/phy-mvebu-a3700-comphy.c if (mvebu_a3700_comphy_modes[i].lane == lane && lane 148 drivers/phy/marvell/phy-mvebu-a3700-comphy.c struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy); lane 154 drivers/phy/marvell/phy-mvebu-a3700-comphy.c fw_mode = mvebu_a3700_comphy_get_fw_mode(lane->id, lane->port, mode, lane 157 drivers/phy/marvell/phy-mvebu-a3700-comphy.c dev_err(lane->dev, "invalid COMPHY mode\n"); lane 162 drivers/phy/marvell/phy-mvebu-a3700-comphy.c lane->mode = mode; lane 163 drivers/phy/marvell/phy-mvebu-a3700-comphy.c lane->submode = submode; lane 170 drivers/phy/marvell/phy-mvebu-a3700-comphy.c struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy); lane 175 drivers/phy/marvell/phy-mvebu-a3700-comphy.c fw_mode = mvebu_a3700_comphy_get_fw_mode(lane->id, lane->port, lane 176 drivers/phy/marvell/phy-mvebu-a3700-comphy.c lane->mode, lane->submode); lane 178 drivers/phy/marvell/phy-mvebu-a3700-comphy.c dev_err(lane->dev, "invalid COMPHY mode\n"); lane 182 drivers/phy/marvell/phy-mvebu-a3700-comphy.c switch (lane->mode) { lane 184 drivers/phy/marvell/phy-mvebu-a3700-comphy.c dev_dbg(lane->dev, "set lane %d to USB3 host mode\n", lane->id); lane 188 drivers/phy/marvell/phy-mvebu-a3700-comphy.c dev_dbg(lane->dev, "set lane %d to SATA mode\n", lane->id); lane 192 drivers/phy/marvell/phy-mvebu-a3700-comphy.c switch (lane->submode) { lane 194 drivers/phy/marvell/phy-mvebu-a3700-comphy.c dev_dbg(lane->dev, "set lane %d to SGMII mode\n", lane 195 drivers/phy/marvell/phy-mvebu-a3700-comphy.c lane->id); lane 196 drivers/phy/marvell/phy-mvebu-a3700-comphy.c fw_param = COMPHY_FW_NET(fw_mode, lane->port, lane 200 drivers/phy/marvell/phy-mvebu-a3700-comphy.c dev_dbg(lane->dev, "set lane %d to HS SGMII mode\n", lane 201 drivers/phy/marvell/phy-mvebu-a3700-comphy.c lane->id); lane 202 drivers/phy/marvell/phy-mvebu-a3700-comphy.c fw_param = COMPHY_FW_NET(fw_mode, lane->port, lane 206 drivers/phy/marvell/phy-mvebu-a3700-comphy.c dev_err(lane->dev, "unsupported PHY submode (%d)\n", lane 207 drivers/phy/marvell/phy-mvebu-a3700-comphy.c lane->submode); lane 212 drivers/phy/marvell/phy-mvebu-a3700-comphy.c dev_dbg(lane->dev, "set lane %d to PCIe mode\n", lane->id); lane 213 drivers/phy/marvell/phy-mvebu-a3700-comphy.c fw_param = COMPHY_FW_PCIE(fw_mode, lane->port, lane 218 drivers/phy/marvell/phy-mvebu-a3700-comphy.c dev_err(lane->dev, "unsupported PHY mode (%d)\n", lane->mode); lane 222 drivers/phy/marvell/phy-mvebu-a3700-comphy.c ret = mvebu_a3700_comphy_smc(COMPHY_SIP_POWER_ON, lane->id, fw_param); lane 224 drivers/phy/marvell/phy-mvebu-a3700-comphy.c dev_err(lane->dev, lane 232 drivers/phy/marvell/phy-mvebu-a3700-comphy.c struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy); lane 234 drivers/phy/marvell/phy-mvebu-a3700-comphy.c return mvebu_a3700_comphy_smc(COMPHY_SIP_POWER_OFF, lane->id, 0); lane 247 drivers/phy/marvell/phy-mvebu-a3700-comphy.c struct mvebu_a3700_comphy_lane *lane; lane 257 drivers/phy/marvell/phy-mvebu-a3700-comphy.c lane = phy_get_drvdata(phy); lane 258 drivers/phy/marvell/phy-mvebu-a3700-comphy.c lane->port = args->args[0]; lane 269 drivers/phy/marvell/phy-mvebu-a3700-comphy.c struct mvebu_a3700_comphy_lane *lane; lane 286 drivers/phy/marvell/phy-mvebu-a3700-comphy.c lane = devm_kzalloc(&pdev->dev, sizeof(*lane), GFP_KERNEL); lane 287 drivers/phy/marvell/phy-mvebu-a3700-comphy.c if (!lane) { lane 299 drivers/phy/marvell/phy-mvebu-a3700-comphy.c lane->dev = &pdev->dev; lane 300 drivers/phy/marvell/phy-mvebu-a3700-comphy.c lane->mode = PHY_MODE_INVALID; lane 301 drivers/phy/marvell/phy-mvebu-a3700-comphy.c lane->submode = PHY_INTERFACE_MODE_NA; lane 302 drivers/phy/marvell/phy-mvebu-a3700-comphy.c lane->id = lane_id; lane 303 drivers/phy/marvell/phy-mvebu-a3700-comphy.c lane->port = -1; lane 304 drivers/phy/marvell/phy-mvebu-a3700-comphy.c phy_set_drvdata(phy, lane); lane 181 drivers/phy/marvell/phy-mvebu-cp110-comphy.c unsigned lane; lane 189 drivers/phy/marvell/phy-mvebu-cp110-comphy.c .lane = _lane, \ lane 199 drivers/phy/marvell/phy-mvebu-cp110-comphy.c .lane = _lane, \ lane 273 drivers/phy/marvell/phy-mvebu-cp110-comphy.c unsigned long lane, unsigned long mode) lane 277 drivers/phy/marvell/phy-mvebu-cp110-comphy.c arm_smccc_smc(function, phys, lane, mode, 0, 0, 0, 0, &res); lane 282 drivers/phy/marvell/phy-mvebu-cp110-comphy.c static int mvebu_comphy_get_mode(bool fw_mode, int lane, int port, lane 296 drivers/phy/marvell/phy-mvebu-cp110-comphy.c if (conf->lane == lane && lane 312 drivers/phy/marvell/phy-mvebu-cp110-comphy.c static inline int mvebu_comphy_get_mux(int lane, int port, lane 315 drivers/phy/marvell/phy-mvebu-cp110-comphy.c return mvebu_comphy_get_mode(false, lane, port, mode, submode); lane 318 drivers/phy/marvell/phy-mvebu-cp110-comphy.c static inline int mvebu_comphy_get_fw_mode(int lane, int port, lane 321 drivers/phy/marvell/phy-mvebu-cp110-comphy.c return mvebu_comphy_get_mode(true, lane, port, mode, submode); lane 324 drivers/phy/marvell/phy-mvebu-cp110-comphy.c static int mvebu_comphy_ethernet_init_reset(struct mvebu_comphy_lane *lane) lane 326 drivers/phy/marvell/phy-mvebu-cp110-comphy.c struct mvebu_comphy_priv *priv = lane->priv; lane 329 drivers/phy/marvell/phy-mvebu-cp110-comphy.c regmap_read(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), &val); lane 332 drivers/phy/marvell/phy-mvebu-cp110-comphy.c regmap_write(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), val); lane 335 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id)); lane 344 drivers/phy/marvell/phy-mvebu-cp110-comphy.c switch (lane->submode) { lane 367 drivers/phy/marvell/phy-mvebu-cp110-comphy.c lane->submode, lane 368 drivers/phy/marvell/phy-mvebu-cp110-comphy.c lane->id); lane 372 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id)); lane 374 drivers/phy/marvell/phy-mvebu-cp110-comphy.c if (lane->submode == PHY_INTERFACE_MODE_RXAUI) { lane 377 drivers/phy/marvell/phy-mvebu-cp110-comphy.c switch (lane->id) { lane 389 drivers/phy/marvell/phy-mvebu-cp110-comphy.c lane->id); lane 397 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); lane 401 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); lane 404 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); lane 407 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); lane 413 drivers/phy/marvell/phy-mvebu-cp110-comphy.c regmap_read(priv->regmap, MVEBU_COMPHY_CONF6(lane->id), &val); lane 415 drivers/phy/marvell/phy-mvebu-cp110-comphy.c regmap_write(priv->regmap, MVEBU_COMPHY_CONF6(lane->id), val); lane 418 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id)); lane 420 drivers/phy/marvell/phy-mvebu-cp110-comphy.c if (lane->submode == PHY_INTERFACE_MODE_10GKR) lane 422 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id)); lane 425 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_PWRPLL_CTRL(lane->id)); lane 430 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_PWRPLL_CTRL(lane->id)); lane 432 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_LOOPBACK(lane->id)); lane 435 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_LOOPBACK(lane->id)); lane 440 drivers/phy/marvell/phy-mvebu-cp110-comphy.c static int mvebu_comphy_init_plls(struct mvebu_comphy_lane *lane) lane 442 drivers/phy/marvell/phy-mvebu-cp110-comphy.c struct mvebu_comphy_priv *priv = lane->priv; lane 446 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id)); lane 450 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id)); lane 453 drivers/phy/marvell/phy-mvebu-cp110-comphy.c readl_poll_timeout(priv->base + MVEBU_COMPHY_SERDES_STATUS0(lane->id), lane 463 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); lane 465 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); lane 468 drivers/phy/marvell/phy-mvebu-cp110-comphy.c readl_poll_timeout(priv->base + MVEBU_COMPHY_SERDES_STATUS0(lane->id), lane 474 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); lane 476 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); lane 483 drivers/phy/marvell/phy-mvebu-cp110-comphy.c struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); lane 484 drivers/phy/marvell/phy-mvebu-cp110-comphy.c struct mvebu_comphy_priv *priv = lane->priv; lane 488 drivers/phy/marvell/phy-mvebu-cp110-comphy.c err = mvebu_comphy_ethernet_init_reset(lane); lane 492 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id)); lane 495 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id)); lane 497 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id)); lane 499 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id)); lane 501 drivers/phy/marvell/phy-mvebu-cp110-comphy.c regmap_read(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), &val); lane 504 drivers/phy/marvell/phy-mvebu-cp110-comphy.c regmap_write(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), val); lane 506 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_GEN1_S0(lane->id)); lane 509 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id)); lane 511 drivers/phy/marvell/phy-mvebu-cp110-comphy.c return mvebu_comphy_init_plls(lane); lane 516 drivers/phy/marvell/phy-mvebu-cp110-comphy.c struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); lane 517 drivers/phy/marvell/phy-mvebu-cp110-comphy.c struct mvebu_comphy_priv *priv = lane->priv; lane 521 drivers/phy/marvell/phy-mvebu-cp110-comphy.c err = mvebu_comphy_ethernet_init_reset(lane); lane 525 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id)); lane 528 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id)); lane 530 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id)); lane 532 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id)); lane 534 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id)); lane 536 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id)); lane 538 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_DFE_RES(lane->id)); lane 540 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_DFE_RES(lane->id)); lane 542 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_GEN1_S0(lane->id)); lane 545 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id)); lane 547 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_GEN1_S1(lane->id)); lane 553 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_GEN1_S1(lane->id)); lane 555 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_COEF(lane->id)); lane 557 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_COEF(lane->id)); lane 559 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_GEN1_S4(lane->id)); lane 562 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_GEN1_S4(lane->id)); lane 564 drivers/phy/marvell/phy-mvebu-cp110-comphy.c return mvebu_comphy_init_plls(lane); lane 569 drivers/phy/marvell/phy-mvebu-cp110-comphy.c struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); lane 570 drivers/phy/marvell/phy-mvebu-cp110-comphy.c struct mvebu_comphy_priv *priv = lane->priv; lane 574 drivers/phy/marvell/phy-mvebu-cp110-comphy.c err = mvebu_comphy_ethernet_init_reset(lane); lane 578 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id)); lane 581 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id)); lane 583 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id)); lane 585 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id)); lane 588 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_SPEED_DIV(lane->id)); lane 590 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_SPEED_DIV(lane->id)); lane 592 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id)); lane 594 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id)); lane 597 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_DFE_RES(lane->id)); lane 599 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_DFE_RES(lane->id)); lane 601 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_GEN1_S0(lane->id)); lane 606 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id)); lane 608 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_GEN1_S2(lane->id)); lane 611 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_GEN1_S2(lane->id)); lane 613 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_TX_SLEW_RATE(lane->id)); lane 616 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_TX_SLEW_RATE(lane->id)); lane 619 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_IMP_CAL(lane->id)); lane 623 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_IMP_CAL(lane->id)); lane 625 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_GEN1_S5(lane->id)); lane 627 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_GEN1_S5(lane->id)); lane 629 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_GEN1_S1(lane->id)); lane 639 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_GEN1_S1(lane->id)); lane 641 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_COEF(lane->id)); lane 643 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_COEF(lane->id)); lane 645 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_GEN1_S4(lane->id)); lane 648 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_GEN1_S4(lane->id)); lane 650 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_GEN1_S3(lane->id)); lane 652 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_GEN1_S3(lane->id)); lane 655 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_TRAINING5(lane->id)); lane 658 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_TRAINING5(lane->id)); lane 661 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_TRAINING0(lane->id)); lane 663 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_TRAINING0(lane->id)); lane 665 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_TX_PRESET(lane->id)); lane 668 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_TX_PRESET(lane->id)); lane 670 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_FRAME_DETECT3(lane->id)); lane 672 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_FRAME_DETECT3(lane->id)); lane 674 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_TX_TRAIN_PRESET(lane->id)); lane 677 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_TX_TRAIN_PRESET(lane->id)); lane 679 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_FRAME_DETECT0(lane->id)); lane 682 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_FRAME_DETECT0(lane->id)); lane 684 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_DME(lane->id)); lane 686 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_DME(lane->id)); lane 688 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_VDD_CAL0(lane->id)); lane 690 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_VDD_CAL0(lane->id)); lane 692 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_SP_CALIB(lane->id)); lane 696 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_SP_CALIB(lane->id)); lane 698 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_SP_CALIB(lane->id)); lane 701 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_EXT_SELV(lane->id)); lane 704 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_EXT_SELV(lane->id)); lane 706 drivers/phy/marvell/phy-mvebu-cp110-comphy.c return mvebu_comphy_init_plls(lane); lane 711 drivers/phy/marvell/phy-mvebu-cp110-comphy.c struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); lane 712 drivers/phy/marvell/phy-mvebu-cp110-comphy.c struct mvebu_comphy_priv *priv = lane->priv; lane 716 drivers/phy/marvell/phy-mvebu-cp110-comphy.c mux = mvebu_comphy_get_mux(lane->id, lane->port, lane 717 drivers/phy/marvell/phy-mvebu-cp110-comphy.c lane->mode, lane->submode); lane 722 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val &= ~(0xf << MVEBU_COMPHY_PIPE_SELECTOR_PIPE(lane->id)); lane 726 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val &= ~(0xf << MVEBU_COMPHY_SELECTOR_PHY(lane->id)); lane 727 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val |= mux << MVEBU_COMPHY_SELECTOR_PHY(lane->id); lane 730 drivers/phy/marvell/phy-mvebu-cp110-comphy.c switch (lane->submode) { lane 746 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); lane 748 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); lane 755 drivers/phy/marvell/phy-mvebu-cp110-comphy.c struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); lane 756 drivers/phy/marvell/phy-mvebu-cp110-comphy.c struct mvebu_comphy_priv *priv = lane->priv; lane 761 drivers/phy/marvell/phy-mvebu-cp110-comphy.c fw_mode = mvebu_comphy_get_fw_mode(lane->id, lane->port, lane 762 drivers/phy/marvell/phy-mvebu-cp110-comphy.c lane->mode, lane->submode); lane 767 drivers/phy/marvell/phy-mvebu-cp110-comphy.c switch (lane->mode) { lane 769 drivers/phy/marvell/phy-mvebu-cp110-comphy.c switch (lane->submode) { lane 772 drivers/phy/marvell/phy-mvebu-cp110-comphy.c lane->id); lane 777 drivers/phy/marvell/phy-mvebu-cp110-comphy.c lane->id); lane 782 drivers/phy/marvell/phy-mvebu-cp110-comphy.c lane->id); lane 787 drivers/phy/marvell/phy-mvebu-cp110-comphy.c lane->id); lane 792 drivers/phy/marvell/phy-mvebu-cp110-comphy.c lane->submode); lane 795 drivers/phy/marvell/phy-mvebu-cp110-comphy.c fw_param = COMPHY_FW_PARAM_ETH(fw_mode, lane->port, fw_speed); lane 799 drivers/phy/marvell/phy-mvebu-cp110-comphy.c dev_dbg(priv->dev, "set lane %d to USB3 mode\n", lane->id); lane 800 drivers/phy/marvell/phy-mvebu-cp110-comphy.c fw_param = COMPHY_FW_PARAM(fw_mode, lane->port); lane 803 drivers/phy/marvell/phy-mvebu-cp110-comphy.c dev_dbg(priv->dev, "set lane %d to SATA mode\n", lane->id); lane 804 drivers/phy/marvell/phy-mvebu-cp110-comphy.c fw_param = COMPHY_FW_PARAM(fw_mode, lane->port); lane 807 drivers/phy/marvell/phy-mvebu-cp110-comphy.c dev_dbg(priv->dev, "set lane %d to PCIe mode (x%d)\n", lane->id, lane 808 drivers/phy/marvell/phy-mvebu-cp110-comphy.c lane->submode); lane 809 drivers/phy/marvell/phy-mvebu-cp110-comphy.c fw_param = COMPHY_FW_PARAM_PCIE(fw_mode, lane->port, lane 810 drivers/phy/marvell/phy-mvebu-cp110-comphy.c lane->submode); lane 813 drivers/phy/marvell/phy-mvebu-cp110-comphy.c dev_err(priv->dev, "unsupported PHY mode (%d)\n", lane->mode); lane 817 drivers/phy/marvell/phy-mvebu-cp110-comphy.c ret = mvebu_comphy_smc(COMPHY_SIP_POWER_ON, priv->cp_phys, lane->id, lane 828 drivers/phy/marvell/phy-mvebu-cp110-comphy.c lane->id, lane->mode, ret); lane 838 drivers/phy/marvell/phy-mvebu-cp110-comphy.c struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); lane 843 drivers/phy/marvell/phy-mvebu-cp110-comphy.c if (mvebu_comphy_get_fw_mode(lane->id, lane->port, mode, submode) < 0) lane 846 drivers/phy/marvell/phy-mvebu-cp110-comphy.c lane->mode = mode; lane 847 drivers/phy/marvell/phy-mvebu-cp110-comphy.c lane->submode = submode; lane 850 drivers/phy/marvell/phy-mvebu-cp110-comphy.c if (mode == PHY_MODE_PCIE && !lane->submode) lane 851 drivers/phy/marvell/phy-mvebu-cp110-comphy.c lane->submode = 1; lane 858 drivers/phy/marvell/phy-mvebu-cp110-comphy.c struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); lane 859 drivers/phy/marvell/phy-mvebu-cp110-comphy.c struct mvebu_comphy_priv *priv = lane->priv; lane 862 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); lane 866 drivers/phy/marvell/phy-mvebu-cp110-comphy.c writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id)); lane 869 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val &= ~(0xf << MVEBU_COMPHY_SELECTOR_PHY(lane->id)); lane 873 drivers/phy/marvell/phy-mvebu-cp110-comphy.c val &= ~(0xf << MVEBU_COMPHY_PIPE_SELECTOR_PIPE(lane->id)); lane 881 drivers/phy/marvell/phy-mvebu-cp110-comphy.c struct mvebu_comphy_lane *lane = phy_get_drvdata(phy); lane 882 drivers/phy/marvell/phy-mvebu-cp110-comphy.c struct mvebu_comphy_priv *priv = lane->priv; lane 886 drivers/phy/marvell/phy-mvebu-cp110-comphy.c lane->id, 0); lane 904 drivers/phy/marvell/phy-mvebu-cp110-comphy.c struct mvebu_comphy_lane *lane; lane 914 drivers/phy/marvell/phy-mvebu-cp110-comphy.c lane = phy_get_drvdata(phy); lane 915 drivers/phy/marvell/phy-mvebu-cp110-comphy.c lane->port = args->args[0]; lane 1020 drivers/phy/marvell/phy-mvebu-cp110-comphy.c struct mvebu_comphy_lane *lane; lane 1036 drivers/phy/marvell/phy-mvebu-cp110-comphy.c lane = devm_kzalloc(&pdev->dev, sizeof(*lane), GFP_KERNEL); lane 1037 drivers/phy/marvell/phy-mvebu-cp110-comphy.c if (!lane) { lane 1050 drivers/phy/marvell/phy-mvebu-cp110-comphy.c lane->priv = priv; lane 1051 drivers/phy/marvell/phy-mvebu-cp110-comphy.c lane->mode = PHY_MODE_INVALID; lane 1052 drivers/phy/marvell/phy-mvebu-cp110-comphy.c lane->submode = PHY_INTERFACE_MODE_NA; lane 1053 drivers/phy/marvell/phy-mvebu-cp110-comphy.c lane->id = val; lane 1054 drivers/phy/marvell/phy-mvebu-cp110-comphy.c lane->port = -1; lane 1055 drivers/phy/marvell/phy-mvebu-cp110-comphy.c phy_set_drvdata(phy, lane); lane 657 drivers/phy/phy-xgene.c static void serdes_wr(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 data) lane 663 drivers/phy/phy-xgene.c reg += lane * SERDES_LANE_STRIDE; lane 672 drivers/phy/phy-xgene.c static void serdes_rd(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 *data) lane 677 drivers/phy/phy-xgene.c reg += lane * SERDES_LANE_STRIDE; lane 683 drivers/phy/phy-xgene.c static void serdes_clrbits(struct xgene_phy_ctx *ctx, int lane, u32 reg, lane 688 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, reg, &val); lane 690 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, reg, val); lane 693 drivers/phy/phy-xgene.c static void serdes_setbits(struct xgene_phy_ctx *ctx, int lane, u32 reg, lane 698 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, reg, &val); lane 700 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, reg, val); lane 943 drivers/phy/phy-xgene.c int lane; lane 945 drivers/phy/phy-xgene.c for (lane = 0; lane < MAX_LANE; lane++) { lane 946 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG147, 0x6); lane 949 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG0, &val); lane 953 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG0, val); lane 956 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG1, &val); lane 959 drivers/phy/phy-xgene.c ctx->sata_param.txboostgain[lane * 3 + lane 960 drivers/phy/phy-xgene.c ctx->sata_param.speed[lane]]); lane 961 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG1, val); lane 965 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG2, &val); lane 969 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG2, val); lane 972 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG4, &val); lane 974 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG4, val); lane 977 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG1, &val); lane 980 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG1, val); lane 984 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG5, &val); lane 986 drivers/phy/phy-xgene.c ctx->sata_param.txprecursor_cn1[lane * 3 + lane 987 drivers/phy/phy-xgene.c ctx->sata_param.speed[lane]]); lane 989 drivers/phy/phy-xgene.c ctx->sata_param.txpostcursor_cp1[lane * 3 + lane 990 drivers/phy/phy-xgene.c ctx->sata_param.speed[lane]]); lane 992 drivers/phy/phy-xgene.c ctx->sata_param.txprecursor_cn2[lane * 3 + lane 993 drivers/phy/phy-xgene.c ctx->sata_param.speed[lane]]); lane 994 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG5, val); lane 997 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG6, &val); lane 999 drivers/phy/phy-xgene.c ctx->sata_param.txamplitude[lane * 3 + lane 1000 drivers/phy/phy-xgene.c ctx->sata_param.speed[lane]]); lane 1005 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG6, val); lane 1008 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG7, &val); lane 1011 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG7, val); lane 1014 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG8, &val); lane 1020 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG8, val); lane 1023 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG11, &val); lane 1025 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG11, val); lane 1028 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG12, &val); lane 1032 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG12, val); lane 1035 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG26, &val); lane 1038 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG26, val); lane 1040 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG28, 0x0); lane 1043 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG31, 0x0); lane 1046 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG61, &val); lane 1050 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG61, val); lane 1052 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG62, &val); lane 1054 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG62, val); lane 1059 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, reg, &val); lane 1063 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, reg, val); lane 1069 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, reg, &val); lane 1073 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, reg, val); lane 1079 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, reg, &val); lane 1083 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, reg, val); lane 1086 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG102, &val); lane 1088 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG102, val); lane 1090 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG114, 0xffe0); lane 1092 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG125, &val); lane 1094 drivers/phy/phy-xgene.c ctx->sata_param.txeyedirection[lane * 3 + lane 1095 drivers/phy/phy-xgene.c ctx->sata_param.speed[lane]]); lane 1097 drivers/phy/phy-xgene.c ctx->sata_param.txeyetuning[lane * 3 + lane 1098 drivers/phy/phy-xgene.c ctx->sata_param.speed[lane]]); lane 1100 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG125, val); lane 1102 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG127, &val); lane 1104 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG127, val); lane 1106 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG128, &val); lane 1108 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG128, val); lane 1110 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG145, &val); lane 1120 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG145, val); lane 1128 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, reg, 0xFFFF); lane 1342 drivers/phy/phy-xgene.c static void xgene_phy_force_lat_summer_cal(struct xgene_phy_ctx *ctx, int lane) lane 1370 drivers/phy/phy-xgene.c serdes_setbits(ctx, lane, RXTX_REG127, lane 1377 drivers/phy/phy-xgene.c serdes_clrbits(ctx, lane, RXTX_REG127, lane 1386 drivers/phy/phy-xgene.c serdes_setbits(ctx, lane, RXTX_REG127, lane 1393 drivers/phy/phy-xgene.c serdes_clrbits(ctx, lane, RXTX_REG127, lane 1397 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG28, 0x7); lane 1398 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG31, 0x7e00); lane 1399 drivers/phy/phy-xgene.c serdes_clrbits(ctx, lane, RXTX_REG4, lane 1401 drivers/phy/phy-xgene.c serdes_clrbits(ctx, lane, RXTX_REG7, lane 1404 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, serdes_reg[i].reg, lane 1408 drivers/phy/phy-xgene.c static void xgene_phy_reset_rxd(struct xgene_phy_ctx *ctx, int lane) lane 1411 drivers/phy/phy-xgene.c serdes_clrbits(ctx, lane, RXTX_REG7, RXTX_REG7_RESETB_RXD_MASK); lane 1414 drivers/phy/phy-xgene.c serdes_setbits(ctx, lane, RXTX_REG7, RXTX_REG7_RESETB_RXD_MASK); lane 1422 drivers/phy/phy-xgene.c static void xgene_phy_gen_avg_val(struct xgene_phy_ctx *ctx, int lane) lane 1437 drivers/phy/phy-xgene.c lane); lane 1440 drivers/phy/phy-xgene.c serdes_setbits(ctx, lane, RXTX_REG12, lane 1443 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG28, 0x0000); lane 1445 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG31, 0x0000); lane 1456 drivers/phy/phy-xgene.c xgene_phy_force_lat_summer_cal(ctx, lane); lane 1458 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG21, &val); lane 1463 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG22, &val); lane 1468 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG23, &val); lane 1472 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG24, &val); lane 1476 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG121, &val); lane 1506 drivers/phy/phy-xgene.c xgene_phy_reset_rxd(ctx, lane); lane 1510 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG127, &val); lane 1515 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG127, val); lane 1517 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG128, &val); lane 1522 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG128, val); lane 1524 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG129, &val); lane 1529 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG129, val); lane 1531 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG130, &val); lane 1536 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG130, val); lane 1539 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG14, &val); lane 1542 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG14, val); lane 1558 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG14, &val); lane 1560 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG14, val); lane 1563 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG127, &val); lane 1566 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG127, val); lane 1569 drivers/phy/phy-xgene.c serdes_rd(ctx, lane, RXTX_REG12, &val); lane 1571 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG12, val); lane 1573 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG28, 0x0007); lane 1575 drivers/phy/phy-xgene.c serdes_wr(ctx, lane, RXTX_REG31, 0x7e00); lane 505 drivers/phy/rockchip/phy-rockchip-typec.c static void tcphy_tx_usb3_cfg_lane(struct rockchip_typec_phy *tcphy, u32 lane) lane 507 drivers/phy/rockchip/phy-rockchip-typec.c writel(0x7799, tcphy->base + TX_PSC_A0(lane)); lane 508 drivers/phy/rockchip/phy-rockchip-typec.c writel(0x7798, tcphy->base + TX_PSC_A1(lane)); lane 509 drivers/phy/rockchip/phy-rockchip-typec.c writel(0x5098, tcphy->base + TX_PSC_A2(lane)); lane 510 drivers/phy/rockchip/phy-rockchip-typec.c writel(0x5098, tcphy->base + TX_PSC_A3(lane)); lane 511 drivers/phy/rockchip/phy-rockchip-typec.c writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_000(lane)); lane 512 drivers/phy/rockchip/phy-rockchip-typec.c writel(0xbf, tcphy->base + XCVR_DIAG_BIDI_CTRL(lane)); lane 515 drivers/phy/rockchip/phy-rockchip-typec.c static void tcphy_rx_usb3_cfg_lane(struct rockchip_typec_phy *tcphy, u32 lane) lane 517 drivers/phy/rockchip/phy-rockchip-typec.c writel(0xa6fd, tcphy->base + RX_PSC_A0(lane)); lane 518 drivers/phy/rockchip/phy-rockchip-typec.c writel(0xa6fd, tcphy->base + RX_PSC_A1(lane)); lane 519 drivers/phy/rockchip/phy-rockchip-typec.c writel(0xa410, tcphy->base + RX_PSC_A2(lane)); lane 520 drivers/phy/rockchip/phy-rockchip-typec.c writel(0x2410, tcphy->base + RX_PSC_A3(lane)); lane 521 drivers/phy/rockchip/phy-rockchip-typec.c writel(0x23ff, tcphy->base + RX_PSC_CAL(lane)); lane 522 drivers/phy/rockchip/phy-rockchip-typec.c writel(0x13, tcphy->base + RX_SIGDET_HL_FILT_TMR(lane)); lane 523 drivers/phy/rockchip/phy-rockchip-typec.c writel(0x03e7, tcphy->base + RX_REE_CTRL_DATA_MASK(lane)); lane 524 drivers/phy/rockchip/phy-rockchip-typec.c writel(0x1004, tcphy->base + RX_DIAG_SIGDET_TUNE(lane)); lane 525 drivers/phy/rockchip/phy-rockchip-typec.c writel(0x2010, tcphy->base + RX_PSC_RDY(lane)); lane 526 drivers/phy/rockchip/phy-rockchip-typec.c writel(0xfb, tcphy->base + XCVR_DIAG_BIDI_CTRL(lane)); lane 529 drivers/phy/rockchip/phy-rockchip-typec.c static void tcphy_dp_cfg_lane(struct rockchip_typec_phy *tcphy, u32 lane) lane 533 drivers/phy/rockchip/phy-rockchip-typec.c writel(0xbefc, tcphy->base + XCVR_PSM_RCTRL(lane)); lane 534 drivers/phy/rockchip/phy-rockchip-typec.c writel(0x6799, tcphy->base + TX_PSC_A0(lane)); lane 535 drivers/phy/rockchip/phy-rockchip-typec.c writel(0x6798, tcphy->base + TX_PSC_A1(lane)); lane 536 drivers/phy/rockchip/phy-rockchip-typec.c writel(0x98, tcphy->base + TX_PSC_A2(lane)); lane 537 drivers/phy/rockchip/phy-rockchip-typec.c writel(0x98, tcphy->base + TX_PSC_A3(lane)); lane 539 drivers/phy/rockchip/phy-rockchip-typec.c writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_000(lane)); lane 540 drivers/phy/rockchip/phy-rockchip-typec.c writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_001(lane)); lane 541 drivers/phy/rockchip/phy-rockchip-typec.c writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_010(lane)); lane 542 drivers/phy/rockchip/phy-rockchip-typec.c writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_011(lane)); lane 543 drivers/phy/rockchip/phy-rockchip-typec.c writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_100(lane)); lane 544 drivers/phy/rockchip/phy-rockchip-typec.c writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_101(lane)); lane 545 drivers/phy/rockchip/phy-rockchip-typec.c writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_110(lane)); lane 546 drivers/phy/rockchip/phy-rockchip-typec.c writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_111(lane)); lane 547 drivers/phy/rockchip/phy-rockchip-typec.c writel(0, tcphy->base + TX_TXCC_CPOST_MULT_10(lane)); lane 548 drivers/phy/rockchip/phy-rockchip-typec.c writel(0, tcphy->base + TX_TXCC_CPOST_MULT_01(lane)); lane 549 drivers/phy/rockchip/phy-rockchip-typec.c writel(0, tcphy->base + TX_TXCC_CPOST_MULT_00(lane)); lane 550 drivers/phy/rockchip/phy-rockchip-typec.c writel(0, tcphy->base + TX_TXCC_CPOST_MULT_11(lane)); lane 552 drivers/phy/rockchip/phy-rockchip-typec.c writel(0x128, tcphy->base + TX_TXCC_CAL_SCLR_MULT(lane)); lane 553 drivers/phy/rockchip/phy-rockchip-typec.c writel(0x400, tcphy->base + TX_DIAG_TX_DRV(lane)); lane 555 drivers/phy/rockchip/phy-rockchip-typec.c rdata = readl(tcphy->base + XCVR_DIAG_PLLDRC_CTRL(lane)); lane 557 drivers/phy/rockchip/phy-rockchip-typec.c writel(rdata, tcphy->base + XCVR_DIAG_PLLDRC_CTRL(lane)); lane 292 drivers/phy/tegra/xusb-tegra124.c struct tegra_xusb_lane *lane; lane 300 drivers/phy/tegra/xusb-tegra124.c lane = port->base.lane; lane 302 drivers/phy/tegra/xusb-tegra124.c if (lane->pad == padctl->pcie) lane 303 drivers/phy/tegra/xusb-tegra124.c offset = XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL6(lane->index); lane 452 drivers/phy/tegra/xusb-tegra124.c static void tegra124_usb2_lane_remove(struct tegra_xusb_lane *lane) lane 454 drivers/phy/tegra/xusb-tegra124.c struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane); lane 466 drivers/phy/tegra/xusb-tegra124.c struct tegra_xusb_lane *lane = phy_get_drvdata(phy); lane 468 drivers/phy/tegra/xusb-tegra124.c return tegra124_xusb_padctl_enable(lane->pad->padctl); lane 473 drivers/phy/tegra/xusb-tegra124.c struct tegra_xusb_lane *lane = phy_get_drvdata(phy); lane 475 drivers/phy/tegra/xusb-tegra124.c return tegra124_xusb_padctl_disable(lane->pad->padctl); lane 480 drivers/phy/tegra/xusb-tegra124.c struct tegra_xusb_lane *lane = phy_get_drvdata(phy); lane 481 drivers/phy/tegra/xusb-tegra124.c struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane); lane 482 drivers/phy/tegra/xusb-tegra124.c struct tegra_xusb_usb2_pad *pad = to_usb2_pad(lane->pad); lane 483 drivers/phy/tegra/xusb-tegra124.c struct tegra_xusb_padctl *padctl = lane->pad->padctl; lane 486 drivers/phy/tegra/xusb-tegra124.c unsigned int index = lane->index; lane 569 drivers/phy/tegra/xusb-tegra124.c struct tegra_xusb_lane *lane = phy_get_drvdata(phy); lane 570 drivers/phy/tegra/xusb-tegra124.c struct tegra_xusb_usb2_pad *pad = to_usb2_pad(lane->pad); lane 571 drivers/phy/tegra/xusb-tegra124.c struct tegra_xusb_padctl *padctl = lane->pad->padctl; lane 575 drivers/phy/tegra/xusb-tegra124.c port = tegra_xusb_find_usb2_port(padctl, lane->index); lane 578 drivers/phy/tegra/xusb-tegra124.c lane->index); lane 701 drivers/phy/tegra/xusb-tegra124.c static void tegra124_ulpi_lane_remove(struct tegra_xusb_lane *lane) lane 703 drivers/phy/tegra/xusb-tegra124.c struct tegra_xusb_ulpi_lane *ulpi = to_ulpi_lane(lane); lane 715 drivers/phy/tegra/xusb-tegra124.c struct tegra_xusb_lane *lane = phy_get_drvdata(phy); lane 717 drivers/phy/tegra/xusb-tegra124.c return tegra124_xusb_padctl_enable(lane->pad->padctl); lane 722 drivers/phy/tegra/xusb-tegra124.c struct tegra_xusb_lane *lane = phy_get_drvdata(phy); lane 724 drivers/phy/tegra/xusb-tegra124.c return tegra124_xusb_padctl_disable(lane->pad->padctl); lane 837 drivers/phy/tegra/xusb-tegra124.c static void tegra124_hsic_lane_remove(struct tegra_xusb_lane *lane) lane 839 drivers/phy/tegra/xusb-tegra124.c struct tegra_xusb_hsic_lane *hsic = to_hsic_lane(lane); lane 851 drivers/phy/tegra/xusb-tegra124.c struct tegra_xusb_lane *lane = phy_get_drvdata(phy); lane 853 drivers/phy/tegra/xusb-tegra124.c return tegra124_xusb_padctl_enable(lane->pad->padctl); lane 858 drivers/phy/tegra/xusb-tegra124.c struct tegra_xusb_lane *lane = phy_get_drvdata(phy); lane 860 drivers/phy/tegra/xusb-tegra124.c return tegra124_xusb_padctl_disable(lane->pad->padctl); lane 865 drivers/phy/tegra/xusb-tegra124.c struct tegra_xusb_lane *lane = phy_get_drvdata(phy); lane 866 drivers/phy/tegra/xusb-tegra124.c struct tegra_xusb_hsic_lane *hsic = to_hsic_lane(lane); lane 867 drivers/phy/tegra/xusb-tegra124.c struct tegra_xusb_hsic_pad *pad = to_hsic_pad(lane->pad); lane 868 drivers/phy/tegra/xusb-tegra124.c struct tegra_xusb_padctl *padctl = lane->pad->padctl; lane 869 drivers/phy/tegra/xusb-tegra124.c unsigned int index = lane->index; lane 935 drivers/phy/tegra/xusb-tegra124.c struct tegra_xusb_lane *lane = phy_get_drvdata(phy); lane 936 drivers/phy/tegra/xusb-tegra124.c struct tegra_xusb_hsic_pad *pad = to_hsic_pad(lane->pad); lane 937 drivers/phy/tegra/xusb-tegra124.c struct tegra_xusb_padctl *padctl = lane->pad->padctl; lane 938 drivers/phy/tegra/xusb-tegra124.c unsigned int index = lane->index; lane 1057 drivers/phy/tegra/xusb-tegra124.c static void tegra124_pcie_lane_remove(struct tegra_xusb_lane *lane) lane 1059 drivers/phy/tegra/xusb-tegra124.c struct tegra_xusb_pcie_lane *pcie = to_pcie_lane(lane); lane 1071 drivers/phy/tegra/xusb-tegra124.c struct tegra_xusb_lane *lane = phy_get_drvdata(phy); lane 1073 drivers/phy/tegra/xusb-tegra124.c return tegra124_xusb_padctl_enable(lane->pad->padctl); lane 1078 drivers/phy/tegra/xusb-tegra124.c struct tegra_xusb_lane *lane = phy_get_drvdata(phy); lane 1080 drivers/phy/tegra/xusb-tegra124.c return tegra124_xusb_padctl_disable(lane->pad->padctl); lane 1085 drivers/phy/tegra/xusb-tegra124.c struct tegra_xusb_lane *lane = phy_get_drvdata(phy); lane 1086 drivers/phy/tegra/xusb-tegra124.c struct tegra_xusb_padctl *padctl = lane->pad->padctl; lane 1118 drivers/phy/tegra/xusb-tegra124.c value |= XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->index); lane 1126 drivers/phy/tegra/xusb-tegra124.c struct tegra_xusb_lane *lane = phy_get_drvdata(phy); lane 1127 drivers/phy/tegra/xusb-tegra124.c struct tegra_xusb_padctl *padctl = lane->pad->padctl; lane 1131 drivers/phy/tegra/xusb-tegra124.c value &= ~XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->index); lane 1235 drivers/phy/tegra/xusb-tegra124.c static void tegra124_sata_lane_remove(struct tegra_xusb_lane *lane) lane 1237 drivers/phy/tegra/xusb-tegra124.c struct tegra_xusb_sata_lane *sata = to_sata_lane(lane); lane 1249 drivers/phy/tegra/xusb-tegra124.c struct tegra_xusb_lane *lane = phy_get_drvdata(phy); lane 1251 drivers/phy/tegra/xusb-tegra124.c return tegra124_xusb_padctl_enable(lane->pad->padctl); lane 1256 drivers/phy/tegra/xusb-tegra124.c struct tegra_xusb_lane *lane = phy_get_drvdata(phy); lane 1258 drivers/phy/tegra/xusb-tegra124.c return tegra124_xusb_padctl_disable(lane->pad->padctl); lane 1263 drivers/phy/tegra/xusb-tegra124.c struct tegra_xusb_lane *lane = phy_get_drvdata(phy); lane 1264 drivers/phy/tegra/xusb-tegra124.c struct tegra_xusb_padctl *padctl = lane->pad->padctl; lane 1300 drivers/phy/tegra/xusb-tegra124.c value |= XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->index); lane 1308 drivers/phy/tegra/xusb-tegra124.c struct tegra_xusb_lane *lane = phy_get_drvdata(phy); lane 1309 drivers/phy/tegra/xusb-tegra124.c struct tegra_xusb_padctl *padctl = lane->pad->padctl; lane 1313 drivers/phy/tegra/xusb-tegra124.c value &= ~XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->index); lane 1476 drivers/phy/tegra/xusb-tegra124.c struct tegra_xusb_lane *lane = usb3->base.lane; lane 1538 drivers/phy/tegra/xusb-tegra124.c if (lane->pad == padctl->pcie) lane 1539 drivers/phy/tegra/xusb-tegra124.c offset = XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL2(lane->index); lane 1550 drivers/phy/tegra/xusb-tegra124.c if (lane->pad == padctl->pcie) lane 1551 drivers/phy/tegra/xusb-tegra124.c offset = XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL5(lane->index); lane 1560 drivers/phy/tegra/xusb-tegra124.c if (lane->pad == padctl->sata) { lane 172 drivers/phy/tegra/xusb-tegra186.c static void tegra186_usb2_lane_remove(struct tegra_xusb_lane *lane) lane 174 drivers/phy/tegra/xusb-tegra186.c struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane); lane 252 drivers/phy/tegra/xusb-tegra186.c struct tegra_xusb_lane *lane = phy_get_drvdata(phy); lane 253 drivers/phy/tegra/xusb-tegra186.c struct tegra_xusb_padctl *padctl = lane->pad->padctl; lane 256 drivers/phy/tegra/xusb-tegra186.c unsigned int index = lane->index; lane 283 drivers/phy/tegra/xusb-tegra186.c struct tegra_xusb_lane *lane = phy_get_drvdata(phy); lane 284 drivers/phy/tegra/xusb-tegra186.c struct tegra_xusb_padctl *padctl = lane->pad->padctl; lane 285 drivers/phy/tegra/xusb-tegra186.c unsigned int index = lane->index; lane 306 drivers/phy/tegra/xusb-tegra186.c struct tegra_xusb_lane *lane = phy_get_drvdata(phy); lane 307 drivers/phy/tegra/xusb-tegra186.c struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane); lane 308 drivers/phy/tegra/xusb-tegra186.c struct tegra_xusb_padctl *padctl = lane->pad->padctl; lane 311 drivers/phy/tegra/xusb-tegra186.c unsigned int index = lane->index; lane 385 drivers/phy/tegra/xusb-tegra186.c struct tegra_xusb_lane *lane = phy_get_drvdata(phy); lane 386 drivers/phy/tegra/xusb-tegra186.c struct tegra_xusb_padctl *padctl = lane->pad->padctl; lane 388 drivers/phy/tegra/xusb-tegra186.c unsigned int index = lane->index; lane 412 drivers/phy/tegra/xusb-tegra186.c struct tegra_xusb_lane *lane = phy_get_drvdata(phy); lane 413 drivers/phy/tegra/xusb-tegra186.c struct tegra_xusb_padctl *padctl = lane->pad->padctl; lane 415 drivers/phy/tegra/xusb-tegra186.c unsigned int index = lane->index; lane 567 drivers/phy/tegra/xusb-tegra186.c static void tegra186_usb3_lane_remove(struct tegra_xusb_lane *lane) lane 569 drivers/phy/tegra/xusb-tegra186.c struct tegra_xusb_usb3_lane *usb3 = to_usb3_lane(lane); lane 601 drivers/phy/tegra/xusb-tegra186.c struct tegra_xusb_lane *lane = phy_get_drvdata(phy); lane 602 drivers/phy/tegra/xusb-tegra186.c struct tegra_xusb_padctl *padctl = lane->pad->padctl; lane 605 drivers/phy/tegra/xusb-tegra186.c unsigned int index = lane->index; lane 661 drivers/phy/tegra/xusb-tegra186.c struct tegra_xusb_lane *lane = phy_get_drvdata(phy); lane 662 drivers/phy/tegra/xusb-tegra186.c struct tegra_xusb_padctl *padctl = lane->pad->padctl; lane 664 drivers/phy/tegra/xusb-tegra186.c unsigned int index = lane->index; lane 806 drivers/phy/tegra/xusb-tegra210.c struct tegra_xusb_lane *lane; lane 813 drivers/phy/tegra/xusb-tegra210.c lane = port->lane; lane 815 drivers/phy/tegra/xusb-tegra210.c if (lane->pad == padctl->pcie) lane 816 drivers/phy/tegra/xusb-tegra210.c offset = XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL1(lane->index); lane 888 drivers/phy/tegra/xusb-tegra210.c static void tegra210_usb2_lane_remove(struct tegra_xusb_lane *lane) lane 890 drivers/phy/tegra/xusb-tegra210.c struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane); lane 902 drivers/phy/tegra/xusb-tegra210.c struct tegra_xusb_lane *lane = phy_get_drvdata(phy); lane 903 drivers/phy/tegra/xusb-tegra210.c struct tegra_xusb_padctl *padctl = lane->pad->padctl; lane 918 drivers/phy/tegra/xusb-tegra210.c struct tegra_xusb_lane *lane = phy_get_drvdata(phy); lane 920 drivers/phy/tegra/xusb-tegra210.c return tegra210_xusb_padctl_disable(lane->pad->padctl); lane 925 drivers/phy/tegra/xusb-tegra210.c struct tegra_xusb_lane *lane = phy_get_drvdata(phy); lane 926 drivers/phy/tegra/xusb-tegra210.c struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane); lane 927 drivers/phy/tegra/xusb-tegra210.c struct tegra_xusb_usb2_pad *pad = to_usb2_pad(lane->pad); lane 928 drivers/phy/tegra/xusb-tegra210.c struct tegra_xusb_padctl *padctl = lane->pad->padctl; lane 931 drivers/phy/tegra/xusb-tegra210.c unsigned int index = lane->index; lane 1050 drivers/phy/tegra/xusb-tegra210.c struct tegra_xusb_lane *lane = phy_get_drvdata(phy); lane 1051 drivers/phy/tegra/xusb-tegra210.c struct tegra_xusb_usb2_pad *pad = to_usb2_pad(lane->pad); lane 1052 drivers/phy/tegra/xusb-tegra210.c struct tegra_xusb_padctl *padctl = lane->pad->padctl; lane 1056 drivers/phy/tegra/xusb-tegra210.c port = tegra_xusb_find_usb2_port(padctl, lane->index); lane 1059 drivers/phy/tegra/xusb-tegra210.c lane->index); lane 1187 drivers/phy/tegra/xusb-tegra210.c static void tegra210_hsic_lane_remove(struct tegra_xusb_lane *lane) lane 1189 drivers/phy/tegra/xusb-tegra210.c struct tegra_xusb_hsic_lane *hsic = to_hsic_lane(lane); lane 1201 drivers/phy/tegra/xusb-tegra210.c struct tegra_xusb_lane *lane = phy_get_drvdata(phy); lane 1202 drivers/phy/tegra/xusb-tegra210.c struct tegra_xusb_padctl *padctl = lane->pad->padctl; lane 1217 drivers/phy/tegra/xusb-tegra210.c struct tegra_xusb_lane *lane = phy_get_drvdata(phy); lane 1219 drivers/phy/tegra/xusb-tegra210.c return tegra210_xusb_padctl_disable(lane->pad->padctl); lane 1224 drivers/phy/tegra/xusb-tegra210.c struct tegra_xusb_lane *lane = phy_get_drvdata(phy); lane 1225 drivers/phy/tegra/xusb-tegra210.c struct tegra_xusb_hsic_lane *hsic = to_hsic_lane(lane); lane 1226 drivers/phy/tegra/xusb-tegra210.c struct tegra_xusb_hsic_pad *pad = to_hsic_pad(lane->pad); lane 1227 drivers/phy/tegra/xusb-tegra210.c struct tegra_xusb_padctl *padctl = lane->pad->padctl; lane 1229 drivers/phy/tegra/xusb-tegra210.c unsigned int index = lane->index; lane 1312 drivers/phy/tegra/xusb-tegra210.c struct tegra_xusb_lane *lane = phy_get_drvdata(phy); lane 1313 drivers/phy/tegra/xusb-tegra210.c struct tegra_xusb_hsic_pad *pad = to_hsic_pad(lane->pad); lane 1314 drivers/phy/tegra/xusb-tegra210.c struct tegra_xusb_padctl *padctl = lane->pad->padctl; lane 1315 drivers/phy/tegra/xusb-tegra210.c unsigned int index = lane->index; lane 1449 drivers/phy/tegra/xusb-tegra210.c static void tegra210_pcie_lane_remove(struct tegra_xusb_lane *lane) lane 1451 drivers/phy/tegra/xusb-tegra210.c struct tegra_xusb_pcie_lane *pcie = to_pcie_lane(lane); lane 1463 drivers/phy/tegra/xusb-tegra210.c struct tegra_xusb_lane *lane = phy_get_drvdata(phy); lane 1465 drivers/phy/tegra/xusb-tegra210.c return tegra210_xusb_padctl_enable(lane->pad->padctl); lane 1470 drivers/phy/tegra/xusb-tegra210.c struct tegra_xusb_lane *lane = phy_get_drvdata(phy); lane 1472 drivers/phy/tegra/xusb-tegra210.c return tegra210_xusb_padctl_disable(lane->pad->padctl); lane 1477 drivers/phy/tegra/xusb-tegra210.c struct tegra_xusb_lane *lane = phy_get_drvdata(phy); lane 1478 drivers/phy/tegra/xusb-tegra210.c struct tegra_xusb_padctl *padctl = lane->pad->padctl; lane 1489 drivers/phy/tegra/xusb-tegra210.c value |= XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->index); lane 1499 drivers/phy/tegra/xusb-tegra210.c struct tegra_xusb_lane *lane = phy_get_drvdata(phy); lane 1500 drivers/phy/tegra/xusb-tegra210.c struct tegra_xusb_padctl *padctl = lane->pad->padctl; lane 1504 drivers/phy/tegra/xusb-tegra210.c value &= ~XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->index); lane 1620 drivers/phy/tegra/xusb-tegra210.c static void tegra210_sata_lane_remove(struct tegra_xusb_lane *lane) lane 1622 drivers/phy/tegra/xusb-tegra210.c struct tegra_xusb_sata_lane *sata = to_sata_lane(lane); lane 1634 drivers/phy/tegra/xusb-tegra210.c struct tegra_xusb_lane *lane = phy_get_drvdata(phy); lane 1636 drivers/phy/tegra/xusb-tegra210.c return tegra210_xusb_padctl_enable(lane->pad->padctl); lane 1641 drivers/phy/tegra/xusb-tegra210.c struct tegra_xusb_lane *lane = phy_get_drvdata(phy); lane 1643 drivers/phy/tegra/xusb-tegra210.c return tegra210_xusb_padctl_disable(lane->pad->padctl); lane 1648 drivers/phy/tegra/xusb-tegra210.c struct tegra_xusb_lane *lane = phy_get_drvdata(phy); lane 1649 drivers/phy/tegra/xusb-tegra210.c struct tegra_xusb_padctl *padctl = lane->pad->padctl; lane 1660 drivers/phy/tegra/xusb-tegra210.c value |= XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->index); lane 1670 drivers/phy/tegra/xusb-tegra210.c struct tegra_xusb_lane *lane = phy_get_drvdata(phy); lane 1671 drivers/phy/tegra/xusb-tegra210.c struct tegra_xusb_padctl *padctl = lane->pad->padctl; lane 1675 drivers/phy/tegra/xusb-tegra210.c value &= ~XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->index); lane 1678 drivers/phy/tegra/xusb-tegra210.c tegra210_sata_uphy_disable(lane->pad->padctl); lane 1807 drivers/phy/tegra/xusb-tegra210.c struct tegra_xusb_lane *lane = usb3->base.lane; lane 1859 drivers/phy/tegra/xusb-tegra210.c if (lane->pad == padctl->sata) lane 1893 drivers/phy/tegra/xusb-tegra210.c struct tegra_xusb_lane *lane = port->lane; lane 1913 drivers/phy/tegra/xusb-tegra210.c if (lane->pad == padctl->sata) lane 103 drivers/phy/tegra/xusb.c int tegra_xusb_lane_parse_dt(struct tegra_xusb_lane *lane, lane 106 drivers/phy/tegra/xusb.c struct device *dev = &lane->pad->dev; lane 114 drivers/phy/tegra/xusb.c err = match_string(lane->soc->funcs, lane->soc->num_funcs, function); lane 121 drivers/phy/tegra/xusb.c lane->function = err; lane 129 drivers/phy/tegra/xusb.c struct tegra_xusb_lane *lane = phy_get_drvdata(phy); lane 131 drivers/phy/tegra/xusb.c lane->pad->ops->remove(lane); lane 179 drivers/phy/tegra/xusb.c struct phy *lane; lane 187 drivers/phy/tegra/xusb.c pad->lanes = devm_kcalloc(&pad->dev, pad->soc->num_lanes, sizeof(lane), lane 196 drivers/phy/tegra/xusb.c struct tegra_xusb_lane *lane; lane 211 drivers/phy/tegra/xusb.c lane = pad->ops->probe(pad, np, i); lane 212 drivers/phy/tegra/xusb.c if (IS_ERR(lane)) { lane 214 drivers/phy/tegra/xusb.c err = PTR_ERR(lane); lane 218 drivers/phy/tegra/xusb.c list_add_tail(&lane->list, &pad->padctl->lanes); lane 219 drivers/phy/tegra/xusb.c phy_set_drvdata(pad->lanes[i], lane); lane 308 drivers/phy/tegra/xusb.c static void tegra_xusb_lane_program(struct tegra_xusb_lane *lane) lane 310 drivers/phy/tegra/xusb.c struct tegra_xusb_padctl *padctl = lane->pad->padctl; lane 311 drivers/phy/tegra/xusb.c const struct tegra_xusb_lane_soc *soc = lane->soc; lane 321 drivers/phy/tegra/xusb.c value |= lane->function << soc->shift; lane 330 drivers/phy/tegra/xusb.c struct tegra_xusb_lane *lane; lane 333 drivers/phy/tegra/xusb.c lane = phy_get_drvdata(pad->lanes[i]); lane 334 drivers/phy/tegra/xusb.c tegra_xusb_lane_program(lane); lane 373 drivers/phy/tegra/xusb.c static bool tegra_xusb_lane_check(struct tegra_xusb_lane *lane, lane 376 drivers/phy/tegra/xusb.c const char *func = lane->soc->funcs[lane->function]; lane 385 drivers/phy/tegra/xusb.c struct tegra_xusb_lane *lane, *hit = ERR_PTR(-ENODEV); lane 392 drivers/phy/tegra/xusb.c list_for_each_entry(lane, &padctl->lanes, list) { lane 393 drivers/phy/tegra/xusb.c if (strcmp(lane->soc->name, name) == 0) { lane 394 drivers/phy/tegra/xusb.c hit = lane; lane 408 drivers/phy/tegra/xusb.c struct tegra_xusb_lane *lane, *match = ERR_PTR(-ENODEV); lane 414 drivers/phy/tegra/xusb.c lane = tegra_xusb_find_lane(port->padctl, map->type, lane 416 drivers/phy/tegra/xusb.c if (IS_ERR(lane)) lane 419 drivers/phy/tegra/xusb.c if (!tegra_xusb_lane_check(lane, function)) lane 426 drivers/phy/tegra/xusb.c match = lane; lane 606 drivers/phy/tegra/xusb.c usb2->base.lane = usb2->base.ops->map(&usb2->base); lane 607 drivers/phy/tegra/xusb.c if (IS_ERR(usb2->base.lane)) { lane 608 drivers/phy/tegra/xusb.c err = PTR_ERR(usb2->base.lane); lane 658 drivers/phy/tegra/xusb.c ulpi->base.lane = ulpi->base.ops->map(&ulpi->base); lane 659 drivers/phy/tegra/xusb.c if (IS_ERR(ulpi->base.lane)) { lane 660 drivers/phy/tegra/xusb.c err = PTR_ERR(ulpi->base.lane); lane 706 drivers/phy/tegra/xusb.c hsic->base.lane = hsic->base.ops->map(&hsic->base); lane 707 drivers/phy/tegra/xusb.c if (IS_ERR(hsic->base.lane)) { lane 708 drivers/phy/tegra/xusb.c err = PTR_ERR(hsic->base.lane); lane 774 drivers/phy/tegra/xusb.c usb3->base.lane = usb3->base.ops->map(&usb3->base); lane 775 drivers/phy/tegra/xusb.c if (IS_ERR(usb3->base.lane)) { lane 776 drivers/phy/tegra/xusb.c err = PTR_ERR(usb3->base.lane); lane 48 drivers/phy/tegra/xusb.h int tegra_xusb_lane_parse_dt(struct tegra_xusb_lane *lane, lane 56 drivers/phy/tegra/xusb.h to_usb3_lane(struct tegra_xusb_lane *lane) lane 58 drivers/phy/tegra/xusb.h return container_of(lane, struct tegra_xusb_usb3_lane, base); lane 69 drivers/phy/tegra/xusb.h to_usb2_lane(struct tegra_xusb_lane *lane) lane 71 drivers/phy/tegra/xusb.h return container_of(lane, struct tegra_xusb_usb2_lane, base); lane 79 drivers/phy/tegra/xusb.h to_ulpi_lane(struct tegra_xusb_lane *lane) lane 81 drivers/phy/tegra/xusb.h return container_of(lane, struct tegra_xusb_ulpi_lane, base); lane 98 drivers/phy/tegra/xusb.h to_hsic_lane(struct tegra_xusb_lane *lane) lane 100 drivers/phy/tegra/xusb.h return container_of(lane, struct tegra_xusb_hsic_lane, base); lane 108 drivers/phy/tegra/xusb.h to_pcie_lane(struct tegra_xusb_lane *lane) lane 110 drivers/phy/tegra/xusb.h return container_of(lane, struct tegra_xusb_pcie_lane, base); lane 118 drivers/phy/tegra/xusb.h to_sata_lane(struct tegra_xusb_lane *lane) lane 120 drivers/phy/tegra/xusb.h return container_of(lane, struct tegra_xusb_sata_lane, base); lane 127 drivers/phy/tegra/xusb.h void (*remove)(struct tegra_xusb_lane *lane); lane 263 drivers/phy/tegra/xusb.h struct tegra_xusb_lane *lane; lane 299 drivers/pinctrl/tegra/pinctrl-tegra-xusb.c const struct tegra_xusb_padctl_lane *lane; lane 303 drivers/pinctrl/tegra/pinctrl-tegra-xusb.c lane = &padctl->soc->lanes[group]; lane 305 drivers/pinctrl/tegra/pinctrl-tegra-xusb.c for (i = 0; i < lane->num_funcs; i++) lane 306 drivers/pinctrl/tegra/pinctrl-tegra-xusb.c if (lane->funcs[i] == function) lane 309 drivers/pinctrl/tegra/pinctrl-tegra-xusb.c if (i >= lane->num_funcs) lane 312 drivers/pinctrl/tegra/pinctrl-tegra-xusb.c value = padctl_readl(padctl, lane->offset); lane 313 drivers/pinctrl/tegra/pinctrl-tegra-xusb.c value &= ~(lane->mask << lane->shift); lane 314 drivers/pinctrl/tegra/pinctrl-tegra-xusb.c value |= i << lane->shift; lane 315 drivers/pinctrl/tegra/pinctrl-tegra-xusb.c padctl_writel(padctl, value, lane->offset); lane 332 drivers/pinctrl/tegra/pinctrl-tegra-xusb.c const struct tegra_xusb_padctl_lane *lane; lane 337 drivers/pinctrl/tegra/pinctrl-tegra-xusb.c lane = &padctl->soc->lanes[group]; lane 342 drivers/pinctrl/tegra/pinctrl-tegra-xusb.c if (lane->iddq == 0) lane 345 drivers/pinctrl/tegra/pinctrl-tegra-xusb.c value = padctl_readl(padctl, lane->offset); lane 347 drivers/pinctrl/tegra/pinctrl-tegra-xusb.c if (value & BIT(lane->iddq)) lane 370 drivers/pinctrl/tegra/pinctrl-tegra-xusb.c const struct tegra_xusb_padctl_lane *lane; lane 376 drivers/pinctrl/tegra/pinctrl-tegra-xusb.c lane = &padctl->soc->lanes[group]; lane 385 drivers/pinctrl/tegra/pinctrl-tegra-xusb.c if (lane->iddq == 0) lane 388 drivers/pinctrl/tegra/pinctrl-tegra-xusb.c regval = padctl_readl(padctl, lane->offset); lane 391 drivers/pinctrl/tegra/pinctrl-tegra-xusb.c regval &= ~BIT(lane->iddq); lane 393 drivers/pinctrl/tegra/pinctrl-tegra-xusb.c regval |= BIT(lane->iddq); lane 395 drivers/pinctrl/tegra/pinctrl-tegra-xusb.c padctl_writel(padctl, regval, lane->offset); lane 255 drivers/scsi/ufs/ufshci.h #define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane) lane 256 drivers/scsi/ufs/ufshci.h #define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane)) lane 52 drivers/thunderbolt/lc.c u32 ctrl, lane; lane 68 drivers/thunderbolt/lc.c lane = TB_LC_SX_CTRL_L1C; lane 70 drivers/thunderbolt/lc.c lane = TB_LC_SX_CTRL_L2C; lane 73 drivers/thunderbolt/lc.c ctrl |= lane; lane 77 drivers/thunderbolt/lc.c ctrl &= ~lane; lane 3769 drivers/video/fbdev/omap2/omapfb/dss/dsi.c u8 lane, pol; lane 3791 drivers/video/fbdev/omap2/omapfb/dss/dsi.c lane = dx / 2; lane 3793 drivers/video/fbdev/omap2/omapfb/dss/dsi.c lanes[lane].function = functions[i / 2]; lane 3794 drivers/video/fbdev/omap2/omapfb/dss/dsi.c lanes[lane].polarity = pol; lane 46 drivers/video/fbdev/omap2/omapfb/dss/hdmi_phy.c u8 lane, pol; lane 68 drivers/video/fbdev/omap2/omapfb/dss/hdmi_phy.c lane = dx / 2; lane 70 drivers/video/fbdev/omap2/omapfb/dss/hdmi_phy.c phy->lane_function[lane] = i / 2; lane 71 drivers/video/fbdev/omap2/omapfb/dss/hdmi_phy.c phy->lane_polarity[lane] = pol; lane 1049 include/drm/drm_dp_helper.h int lane); lane 1051 include/drm/drm_dp_helper.h int lane); lane 262 include/linux/libnvdimm.h void nd_region_release_lane(struct nd_region *nd_region, unsigned int lane); lane 8134 include/linux/mlx5/mlx5_ifc.h u8 lane[0x4]; lane 8159 include/linux/mlx5/mlx5_ifc.h u8 lane[0x4]; lane 8720 include/linux/mlx5/mlx5_ifc.h u8 lane[0x4]; lane 23 include/linux/platform_data/media/mmp-camera.h int lane; /* ccic used lane number; 0 means DVP mode */ lane 2173 include/soc/tegra/bpmp-abi.h uint16_t lane; lane 333 sound/soc/sh/rcar/core.c int lane = rsnd_rdai_ssi_lane_get(rdai); lane 338 sound/soc/sh/rcar/core.c return (chan > 2) && (lane > 1); lane 226 sound/soc/zte/zx-i2s.c unsigned int lane, ch_num, len, ret = 0; lane 258 sound/soc/zte/zx-i2s.c lane = 1; lane 265 sound/soc/zte/zx-i2s.c lane = ch_num / 2; lane 272 sound/soc/zte/zx-i2s.c val |= ZX_I2S_TIMING_LANE(lane); lane 2650 tools/testing/nvdimm/test/nfit.c unsigned int lane; lane 2652 tools/testing/nvdimm/test/nfit.c lane = nd_region_acquire_lane(nd_region); lane 2661 tools/testing/nvdimm/test/nfit.c nd_region_release_lane(nd_region, lane);