l2x0_base          78 arch/arm/mach-imx/mm-imx3.c 	void __iomem *l2x0_base;
l2x0_base          99 arch/arm/mach-imx/mm-imx3.c 	l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
l2x0_base         100 arch/arm/mach-imx/mm-imx3.c 	if (!l2x0_base) {
l2x0_base         105 arch/arm/mach-imx/mm-imx3.c 	l2x0_init(l2x0_base, 0x00030024, 0x00000000);
l2x0_base          88 arch/arm/mach-imx/system.c 	void __iomem *l2x0_base;
l2x0_base          96 arch/arm/mach-imx/system.c 	l2x0_base = of_iomap(np, 0);
l2x0_base          97 arch/arm/mach-imx/system.c 	if (!l2x0_base)
l2x0_base         100 arch/arm/mach-imx/system.c 	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
l2x0_base         102 arch/arm/mach-imx/system.c 		val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL);
l2x0_base         111 arch/arm/mach-imx/system.c 		writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL);
l2x0_base         114 arch/arm/mach-imx/system.c 	iounmap(l2x0_base);
l2x0_base         198 arch/arm/mach-omap2/omap-mpuss-lowpower.c 	void __iomem *l2x0_base = omap4_get_l2cache_base();
l2x0_base         200 arch/arm/mach-omap2/omap-mpuss-lowpower.c 	if (l2x0_base && sar_base) {
l2x0_base          36 arch/arm/mach-ux500/cpu-db8500.c 	void __iomem *l2x0_base;
l2x0_base          39 arch/arm/mach-ux500/cpu-db8500.c 	l2x0_base = of_iomap(np, 0);
l2x0_base          41 arch/arm/mach-ux500/cpu-db8500.c 	if (!l2x0_base)
l2x0_base          52 arch/arm/mach-ux500/cpu-db8500.c 		writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
l2x0_base          54 arch/arm/mach-ux500/cpu-db8500.c 		writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE +
l2x0_base          57 arch/arm/mach-ux500/cpu-db8500.c 	iounmap(l2x0_base);
l2x0_base          20 arch/arm/mm/cache-l2x0-pmu.c static void __iomem *l2x0_base;
l2x0_base          66 arch/arm/mm/cache-l2x0-pmu.c 	writel_relaxed(val, l2x0_base + L2X0_EVENT_CNT0_CFG - 4 * idx);
l2x0_base          71 arch/arm/mm/cache-l2x0-pmu.c 	return readl_relaxed(l2x0_base + L2X0_EVENT_CNT0_VAL - 4 * idx);
l2x0_base          76 arch/arm/mm/cache-l2x0-pmu.c 	writel_relaxed(val, l2x0_base + L2X0_EVENT_CNT0_VAL - 4 * idx);
l2x0_base          81 arch/arm/mm/cache-l2x0-pmu.c 	u32 val = readl_relaxed(l2x0_base + L2X0_EVENT_CNT_CTRL);
l2x0_base          83 arch/arm/mm/cache-l2x0-pmu.c 	writel_relaxed(val, l2x0_base + L2X0_EVENT_CNT_CTRL);
l2x0_base          88 arch/arm/mm/cache-l2x0-pmu.c 	u32 val = readl_relaxed(l2x0_base + L2X0_EVENT_CNT_CTRL);
l2x0_base          90 arch/arm/mm/cache-l2x0-pmu.c 	writel_relaxed(val, l2x0_base + L2X0_EVENT_CNT_CTRL);
l2x0_base         500 arch/arm/mm/cache-l2x0-pmu.c 	l2x0_base = base;
l2x0_base         507 arch/arm/mm/cache-l2x0-pmu.c 	if (!l2x0_base)
l2x0_base          39 arch/arm/mm/cache-l2x0.c static void __iomem *l2x0_base;
l2x0_base         134 arch/arm/mm/cache-l2x0.c 	void __iomem *base = l2x0_base;
l2x0_base         145 arch/arm/mm/cache-l2x0.c 	l2x0_saved_regs.aux_ctrl = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
l2x0_base         150 arch/arm/mm/cache-l2x0.c 	void __iomem *base = l2x0_base;
l2x0_base         189 arch/arm/mm/cache-l2x0.c 	void __iomem *base = l2x0_base;
l2x0_base         208 arch/arm/mm/cache-l2x0.c 	void __iomem *base = l2x0_base;
l2x0_base         217 arch/arm/mm/cache-l2x0.c 	void __iomem *base = l2x0_base;
l2x0_base         226 arch/arm/mm/cache-l2x0.c 	void __iomem *base = l2x0_base;
l2x0_base         236 arch/arm/mm/cache-l2x0.c 	__l2c210_cache_sync(l2x0_base);
l2x0_base         309 arch/arm/mm/cache-l2x0.c 	void __iomem *base = l2x0_base;
l2x0_base         336 arch/arm/mm/cache-l2x0.c 	void __iomem *base = l2x0_base;
l2x0_base         355 arch/arm/mm/cache-l2x0.c 	void __iomem *base = l2x0_base;
l2x0_base         374 arch/arm/mm/cache-l2x0.c 	l2c220_op_way(l2x0_base, L2X0_CLEAN_INV_WAY);
l2x0_base         382 arch/arm/mm/cache-l2x0.c 	__l2c220_cache_sync(l2x0_base);
l2x0_base         469 arch/arm/mm/cache-l2x0.c 	void __iomem *base = l2x0_base;
l2x0_base         503 arch/arm/mm/cache-l2x0.c 	void __iomem *base = l2x0_base;
l2x0_base         528 arch/arm/mm/cache-l2x0.c 	void __iomem *base = l2x0_base;
l2x0_base         803 arch/arm/mm/cache-l2x0.c 	old_aux = aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
l2x0_base         856 arch/arm/mm/cache-l2x0.c 		data->fixup(l2x0_base, cache_id, &fns);
l2x0_base         866 arch/arm/mm/cache-l2x0.c 	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
l2x0_base         869 arch/arm/mm/cache-l2x0.c 		data->enable(l2x0_base, data->num_lock);
l2x0_base         879 arch/arm/mm/cache-l2x0.c 		data->save(l2x0_base);
l2x0_base         882 arch/arm/mm/cache-l2x0.c 	aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
l2x0_base         889 arch/arm/mm/cache-l2x0.c 	l2x0_pmu_register(l2x0_base, cache_id);
l2x0_base         899 arch/arm/mm/cache-l2x0.c 	l2x0_base = base;
l2x0_base         920 arch/arm/mm/cache-l2x0.c 		data->save(l2x0_base);
l2x0_base        1370 arch/arm/mm/cache-l2x0.c 	void __iomem *base = l2x0_base;
l2x0_base        1420 arch/arm/mm/cache-l2x0.c 	void __iomem *base = l2x0_base;
l2x0_base        1433 arch/arm/mm/cache-l2x0.c 	writel_relaxed(0, l2x0_base + AURORA_SYNC_REG);
l2x0_base        1438 arch/arm/mm/cache-l2x0.c 	void __iomem *base = l2x0_base;
l2x0_base        1769 arch/arm/mm/cache-l2x0.c 	l2x0_base = ioremap(res.start, resource_size(&res));
l2x0_base        1770 arch/arm/mm/cache-l2x0.c 	if (!l2x0_base)
l2x0_base        1781 arch/arm/mm/cache-l2x0.c 	old_aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
l2x0_base        1803 arch/arm/mm/cache-l2x0.c 		data->save(l2x0_base);
l2x0_base        1806 arch/arm/mm/cache-l2x0.c 	if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN))
l2x0_base        1813 arch/arm/mm/cache-l2x0.c 		cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);