l2ctype            19 arch/arm/mm/cache-xsc3l2.c #define CACHE_WAY_SIZE(l2ctype)	(8192 << (((l2ctype) >> 8) & 0xf))
l2ctype            20 arch/arm/mm/cache-xsc3l2.c #define CACHE_SET_SIZE(l2ctype)	(CACHE_WAY_SIZE(l2ctype) >> CACHE_LINE_SHIFT)
l2ctype            24 arch/arm/mm/cache-xsc3l2.c 	unsigned long l2ctype;
l2ctype            26 arch/arm/mm/cache-xsc3l2.c 	__asm__("mrc p15, 1, %0, c0, c0, 1" : "=r" (l2ctype));
l2ctype            28 arch/arm/mm/cache-xsc3l2.c 	return !!(l2ctype & 0xf8);
l2ctype            43 arch/arm/mm/cache-xsc3l2.c 	unsigned long l2ctype, set_way;
l2ctype            46 arch/arm/mm/cache-xsc3l2.c 	__asm__("mrc p15, 1, %0, c0, c0, 1" : "=r" (l2ctype));
l2ctype            48 arch/arm/mm/cache-xsc3l2.c 	for (set = 0; set < CACHE_SET_SIZE(l2ctype); set++) {
l2ctype           153 arch/arm/mm/cache-xsc3l2.c 	unsigned long l2ctype, set_way;
l2ctype           156 arch/arm/mm/cache-xsc3l2.c 	__asm__("mrc p15, 1, %0, c0, c0, 1" : "=r" (l2ctype));
l2ctype           158 arch/arm/mm/cache-xsc3l2.c 	for (set = 0; set < CACHE_SET_SIZE(l2ctype); set++) {