l2_base           226 arch/arm/mach-imx/pm-imx6.c 	struct imx6_pm_base l2_base;
l2_base           372 arch/arm/mach-imx/pm-imx6.c 			suspend_ocram_base)->l2_base.vbase)
l2_base           548 arch/arm/mach-imx/pm-imx6.c 		ret = imx6_pm_get_base(&pm_info->l2_base, socdata->pl310_compat);
l2_base            48 arch/powerpc/platforms/85xx/xes_mpc85xx.c static void xes_mpc85xx_configure_l2(void __iomem *l2_base)
l2_base            53 arch/powerpc/platforms/85xx/xes_mpc85xx.c 	tmp = in_be32(l2_base);
l2_base            71 arch/powerpc/platforms/85xx/xes_mpc85xx.c 	out_be32(l2_base, ctl);
l2_base            86 arch/powerpc/platforms/85xx/xes_mpc85xx.c 		void __iomem *l2_base;
l2_base           105 arch/powerpc/platforms/85xx/xes_mpc85xx.c 		l2_base = ioremap(r[0].start, resource_size(&r[0]));
l2_base           107 arch/powerpc/platforms/85xx/xes_mpc85xx.c 		xes_mpc85xx_configure_l2(l2_base);
l2_base            32 arch/riscv/mm/sifive_l2_cache.c static void __iomem *l2_base;
l2_base            52 arch/riscv/mm/sifive_l2_cache.c 		writel(val, l2_base + SIFIVE_L2_ECCINJECTERR);
l2_base            77 arch/riscv/mm/sifive_l2_cache.c 	regval = readl(l2_base + SIFIVE_L2_CONFIG);
l2_base            87 arch/riscv/mm/sifive_l2_cache.c 	regval = readl(l2_base + SIFIVE_L2_WAYENABLE);
l2_base           115 arch/riscv/mm/sifive_l2_cache.c 		add_h = readl(l2_base + SIFIVE_L2_DIRECCFIX_HIGH);
l2_base           116 arch/riscv/mm/sifive_l2_cache.c 		add_l = readl(l2_base + SIFIVE_L2_DIRECCFIX_LOW);
l2_base           119 arch/riscv/mm/sifive_l2_cache.c 		readl(l2_base + SIFIVE_L2_DIRECCFIX_COUNT);
l2_base           124 arch/riscv/mm/sifive_l2_cache.c 		add_h = readl(l2_base + SIFIVE_L2_DATECCFIX_HIGH);
l2_base           125 arch/riscv/mm/sifive_l2_cache.c 		add_l = readl(l2_base + SIFIVE_L2_DATECCFIX_LOW);
l2_base           128 arch/riscv/mm/sifive_l2_cache.c 		readl(l2_base + SIFIVE_L2_DATECCFIX_COUNT);
l2_base           133 arch/riscv/mm/sifive_l2_cache.c 		add_h = readl(l2_base + SIFIVE_L2_DATECCFAIL_HIGH);
l2_base           134 arch/riscv/mm/sifive_l2_cache.c 		add_l = readl(l2_base + SIFIVE_L2_DATECCFAIL_LOW);
l2_base           137 arch/riscv/mm/sifive_l2_cache.c 		readl(l2_base + SIFIVE_L2_DATECCFAIL_COUNT);
l2_base           158 arch/riscv/mm/sifive_l2_cache.c 	l2_base = ioremap(res.start, resource_size(&res));
l2_base           159 arch/riscv/mm/sifive_l2_cache.c 	if (!l2_base)