l0                 13 arch/sparc/include/asm/head_32.h 	rd %psr, %l0; b label; rd %wim, %l3; nop;
l0                 16 arch/sparc/include/asm/head_32.h #define SRMMU_TFAULT rd %psr, %l0; rd %wim, %l3; b srmmu_fault; mov 1, %l7;
l0                 17 arch/sparc/include/asm/head_32.h #define SRMMU_DFAULT rd %psr, %l0; rd %wim, %l3; b srmmu_fault; mov 0, %l7;
l0                 21 arch/sparc/include/asm/head_32.h         rd %psr, %l0; mov num, %l7; b bad_trap_handler; rd %wim, %l3;
l0                 38 arch/sparc/include/asm/head_32.h         rd %psr, %l0;
l0                 42 arch/sparc/include/asm/head_32.h 	rd %psr,%l0; \
l0                 50 arch/sparc/include/asm/head_32.h 	rd %psr,%l0;                    \
l0                 59 arch/sparc/include/asm/head_32.h         b getcc_trap_handler; rd %psr, %l0; nop; nop;
l0                 63 arch/sparc/include/asm/head_32.h         b setcc_trap_handler; rd %psr, %l0; nop; nop;
l0                 73 arch/sparc/include/asm/head_32.h         mov int_level, %l7; rd %psr, %l0; b real_irq_entry; rd %wim, %l3;
l0                 79 arch/sparc/include/asm/head_32.h         rd %psr, %l0; rd %wim, %l3; b spill_window_entry; andcc %l0, PSR_PS, %g0;
l0                 82 arch/sparc/include/asm/head_32.h         rd %psr, %l0; rd %wim, %l3; b fill_window_entry; andcc %l0, PSR_PS, %g0;
l0                 16 arch/sparc/include/asm/ttable.h 	rdpr	%cleanwin, %l0;		add	%l0, 1, %l0;		\
l0                 17 arch/sparc/include/asm/ttable.h 	wrpr	%l0, 0x0, %cleanwin;					\
l0                 20 arch/sparc/include/asm/ttable.h 	clr	%l0;	clr	%l1;	clr	%l2;	clr	%l3;	\
l0                252 arch/sparc/include/asm/ttable.h 	stx	%l0, [%sp + STACK_BIAS + 0x00];		\
l0                273 arch/sparc/include/asm/ttable.h 	stx	%l0, [%sp + STACK_BIAS + 0x00];		\
l0                299 arch/sparc/include/asm/ttable.h 	stxa	%l0, [%g1 + %g0] ASI;			\
l0                331 arch/sparc/include/asm/ttable.h 	stxa	%l0, [%sp + STACK_BIAS + 0x00] %asi;	\
l0                365 arch/sparc/include/asm/ttable.h 	stx	%l0, [%g3 + TI_REG_WINDOW + 0x00];	\
l0                395 arch/sparc/include/asm/ttable.h 	stwa	%l0, [%sp + %g0] ASI;			\
l0                430 arch/sparc/include/asm/ttable.h 	stwa	%l0, [%sp + 0x00] %asi;	\
l0                464 arch/sparc/include/asm/ttable.h 	stw	%l0, [%g3 + TI_REG_WINDOW + 0x00];	\
l0                508 arch/sparc/include/asm/ttable.h 	ldx	[%sp + STACK_BIAS + 0x00], %l0;		\
l0                532 arch/sparc/include/asm/ttable.h 	ldx	[%sp + STACK_BIAS + 0x00], %l0;		\
l0                559 arch/sparc/include/asm/ttable.h 	ldxa	[%g1 + %g0] ASI, %l0;			\
l0                589 arch/sparc/include/asm/ttable.h 	ldxa	[%sp + STACK_BIAS + 0x00] %asi, %l0;	\
l0                619 arch/sparc/include/asm/ttable.h 	lduwa	[%sp + %g0] ASI, %l0;			\
l0                652 arch/sparc/include/asm/ttable.h 	lduwa	[%sp + 0x00] %asi, %l0;			\
l0                 17 arch/sparc/include/asm/winmacro.h 	std	%l0, [%reg + RW_L0]; \
l0                 28 arch/sparc/include/asm/winmacro.h 	ldd	[%reg + RW_L0], %l0; \
l0                318 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c 	unsigned int pixelsPerClock, lstall, D, initalXmitDelay, w, s, ix, wx, p, l0, a, ax, l,
l0                351 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c 	l0 = ix / w;
l0                352 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c 	a = ix + p * l0;
l0                341 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c 	unsigned int pixelsPerClock, lstall, D, initalXmitDelay, w, s, ix, wx, p, l0, a, ax, l,
l0                374 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c 	l0 = ix / w;
l0                375 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c 	a = ix + p * l0;
l0                513 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 	unsigned int pixelsPerClock, lstall, D, initalXmitDelay, w, S, ix, wx, p, l0, a, ax, l,
l0                546 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 	l0 = ix / w;
l0                547 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 	a = ix + p * l0;
l0                 64 fs/xfs/libxfs/xfs_bmap_btree.c 	uint64_t		l0 = get_unaligned_be64(&rec->l0);
l0                 67 fs/xfs/libxfs/xfs_bmap_btree.c 	irec->br_startoff = (l0 & xfs_mask64lo(64 - BMBT_EXNTFLAG_BITLEN)) >> 9;
l0                 68 fs/xfs/libxfs/xfs_bmap_btree.c 	irec->br_startblock = ((l0 & xfs_mask64lo(9)) << 43) | (l1 >> 21);
l0                 70 fs/xfs/libxfs/xfs_bmap_btree.c 	if (l0 >> (64 - BMBT_EXNTFLAG_BITLEN))
l0                 93 fs/xfs/libxfs/xfs_bmap_btree.c 	return ((xfs_fileoff_t)be64_to_cpu(r->l0) &
l0                115 fs/xfs/libxfs/xfs_bmap_btree.c 		 ((xfs_bmbt_rec_base_t)s->br_startblock >> 43), &r->l0);
l0               1545 fs/xfs/libxfs/xfs_format.h 	__be64			l0, l1;
l0               1263 kernel/rcu/srcutree.c 		unsigned long l0, l1;
l0               1278 kernel/rcu/srcutree.c 		l0 = sdp->srcu_lock_count[!idx];
l0               1281 kernel/rcu/srcutree.c 		c0 = l0 - u0;
l0                573 lib/bch.c      	int n = 0, i, l0, l1, l2;
l0                578 lib/bch.c      		l0 = bch->a_log_tab[poly->c[0]];
l0                583 lib/bch.c      		u = a_pow(bch, l0+l2+2*(GF_N(bch)-l1));
l0                172 scripts/dtc/dtc.h #define for_each_label_withdel(l0, l) \
l0                173 scripts/dtc/dtc.h 	for ((l) = (l0); (l); (l) = (l)->next)
l0                175 scripts/dtc/dtc.h #define for_each_label(l0, l) \
l0                176 scripts/dtc/dtc.h 	for_each_label_withdel(l0, l) \