L1I 1283 arch/alpha/kernel/setup.c int L1I, L1D, L2, L3; L1I 1290 arch/alpha/kernel/setup.c L1I = CSHAPE(8*1024, 5, 1); L1I 1292 arch/alpha/kernel/setup.c L1I = CSHAPE(16*1024, 5, 1); L1I 1293 arch/alpha/kernel/setup.c L1D = L1I; L1I 1314 arch/alpha/kernel/setup.c L1I = L1D = CSHAPE(8*1024, 5, 1); L1I 1329 arch/alpha/kernel/setup.c L1I = L1D = CSHAPE(8*1024, 5, 1); L1I 1354 arch/alpha/kernel/setup.c L1I = CSHAPE(16*1024, 6, 1); L1I 1357 arch/alpha/kernel/setup.c L1I = CSHAPE(32*1024, 6, 2); L1I 1381 arch/alpha/kernel/setup.c L1I = L1D = CSHAPE(64*1024, 6, 2); L1I 1388 arch/alpha/kernel/setup.c L1I = L1D = CSHAPE(64*1024, 6, 2); L1I 1395 arch/alpha/kernel/setup.c L1I = L1D = L2 = L3 = 0; L1I 1399 arch/alpha/kernel/setup.c alpha_l1i_cacheshape = L1I; L1I 141 arch/arc/include/asm/perf_event.h [C(L1I)] = { L1I 101 arch/arm/kernel/perf_event_v6.c [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV6_PERFCTR_ICACHE_MISS, L1I 164 arch/arm/kernel/perf_event_v6.c [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ICACHE_MISS, L1I 184 arch/arm/kernel/perf_event_v7.c [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS, L1I 185 arch/arm/kernel/perf_event_v7.c [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, L1I 234 arch/arm/kernel/perf_event_v7.c [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, L1I 273 arch/arm/kernel/perf_event_v7.c [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, L1I 274 arch/arm/kernel/perf_event_v7.c [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, L1I 279 arch/arm/kernel/perf_event_v7.c [C(L1I)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL, L1I 280 arch/arm/kernel/perf_event_v7.c [C(L1I)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP, L1I 323 arch/arm/kernel/perf_event_v7.c [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, L1I 324 arch/arm/kernel/perf_event_v7.c [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, L1I 372 arch/arm/kernel/perf_event_v7.c [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, L1I 373 arch/arm/kernel/perf_event_v7.c [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, L1I 421 arch/arm/kernel/perf_event_v7.c [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, L1I 422 arch/arm/kernel/perf_event_v7.c [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, L1I 477 arch/arm/kernel/perf_event_v7.c [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_ICACHE_ACCESS, L1I 478 arch/arm/kernel/perf_event_v7.c [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = KRAIT_PERFCTR_L1_ICACHE_MISS, L1I 517 arch/arm/kernel/perf_event_v7.c [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = SCORPION_ICACHE_ACCESS, L1I 518 arch/arm/kernel/perf_event_v7.c [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = SCORPION_ICACHE_MISS, L1I 78 arch/arm/kernel/perf_event_xscale.c [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = XSCALE_PERFCTR_ICACHE_MISS, L1I 60 arch/arm64/kernel/perf_event.c [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE, L1I 61 arch/arm64/kernel/perf_event.c [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL, L1I 122 arch/arm64/kernel/perf_event.c [C(L1I)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS, L1I 123 arch/arm64/kernel/perf_event.c [C(L1I)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS, L1I 759 arch/csky/kernel/perf_event.c [C(L1I)] = { L1I 891 arch/mips/kernel/perf_event_mipsxx.c [C(L1I)] = { L1I 972 arch/mips/kernel/perf_event_mipsxx.c [C(L1I)] = { L1I 1041 arch/mips/kernel/perf_event_mipsxx.c [C(L1I)] = { L1I 1085 arch/mips/kernel/perf_event_mipsxx.c [C(L1I)] = { L1I 1143 arch/mips/kernel/perf_event_mipsxx.c [C(L1I)] = { L1I 1195 arch/mips/kernel/perf_event_mipsxx.c [C(L1I)] = { L1I 1236 arch/mips/kernel/perf_event_mipsxx.c [C(L1I)] = { L1I 264 arch/nds32/include/asm/pmu.h [C(L1I)] = { L1I 44 arch/powerpc/perf/e500-pmu.c [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */ L1I 42 arch/powerpc/perf/e6500-pmu.c [C(L1I)] = { L1I 119 arch/powerpc/perf/generic-compat-pmu.c [ C(L1I) ] = { L1I 363 arch/powerpc/perf/mpc7450-pmu.c [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */ L1I 627 arch/powerpc/perf/power5+-pmu.c [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */ L1I 569 arch/powerpc/perf/power5-pmu.c [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */ L1I 490 arch/powerpc/perf/power6-pmu.c [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */ L1I 341 arch/powerpc/perf/power7-pmu.c [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */ L1I 271 arch/powerpc/perf/power8-pmu.c [ C(L1I) ] = { L1I 328 arch/powerpc/perf/power9-pmu.c [ C(L1I) ] = { L1I 441 arch/powerpc/perf/ppc970-pmu.c [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */ L1I 70 arch/riscv/kernel/perf_event.c [C(L1I)] = { L1I 106 arch/sh/kernel/cpu/sh4/perf_event.c [ C(L1I) ] = { L1I 131 arch/sh/kernel/cpu/sh4a/perf_event.c [ C(L1I) ] = { L1I 235 arch/sparc/kernel/perf_event.c [C(L1I)] = { L1I 373 arch/sparc/kernel/perf_event.c [C(L1I)] = { L1I 508 arch/sparc/kernel/perf_event.c [C(L1I)] = { L1I 645 arch/sparc/kernel/perf_event.c [C(L1I)] = { L1I 36 arch/x86/events/amd/core.c [ C(L1I ) ] = { L1I 140 arch/x86/events/amd/core.c [C(L1I)] = { L1I 439 arch/x86/events/intel/core.c [ C(L1I ) ] = { L1I 667 arch/x86/events/intel/core.c [ C(L1I ) ] = { L1I 823 arch/x86/events/intel/core.c [ C(L1I ) ] = { L1I 975 arch/x86/events/intel/core.c [ C(L1I ) ] = { L1I 1158 arch/x86/events/intel/core.c [ C(L1I ) ] = { L1I 1273 arch/x86/events/intel/core.c [ C(L1I ) ] = { L1I 1364 arch/x86/events/intel/core.c [ C(L1I ) ] = { L1I 1515 arch/x86/events/intel/core.c [ C(L1I ) ] = { L1I 1649 arch/x86/events/intel/core.c [C(L1I)] = { L1I 1765 arch/x86/events/intel/core.c [C(L1I)] = { L1I 45 arch/x86/events/intel/knc.c [ C(L1I ) ] = { L1I 42 arch/x86/events/intel/p6.c [ C(L1I ) ] = { L1I 84 arch/xtensa/kernel/perf_event.c [C(L1I)] = { L1I 526 tools/perf/util/evsel.c [C(L1I)] = (CACHE_READ | CACHE_PREFETCH),