jz4740_timer_base   49 arch/mips/include/asm/mach-jz4740/timer.h extern void __iomem *jz4740_timer_base;
jz4740_timer_base   57 arch/mips/include/asm/mach-jz4740/timer.h 	writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
jz4740_timer_base   62 arch/mips/include/asm/mach-jz4740/timer.h 	writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
jz4740_timer_base   67 arch/mips/include/asm/mach-jz4740/timer.h 	return readb(jz4740_timer_base + JZ_REG_TIMER_ENABLE) & BIT(timer);
jz4740_timer_base   72 arch/mips/include/asm/mach-jz4740/timer.h 	writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_SET);
jz4740_timer_base   77 arch/mips/include/asm/mach-jz4740/timer.h 	writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_CLEAR);
jz4740_timer_base   82 arch/mips/include/asm/mach-jz4740/timer.h 	writew(period, jz4740_timer_base + JZ_REG_TIMER_DFR(timer));
jz4740_timer_base   87 arch/mips/include/asm/mach-jz4740/timer.h 	writew(duty, jz4740_timer_base + JZ_REG_TIMER_DHR(timer));
jz4740_timer_base   92 arch/mips/include/asm/mach-jz4740/timer.h 	writew(count, jz4740_timer_base + JZ_REG_TIMER_CNT(timer));
jz4740_timer_base   97 arch/mips/include/asm/mach-jz4740/timer.h 	return readw(jz4740_timer_base + JZ_REG_TIMER_CNT(timer));
jz4740_timer_base  102 arch/mips/include/asm/mach-jz4740/timer.h 	writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
jz4740_timer_base  107 arch/mips/include/asm/mach-jz4740/timer.h 	writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
jz4740_timer_base  108 arch/mips/include/asm/mach-jz4740/timer.h 	writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_CLEAR);
jz4740_timer_base  113 arch/mips/include/asm/mach-jz4740/timer.h 	writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_SET);
jz4740_timer_base  118 arch/mips/include/asm/mach-jz4740/timer.h 	writew(ctrl, jz4740_timer_base + JZ_REG_TIMER_CTRL(timer));
jz4740_timer_base  123 arch/mips/include/asm/mach-jz4740/timer.h 	return readw(jz4740_timer_base + JZ_REG_TIMER_CTRL(timer));
jz4740_timer_base   15 arch/mips/jz4740/timer.c void __iomem *jz4740_timer_base;
jz4740_timer_base   16 arch/mips/jz4740/timer.c EXPORT_SYMBOL_GPL(jz4740_timer_base);
jz4740_timer_base   20 arch/mips/jz4740/timer.c 	writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
jz4740_timer_base   26 arch/mips/jz4740/timer.c 	writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
jz4740_timer_base   32 arch/mips/jz4740/timer.c 	jz4740_timer_base = ioremap(JZ4740_TCU_BASE_ADDR, 0x100);
jz4740_timer_base   34 arch/mips/jz4740/timer.c 	if (!jz4740_timer_base)
jz4740_timer_base   38 arch/mips/jz4740/timer.c 	writel(0x000100fc, jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
jz4740_timer_base   41 arch/mips/jz4740/timer.c 	writel(0x00ff00ff, jz4740_timer_base + JZ_REG_TIMER_MASK_SET);