irqmask 395 arch/alpha/kernel/err_titan.c u64 irqmask; irqmask 461 arch/alpha/kernel/err_titan.c irqmask = tmchk->c_dirx & TITAN_MCHECK_INTERRUPT_MASK; irqmask 462 arch/alpha/kernel/err_titan.c titan_dispatch_irqs(irqmask); irqmask 715 arch/alpha/kernel/err_titan.c u64 irqmask; irqmask 749 arch/alpha/kernel/err_titan.c irqmask = tmchk->c_dirx & PRIVATEER_680_INTERRUPT_MASK; irqmask 754 arch/alpha/kernel/err_titan.c titan_dispatch_irqs(irqmask); irqmask 103 arch/arm/include/asm/ecard.h unsigned char irqmask; /* IRQ mask */ irqmask 148 arch/arm/include/asm/ecard.h unsigned char irqmask; /* IRQ mask */ irqmask 395 arch/arm/mach-rpc/ecard.c return !ec->irqmask || readb(ec->irqaddr) & ec->irqmask; irqmask 515 arch/arm/mach-rpc/ecard.c ec->irqaddr, ec->irqmask, readb(ec->irqaddr)); irqmask 921 arch/arm/mach-rpc/ecard.c ec->cid.irqmask = cid.r_irqmask; irqmask 929 arch/arm/mach-rpc/ecard.c ec->irqmask = ec->cid.irqmask; irqmask 934 arch/arm/mach-rpc/ecard.c ec->irqmask = 1; irqmask 55 arch/mips/include/asm/mach-netlogic/multi-node.h uint64_t irqmask; /* EIMR for the node */ irqmask 218 arch/mips/netlogic/common/irq.c nodep->irqmask = PERCPU_IRQ_MASK; irqmask 223 arch/mips/netlogic/common/irq.c nodep->irqmask |= 1ull << i; irqmask 242 arch/mips/netlogic/common/irq.c write_c0_eimr(nlm_get_node(node)->irqmask); irqmask 347 arch/mips/netlogic/common/irq.c write_c0_eimr(nlm_current_node()->irqmask); irqmask 191 arch/mips/sni/rm200.c int irqmask = 1 << irq; irqmask 195 arch/mips/sni/rm200.c value = readb(rm200_pic_master + PIC_CMD) & irqmask; irqmask 200 arch/mips/sni/rm200.c value = readb(rm200_pic_slave + PIC_CMD) & (irqmask >> 8); irqmask 213 arch/mips/sni/rm200.c unsigned int irqmask, irq = d->irq - RM200_I8259A_IRQ_BASE; irqmask 216 arch/mips/sni/rm200.c irqmask = 1 << irq; irqmask 233 arch/mips/sni/rm200.c if (rm200_cached_irq_mask & irqmask) irqmask 235 arch/mips/sni/rm200.c rm200_cached_irq_mask |= irqmask; irqmask 268 arch/mips/sni/rm200.c if (!(spurious_irq_mask & irqmask)) { irqmask 271 arch/mips/sni/rm200.c spurious_irq_mask |= irqmask; irqmask 130 arch/x86/kernel/i8259.c int irqmask = 1<<irq; irqmask 134 arch/x86/kernel/i8259.c value = inb(PIC_MASTER_CMD) & irqmask; irqmask 139 arch/x86/kernel/i8259.c value = inb(PIC_SLAVE_CMD) & (irqmask >> 8); irqmask 153 arch/x86/kernel/i8259.c unsigned int irqmask = 1 << irq; irqmask 172 arch/x86/kernel/i8259.c if (cached_irq_mask & irqmask) irqmask 174 arch/x86/kernel/i8259.c cached_irq_mask |= irqmask; irqmask 209 arch/x86/kernel/i8259.c if (!(spurious_irq_mask & irqmask)) { irqmask 212 arch/x86/kernel/i8259.c spurious_irq_mask |= irqmask; irqmask 824 drivers/ata/pata_hpt37x.c u8 irqmask; irqmask 916 drivers/ata/pata_hpt37x.c pci_read_config_byte(dev, 0x5A, &irqmask); irqmask 917 drivers/ata/pata_hpt37x.c irqmask &= ~0x10; irqmask 918 drivers/ata/pata_hpt37x.c pci_write_config_byte(dev, 0x5a, irqmask); irqmask 495 drivers/ata/pata_hpt3x2n.c u8 irqmask; irqmask 544 drivers/ata/pata_hpt3x2n.c pci_read_config_byte(dev, 0x5A, &irqmask); irqmask 545 drivers/ata/pata_hpt3x2n.c irqmask &= ~0x10; irqmask 546 drivers/ata/pata_hpt3x2n.c pci_write_config_byte(dev, 0x5a, irqmask); irqmask 67 drivers/ata/pata_icside.c unsigned int irqmask; irqmask 384 drivers/ata/pata_icside.c info->irqmask = 1; irqmask 445 drivers/ata/pata_icside.c ec->irqmask = info->irqmask; irqmask 21 drivers/clocksource/timer-atmel-st.c static u32 irqmask; irqmask 53 drivers/clocksource/timer-atmel-st.c sr &= irqmask; irqmask 108 drivers/clocksource/timer-atmel-st.c irqmask = 0; irqmask 109 drivers/clocksource/timer-atmel-st.c regmap_write(regmap_st, AT91_ST_IER, irqmask); irqmask 121 drivers/clocksource/timer-atmel-st.c irqmask = AT91_ST_ALMS; irqmask 123 drivers/clocksource/timer-atmel-st.c regmap_write(regmap_st, AT91_ST_IER, irqmask); irqmask 132 drivers/clocksource/timer-atmel-st.c irqmask = AT91_ST_PITS; irqmask 134 drivers/clocksource/timer-atmel-st.c regmap_write(regmap_st, AT91_ST_IER, irqmask); irqmask 20 drivers/gpio/gpio-sa1100.c u32 irqmask; irqmask 115 drivers/gpio/gpio-sa1100.c grer = sgc->irqrising & sgc->irqmask; irqmask 116 drivers/gpio/gpio-sa1100.c gfer = sgc->irqfalling & sgc->irqmask; irqmask 162 drivers/gpio/gpio-sa1100.c sgc->irqmask &= ~mask; irqmask 172 drivers/gpio/gpio-sa1100.c sgc->irqmask |= mask; irqmask 550 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c return mdp4_crtc->vblank.irqmask; irqmask 635 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_crtc->vblank.irqmask = dma2irq(mdp4_crtc->dma); irqmask 638 drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c mdp4_crtc->err.irqmask = dma2err(mdp4_crtc->dma); irqmask 13 drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c void mdp4_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask, irqmask 17 drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c irqmask ^ (irqmask & old_irqmask)); irqmask 18 drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c mdp4_write(to_mdp4_kms(mdp_kms), REG_MDP4_INTR_ENABLE, irqmask); irqmask 51 drivers/gpu/drm/msm/disp/mdp4/mdp4_irq.c error_handler->irqmask = MDP4_IRQ_PRIMARY_INTF_UDERRUN | irqmask 158 drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h void mdp4_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask, irqmask 743 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_crtc->vblank.irqmask = mdp5_cstate->vblank_irqmask; irqmask 744 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_crtc->err.irqmask = mdp5_cstate->err_irqmask; irqmask 745 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c mdp5_crtc->pp_done.irqmask = mdp5_cstate->pp_done_irqmask; irqmask 1150 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c return mdp5_crtc->vblank.irqmask; irqmask 15 drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c void mdp5_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask, irqmask 19 drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c irqmask ^ (irqmask & old_irqmask)); irqmask 20 drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c mdp5_write(to_mdp5_kms(mdp_kms), REG_MDP5_INTR_EN, irqmask); irqmask 58 drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c error_handler->irqmask = MDP5_IRQ_INTF0_UNDER_RUN | irqmask 262 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h void mdp5_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask, irqmask 24 drivers/gpu/drm/msm/disp/mdp_kms.c uint32_t irqmask = mdp_kms->vblank_mask; irqmask 29 drivers/gpu/drm/msm/disp/mdp_kms.c irqmask |= irq->irqmask; irqmask 31 drivers/gpu/drm/msm/disp/mdp_kms.c mdp_kms->funcs->set_irqmask(mdp_kms, irqmask, mdp_kms->cur_irq_mask); irqmask 32 drivers/gpu/drm/msm/disp/mdp_kms.c mdp_kms->cur_irq_mask = irqmask; irqmask 54 drivers/gpu/drm/msm/disp/mdp_kms.c if (handler->irqmask & status) { irqmask 56 drivers/gpu/drm/msm/disp/mdp_kms.c handler->irq(handler, handler->irqmask & status); irqmask 87 drivers/gpu/drm/msm/disp/mdp_kms.c void mdp_irq_wait(struct mdp_kms *mdp_kms, uint32_t irqmask) irqmask 92 drivers/gpu/drm/msm/disp/mdp_kms.c .irqmask = irqmask, irqmask 22 drivers/gpu/drm/msm/disp/mdp_kms.h void (*set_irqmask)(struct mdp_kms *mdp_kms, uint32_t irqmask, irqmask 59 drivers/gpu/drm/msm/disp/mdp_kms.h uint32_t irqmask; irqmask 66 drivers/gpu/drm/msm/disp/mdp_kms.h void mdp_irq_wait(struct mdp_kms *mdp_kms, uint32_t irqmask); irqmask 14 drivers/gpu/drm/omapdrm/omap_irq.c u32 irqmask; irqmask 23 drivers/gpu/drm/omapdrm/omap_irq.c u32 irqmask = priv->irq_mask; irqmask 28 drivers/gpu/drm/omapdrm/omap_irq.c irqmask |= wait->irqmask; irqmask 30 drivers/gpu/drm/omapdrm/omap_irq.c DBG("irqmask=%08x", irqmask); irqmask 32 drivers/gpu/drm/omapdrm/omap_irq.c priv->dispc_ops->write_irqenable(priv->dispc, irqmask); irqmask 42 drivers/gpu/drm/omapdrm/omap_irq.c u32 irqmask, int count) irqmask 49 drivers/gpu/drm/omapdrm/omap_irq.c wait->irqmask = irqmask; irqmask 243 drivers/gpu/drm/omapdrm/omap_irq.c if (wait->irqmask & irqstatus) irqmask 25 drivers/gpu/drm/omapdrm/omap_irq.h u32 irqmask, int count); irqmask 425 drivers/ide/icside.c ec->irqmask = 1; irqmask 114 drivers/irqchip/irq-i8259.c int irqmask = 1 << irq; irqmask 118 drivers/irqchip/irq-i8259.c value = inb(PIC_MASTER_CMD) & irqmask; irqmask 123 drivers/irqchip/irq-i8259.c value = inb(PIC_SLAVE_CMD) & (irqmask >> 8); irqmask 136 drivers/irqchip/irq-i8259.c unsigned int irqmask, irq = d->irq - I8259A_IRQ_BASE; irqmask 139 drivers/irqchip/irq-i8259.c irqmask = 1 << irq; irqmask 156 drivers/irqchip/irq-i8259.c if (cached_irq_mask & irqmask) irqmask 158 drivers/irqchip/irq-i8259.c cached_irq_mask |= irqmask; irqmask 191 drivers/irqchip/irq-i8259.c if (!(spurious_irq_mask & irqmask)) { irqmask 193 drivers/irqchip/irq-i8259.c spurious_irq_mask |= irqmask; irqmask 316 drivers/media/pci/ivtv/ivtv-driver.c itv->irqmask &= ~mask; irqmask 317 drivers/media/pci/ivtv/ivtv-driver.c write_reg_sync(itv->irqmask, IVTV_REG_IRQMASK); irqmask 322 drivers/media/pci/ivtv/ivtv-driver.c itv->irqmask |= mask; irqmask 323 drivers/media/pci/ivtv/ivtv-driver.c write_reg_sync(itv->irqmask, IVTV_REG_IRQMASK); irqmask 684 drivers/media/pci/ivtv/ivtv-driver.h u32 irqmask; /* active interrupts */ irqmask 930 drivers/media/pci/ivtv/ivtv-irq.c combo = ~itv->irqmask & stat; irqmask 939 drivers/media/pci/ivtv/ivtv-irq.c if (~itv->irqmask & IVTV_IRQ_DEC_VSYNC) { irqmask 1005 drivers/media/pci/ivtv/ivtv-irq.c if (~itv->irqmask & IVTV_IRQ_DEC_VSYNC) { irqmask 769 drivers/media/pci/ivtv/ivtv-streams.c IVTV_DEBUG_IRQ("IRQ Mask is now: 0x%08x\n", itv->irqmask); irqmask 79 drivers/media/pci/tw5864/tw5864-core.c tw_writel(TW5864_INTR_ENABLE_L, dev->irqmask & 0xffff); irqmask 80 drivers/media/pci/tw5864/tw5864-core.c tw_writel(TW5864_INTR_ENABLE_H, (dev->irqmask >> 16)); irqmask 88 drivers/media/pci/tw5864/tw5864-core.c dev->irqmask = 0; irqmask 1057 drivers/media/pci/tw5864/tw5864-video.c dev->irqmask |= TW5864_INTR_VLC_DONE | TW5864_INTR_TIMER; irqmask 163 drivers/media/pci/tw5864/tw5864.h u32 irqmask; irqmask 198 drivers/media/rc/winbond-cir.c u8 irqmask; irqmask 248 drivers/media/rc/winbond-cir.c wbcir_set_irqmask(struct wbcir_data *data, u8 irqmask) irqmask 250 drivers/media/rc/winbond-cir.c if (data->irqmask == irqmask) irqmask 254 drivers/media/rc/winbond-cir.c outb(irqmask, data->sbase + WBCIR_REG_SP3_IER); irqmask 255 drivers/media/rc/winbond-cir.c data->irqmask = irqmask; irqmask 464 drivers/media/rc/winbond-cir.c status &= data->irqmask; irqmask 993 drivers/mmc/host/mmci.c unsigned int datactrl, timeout, irqmask; irqmask 1052 drivers/mmc/host/mmci.c irqmask = MCI_RXFIFOHALFFULLMASK; irqmask 1060 drivers/mmc/host/mmci.c irqmask |= MCI_RXDATAAVLBLMASK; irqmask 1066 drivers/mmc/host/mmci.c irqmask = MCI_TXFIFOHALFEMPTYMASK; irqmask 1071 drivers/mmc/host/mmci.c mmci_set_mask1(host, irqmask); irqmask 2246 drivers/net/ethernet/cortina/gemini.c unsigned long irqmask = SWFQ_EMPTY_INT_BIT; irqmask 2257 drivers/net/ethernet/cortina/gemini.c writel(irqmask, geth->base + GLOBAL_INTERRUPT_STATUS_4_REG); irqmask 2259 drivers/net/ethernet/cortina/gemini.c irqmask |= readl(geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); irqmask 2260 drivers/net/ethernet/cortina/gemini.c writel(irqmask, geth->base + GLOBAL_INTERRUPT_ENABLE_4_REG); irqmask 783 drivers/net/ethernet/nvidia/forcedeth.c u32 irqmask; irqmask 3620 drivers/net/ethernet/nvidia/forcedeth.c if (np->irqmask != NVREG_IRQMASK_CPU) { irqmask 3621 drivers/net/ethernet/nvidia/forcedeth.c np->irqmask = NVREG_IRQMASK_CPU; irqmask 3630 drivers/net/ethernet/nvidia/forcedeth.c if (np->irqmask != NVREG_IRQMASK_THROUGHPUT) { irqmask 3631 drivers/net/ethernet/nvidia/forcedeth.c np->irqmask = NVREG_IRQMASK_THROUGHPUT; irqmask 3653 drivers/net/ethernet/nvidia/forcedeth.c if (!(np->events & np->irqmask)) irqmask 3686 drivers/net/ethernet/nvidia/forcedeth.c if (!(np->events & np->irqmask)) irqmask 3715 drivers/net/ethernet/nvidia/forcedeth.c if (!(events & np->irqmask)) irqmask 3795 drivers/net/ethernet/nvidia/forcedeth.c np->nic_poll_irq = np->irqmask; irqmask 3809 drivers/net/ethernet/nvidia/forcedeth.c writel(np->irqmask, base + NvRegIrqMask); irqmask 3827 drivers/net/ethernet/nvidia/forcedeth.c if (!(events & np->irqmask)) irqmask 3872 drivers/net/ethernet/nvidia/forcedeth.c if (!(events & np->irqmask)) irqmask 3953 drivers/net/ethernet/nvidia/forcedeth.c static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask) irqmask 3964 drivers/net/ethernet/nvidia/forcedeth.c if ((irqmask >> i) & 0x1) irqmask 3971 drivers/net/ethernet/nvidia/forcedeth.c if ((irqmask >> (i + 8)) & 0x1) irqmask 4141 drivers/net/ethernet/nvidia/forcedeth.c mask = np->irqmask; irqmask 5244 drivers/net/ethernet/nvidia/forcedeth.c nv_disable_hw_interrupts(dev, np->irqmask); irqmask 5298 drivers/net/ethernet/nvidia/forcedeth.c nv_enable_hw_interrupts(dev, np->irqmask); irqmask 5527 drivers/net/ethernet/nvidia/forcedeth.c nv_disable_hw_interrupts(dev, np->irqmask); irqmask 5537 drivers/net/ethernet/nvidia/forcedeth.c nv_enable_hw_interrupts(dev, np->irqmask); irqmask 5610 drivers/net/ethernet/nvidia/forcedeth.c nv_disable_hw_interrupts(dev, np->irqmask); irqmask 5944 drivers/net/ethernet/nvidia/forcedeth.c np->irqmask = NVREG_IRQMASK_CPU; irqmask 5950 drivers/net/ethernet/nvidia/forcedeth.c np->irqmask = NVREG_IRQMASK_THROUGHPUT; irqmask 5955 drivers/net/ethernet/nvidia/forcedeth.c np->irqmask = NVREG_IRQMASK_THROUGHPUT; irqmask 5961 drivers/net/ethernet/nvidia/forcedeth.c np->irqmask |= NVREG_IRQ_TIMER; irqmask 777 drivers/net/ethernet/seeq/ether3.c ec->irqmask = 0xf0; irqmask 74 drivers/net/wireless/mediatek/mt76/mmio.c dev->mmio.irqmask &= ~clear; irqmask 75 drivers/net/wireless/mediatek/mt76/mmio.c dev->mmio.irqmask |= set; irqmask 76 drivers/net/wireless/mediatek/mt76/mmio.c mt76_mmio_wr(dev, addr, dev->mmio.irqmask); irqmask 421 drivers/net/wireless/mediatek/mt76/mt76.h u32 irqmask; irqmask 23 drivers/net/wireless/mediatek/mt76/mt7603/core.c intr &= dev->mt76.mmio.irqmask; irqmask 1278 drivers/net/wireless/mediatek/mt76/mt7603/mac.c u32 mask = dev->mt76.mmio.irqmask; irqmask 49 drivers/net/wireless/mediatek/mt76/mt7615/pci.c intr &= dev->mt76.mmio.irqmask; irqmask 267 drivers/net/wireless/mediatek/mt76/mt76x02_mmio.c trace_dev_irq(dev, intr, dev->mt76.mmio.irqmask); irqmask 269 drivers/net/wireless/mediatek/mt76/mt76x02_mmio.c intr &= dev->mt76.mmio.irqmask; irqmask 438 drivers/net/wireless/mediatek/mt76/mt76x02_mmio.c u32 mask = dev->mt76.mmio.irqmask; irqmask 46 drivers/regulator/lp8755.c unsigned int irqmask; irqmask 370 drivers/regulator/lp8755.c && (pchip->irqmask & (0x04 << icnt)) irqmask 389 drivers/regulator/lp8755.c if ((flag1 & 0x01) && (pchip->irqmask & 0x01)) irqmask 400 drivers/regulator/lp8755.c if ((flag1 & 0x02) && (pchip->irqmask & 0x02)) irqmask 432 drivers/regulator/lp8755.c pchip->irqmask = regval; irqmask 2922 drivers/scsi/arm/acornscsi.c ec->irqmask = 0x0a; irqmask 297 drivers/scsi/arm/arxescsi.c ec->irqmask = CSTATUS_IRQ; irqmask 420 drivers/scsi/arm/cumana_2.c ec->irqmask = STATUS_INT; irqmask 539 drivers/scsi/arm/eesox.c ec->irqmask = EESOX_STAT_INTR; irqmask 346 drivers/scsi/arm/powertec.c ec->irqmask = POWERTEC_INTR_BIT; irqmask 631 drivers/video/fbdev/omap2/omapfb/dss/dispc-compat.c int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask, irqmask 640 drivers/video/fbdev/omap2/omapfb/dss/dispc-compat.c irqmask); irqmask 648 drivers/video/fbdev/omap2/omapfb/dss/dispc-compat.c omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask); irqmask 13 drivers/video/fbdev/omap2/omapfb/dss/dispc-compat.h int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask, irqmask 1429 sound/isa/es18xx.c int irqmask, dma1mask, dma2mask; irqmask 1433 sound/isa/es18xx.c irqmask = 0; irqmask 1436 sound/isa/es18xx.c irqmask = 1; irqmask 1439 sound/isa/es18xx.c irqmask = 2; irqmask 1442 sound/isa/es18xx.c irqmask = 3; irqmask 1481 sound/isa/es18xx.c snd_es18xx_write(chip, 0xB1, 0x50 | (irqmask << 2)); irqmask 1498 sound/isa/es18xx.c snd_es18xx_mixer_write(chip, 0x7f, ((irqmask + 1) << 1) | 0x01); irqmask 191 sound/pci/es1938.c unsigned char irqmask; irqmask 199 sound/pci/sonicvibes.c unsigned char irqmask; irqmask 613 sound/pci/sonicvibes.c outb(sonic->irqmask = ~0, SV_REG(sonic, IRQMASK)); irqmask 1344 sound/pci/sonicvibes.c outb(sonic->irqmask = ~(SV_DMAA_MASK | SV_DMAC_MASK | SV_UD_MASK), SV_REG(sonic, IRQMASK)); irqmask 1405 sound/pci/sonicvibes.c outb(sonic->irqmask &= ~SV_MIDI_MASK, SV_REG(sonic, IRQMASK)); irqmask 1412 sound/pci/sonicvibes.c outb(sonic->irqmask |= SV_MIDI_MASK, SV_REG(sonic, IRQMASK));