irqcontroller      28 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	} irqcontroller;
irqcontroller      54 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 				mdp5_mdss->irqcontroller.domain, hwirq));
irqcontroller      77 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	clear_bit(irqd->hwirq, &mdp5_mdss->irqcontroller.enabled_mask);
irqcontroller      86 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	set_bit(irqd->hwirq, &mdp5_mdss->irqcontroller.enabled_mask);
irqcontroller     128 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	mdp5_mdss->irqcontroller.enabled_mask = 0;
irqcontroller     129 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	mdp5_mdss->irqcontroller.domain = d;
irqcontroller     190 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	irq_domain_remove(mdp5_mdss->irqcontroller.domain);
irqcontroller     191 drivers/gpu/drm/msm/disp/mdp5/mdp5_mdss.c 	mdp5_mdss->irqcontroller.domain = NULL;