irq_pipe_mask 284 drivers/gpu/drm/i915/display/intel_display_power.c u8 irq_pipe_mask, bool has_vga) irq_pipe_mask 304 drivers/gpu/drm/i915/display/intel_display_power.c if (irq_pipe_mask) irq_pipe_mask 305 drivers/gpu/drm/i915/display/intel_display_power.c gen8_irq_power_well_post_enable(dev_priv, irq_pipe_mask); irq_pipe_mask 309 drivers/gpu/drm/i915/display/intel_display_power.c u8 irq_pipe_mask) irq_pipe_mask 311 drivers/gpu/drm/i915/display/intel_display_power.c if (irq_pipe_mask) irq_pipe_mask 312 drivers/gpu/drm/i915/display/intel_display_power.c gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask); irq_pipe_mask 424 drivers/gpu/drm/i915/display/intel_display_power.c power_well->desc->hsw.irq_pipe_mask, irq_pipe_mask 436 drivers/gpu/drm/i915/display/intel_display_power.c power_well->desc->hsw.irq_pipe_mask); irq_pipe_mask 2750 drivers/gpu/drm/i915/display/intel_display_power.c .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), irq_pipe_mask 2951 drivers/gpu/drm/i915/display/intel_display_power.c .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), irq_pipe_mask 3033 drivers/gpu/drm/i915/display/intel_display_power.c .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), irq_pipe_mask 3093 drivers/gpu/drm/i915/display/intel_display_power.c .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), irq_pipe_mask 3262 drivers/gpu/drm/i915/display/intel_display_power.c .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C), irq_pipe_mask 3401 drivers/gpu/drm/i915/display/intel_display_power.c .hsw.irq_pipe_mask = BIT(PIPE_B), irq_pipe_mask 3583 drivers/gpu/drm/i915/display/intel_display_power.c .hsw.irq_pipe_mask = BIT(PIPE_C), irq_pipe_mask 3634 drivers/gpu/drm/i915/display/intel_display_power.c .hsw.irq_pipe_mask = BIT(PIPE_B), irq_pipe_mask 3900 drivers/gpu/drm/i915/display/intel_display_power.c .hsw.irq_pipe_mask = BIT(PIPE_C), irq_pipe_mask 3912 drivers/gpu/drm/i915/display/intel_display_power.c .hsw.irq_pipe_mask = BIT(PIPE_D), irq_pipe_mask 189 drivers/gpu/drm/i915/display/intel_display_power.h u8 irq_pipe_mask;