irq_enable_mask    25 arch/mips/include/asm/mach-loongson64/mmzone.h 	unsigned long irq_enable_mask[2];
irq_enable_mask    33 arch/mips/sgi-ip27/ip27-irq.c static DEFINE_PER_CPU(unsigned long [2], irq_enable_mask);
irq_enable_mask    53 arch/mips/sgi-ip27/ip27-irq.c 	unsigned long *mask = per_cpu(irq_enable_mask, hd->cpu);
irq_enable_mask    63 arch/mips/sgi-ip27/ip27-irq.c 	unsigned long *mask = per_cpu(irq_enable_mask, hd->cpu);
irq_enable_mask   190 arch/mips/sgi-ip27/ip27-irq.c 	unsigned long *mask = per_cpu(irq_enable_mask, cpu);
irq_enable_mask   232 arch/mips/sgi-ip27/ip27-irq.c 	unsigned long *mask = per_cpu(irq_enable_mask, cpu);
irq_enable_mask   257 arch/mips/sgi-ip27/ip27-irq.c 	unsigned long *mask = per_cpu(irq_enable_mask, cpu);
irq_enable_mask    37 drivers/dma/ti/omap-dma.c 	uint32_t irq_enable_mask;
irq_enable_mask   604 drivers/dma/ti/omap-dma.c 	status &= od->irq_enable_mask;
irq_enable_mask   662 drivers/dma/ti/omap-dma.c 			od->irq_enable_mask |= val;
irq_enable_mask   663 drivers/dma/ti/omap-dma.c 			omap_dma_glbl_write(od, IRQENABLE_L1, od->irq_enable_mask);
irq_enable_mask   697 drivers/dma/ti/omap-dma.c 		od->irq_enable_mask &= ~BIT(c->dma_ch);
irq_enable_mask   698 drivers/dma/ti/omap-dma.c 		omap_dma_glbl_write(od, IRQENABLE_L1, od->irq_enable_mask);
irq_enable_mask  1555 drivers/dma/ti/omap-dma.c 		od->irq_enable_mask = 0;
irq_enable_mask   404 drivers/gpu/drm/i915/gt/intel_engine_types.h 	u32		irq_enable_mask; /* bitmask to enable ring interrupt */
irq_enable_mask  2729 drivers/gpu/drm/i915/gt/intel_lrc.c 		     ~(engine->irq_enable_mask | engine->irq_keep_mask));
irq_enable_mask  3075 drivers/gpu/drm/i915/gt/intel_lrc.c 	engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;
irq_enable_mask   987 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	gen5_gt_enable_irq(engine->gt, engine->irq_enable_mask);
irq_enable_mask   993 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	gen5_gt_disable_irq(engine->gt, engine->irq_enable_mask);
irq_enable_mask   999 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	engine->i915->irq_mask &= ~engine->irq_enable_mask;
irq_enable_mask  1007 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	engine->i915->irq_mask |= engine->irq_enable_mask;
irq_enable_mask  1016 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	i915->irq_mask &= ~engine->irq_enable_mask;
irq_enable_mask  1026 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	i915->irq_mask |= engine->irq_enable_mask;
irq_enable_mask  1049 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		     ~(engine->irq_enable_mask | engine->irq_keep_mask));
irq_enable_mask  1054 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	gen5_gt_enable_irq(engine->gt, engine->irq_enable_mask);
irq_enable_mask  1061 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	gen5_gt_disable_irq(engine->gt, engine->irq_enable_mask);
irq_enable_mask  1067 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	ENGINE_WRITE(engine, RING_IMR, ~engine->irq_enable_mask);
irq_enable_mask  1072 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	gen6_gt_pm_unmask_irq(engine->gt, engine->irq_enable_mask);
irq_enable_mask  1079 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	gen6_gt_pm_mask_irq(engine->gt, engine->irq_enable_mask);
irq_enable_mask  2237 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
irq_enable_mask  2252 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		engine->irq_enable_mask = I915_USER_INTERRUPT;
irq_enable_mask  2270 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
irq_enable_mask  2279 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 			engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
irq_enable_mask  2281 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 			engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
irq_enable_mask  2290 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
irq_enable_mask  2305 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
irq_enable_mask    97 drivers/gpu/drm/via/via_drv.h 	uint32_t irq_enable_mask;
irq_enable_mask   268 drivers/gpu/drm/via/via_irq.c 		dev_priv->irq_enable_mask = VIA_IRQ_VBLANK_ENABLE;
irq_enable_mask   287 drivers/gpu/drm/via/via_irq.c 			dev_priv->irq_enable_mask |= cur_irq->enable_mask;
irq_enable_mask   299 drivers/gpu/drm/via/via_irq.c 			  ~(dev_priv->irq_enable_mask));
irq_enable_mask   317 drivers/gpu/drm/via/via_irq.c 		  | dev_priv->irq_enable_mask);
irq_enable_mask   341 drivers/gpu/drm/via/via_irq.c 			  ~(VIA_IRQ_VBLANK_ENABLE | dev_priv->irq_enable_mask));
irq_enable_mask   138 drivers/pinctrl/pinctrl-single.c 	unsigned irq_enable_mask;
irq_enable_mask   671 drivers/pinctrl/pinctrl-single.c 	if (pcs_soc->irq_enable_mask) {
irq_enable_mask   675 drivers/pinctrl/pinctrl-single.c 		if (val & pcs_soc->irq_enable_mask) {
irq_enable_mask   678 drivers/pinctrl/pinctrl-single.c 			val &= ~pcs_soc->irq_enable_mask;
irq_enable_mask  1381 drivers/pinctrl/pinctrl-single.c 		soc_mask = pcs_soc->irq_enable_mask;
irq_enable_mask  1553 drivers/pinctrl/pinctrl-single.c 	if (!pcs_soc->irq_enable_mask ||
irq_enable_mask  1916 drivers/pinctrl/pinctrl-single.c 	.irq_enable_mask = (1 << 14),	/* OMAP_WAKEUP_EN */
irq_enable_mask  1921 drivers/pinctrl/pinctrl-single.c 	.irq_enable_mask = (1 << 24),	/* WAKEUPENABLE */
irq_enable_mask  1927 drivers/pinctrl/pinctrl-single.c 	.irq_enable_mask = (1 << 29),   /* OMAP_WAKEUP_EN */