irq_ena           107 drivers/clocksource/timer-ti-dm.c 	writel_relaxed(timer->context.tier, timer->irq_ena);
irq_ena           693 drivers/clocksource/timer-ti-dm.c 		l = readl_relaxed(timer->irq_ena) & ~mask;
irq_ena           230 drivers/gpu/drm/armada/armada_crtc.c 	if (dcrtc->irq_ena & mask) {
irq_ena           231 drivers/gpu/drm/armada/armada_crtc.c 		dcrtc->irq_ena &= ~mask;
irq_ena           232 drivers/gpu/drm/armada/armada_crtc.c 		writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
irq_ena           238 drivers/gpu/drm/armada/armada_crtc.c 	if ((dcrtc->irq_ena & mask) != mask) {
irq_ena           239 drivers/gpu/drm/armada/armada_crtc.c 		dcrtc->irq_ena |= mask;
irq_ena           240 drivers/gpu/drm/armada/armada_crtc.c 		writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
irq_ena           274 drivers/gpu/drm/armada/armada_crtc.c 	if (stat & dcrtc->irq_ena & DUMB_FRAMEDONE) {
irq_ena           320 drivers/gpu/drm/armada/armada_crtc.c 	v = stat & dcrtc->irq_ena;
irq_ena           929 drivers/gpu/drm/armada/armada_crtc.c 	dcrtc->irq_ena = CLEAN_SPU_IRQ_ISR;
irq_ena           941 drivers/gpu/drm/armada/armada_crtc.c 	writel_relaxed(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
irq_ena            63 drivers/gpu/drm/armada/armada_crtc.h 	uint32_t		irq_ena;
irq_ena           103 include/clocksource/timer-ti-dm.h 	void __iomem	*irq_ena;	/* irq enable */
irq_ena           284 include/clocksource/timer-ti-dm.h 		timer->irq_ena = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
irq_ena           291 include/clocksource/timer-ti-dm.h 		timer->irq_ena = timer->io_base + OMAP_TIMER_V2_IRQENABLE_SET;
irq_ena           378 include/clocksource/timer-ti-dm.h 	writel_relaxed(value, timer->irq_ena);