ipu_ch             88 drivers/gpu/drm/imx/ipuv3-plane.c 	return ipu_idmac_channel_irq(ipu_plane->ipu, ipu_plane->ipu_ch,
ipu_ch            151 drivers/gpu/drm/imx/ipuv3-plane.c 	if (!IS_ERR_OR_NULL(ipu_plane->ipu_ch))
ipu_ch            152 drivers/gpu/drm/imx/ipuv3-plane.c 		ipu_idmac_put(ipu_plane->ipu_ch);
ipu_ch            162 drivers/gpu/drm/imx/ipuv3-plane.c 	ipu_plane->ipu_ch = ipu_idmac_get(ipu_plane->ipu, ipu_plane->dma);
ipu_ch            163 drivers/gpu/drm/imx/ipuv3-plane.c 	if (IS_ERR(ipu_plane->ipu_ch)) {
ipu_ch            164 drivers/gpu/drm/imx/ipuv3-plane.c 		ret = PTR_ERR(ipu_plane->ipu_ch);
ipu_ch            223 drivers/gpu/drm/imx/ipuv3-plane.c 	ipu_idmac_enable_channel(ipu_plane->ipu_ch);
ipu_ch            236 drivers/gpu/drm/imx/ipuv3-plane.c 	ret = ipu_idmac_wait_busy(ipu_plane->ipu_ch, 50);
ipu_ch            244 drivers/gpu/drm/imx/ipuv3-plane.c 	ipu_idmac_disable_channel(ipu_plane->ipu_ch);
ipu_ch            251 drivers/gpu/drm/imx/ipuv3-plane.c 		ipu_prg_channel_disable(ipu_plane->ipu_ch);
ipu_ch            592 drivers/gpu/drm/imx/ipuv3-plane.c 		ipu_prg_channel_configure(ipu_plane->ipu_ch, axi_id,
ipu_ch            603 drivers/gpu/drm/imx/ipuv3-plane.c 		active = ipu_idmac_get_current_buffer(ipu_plane->ipu_ch);
ipu_ch            604 drivers/gpu/drm/imx/ipuv3-plane.c 		ipu_cpmem_set_buffer(ipu_plane->ipu_ch, !active, eba);
ipu_ch            605 drivers/gpu/drm/imx/ipuv3-plane.c 		ipu_idmac_select_buffer(ipu_plane->ipu_ch, !active);
ipu_ch            634 drivers/gpu/drm/imx/ipuv3-plane.c 	ipu_cpmem_zero(ipu_plane->ipu_ch);
ipu_ch            635 drivers/gpu/drm/imx/ipuv3-plane.c 	ipu_cpmem_set_resolution(ipu_plane->ipu_ch, width, height);
ipu_ch            636 drivers/gpu/drm/imx/ipuv3-plane.c 	ipu_cpmem_set_fmt(ipu_plane->ipu_ch, fb->format->format);
ipu_ch            637 drivers/gpu/drm/imx/ipuv3-plane.c 	ipu_cpmem_set_burstsize(ipu_plane->ipu_ch, burstsize);
ipu_ch            638 drivers/gpu/drm/imx/ipuv3-plane.c 	ipu_cpmem_set_high_priority(ipu_plane->ipu_ch);
ipu_ch            639 drivers/gpu/drm/imx/ipuv3-plane.c 	ipu_idmac_enable_watermark(ipu_plane->ipu_ch, true);
ipu_ch            640 drivers/gpu/drm/imx/ipuv3-plane.c 	ipu_idmac_set_double_buffer(ipu_plane->ipu_ch, 1);
ipu_ch            641 drivers/gpu/drm/imx/ipuv3-plane.c 	ipu_cpmem_set_stride(ipu_plane->ipu_ch, fb->pitches[0]);
ipu_ch            642 drivers/gpu/drm/imx/ipuv3-plane.c 	ipu_cpmem_set_axi_id(ipu_plane->ipu_ch, axi_id);
ipu_ch            658 drivers/gpu/drm/imx/ipuv3-plane.c 		ipu_cpmem_set_yuv_planar_full(ipu_plane->ipu_ch,
ipu_ch            669 drivers/gpu/drm/imx/ipuv3-plane.c 		ipu_cpmem_set_yuv_planar_full(ipu_plane->ipu_ch,
ipu_ch            688 drivers/gpu/drm/imx/ipuv3-plane.c 		ipu_cpmem_set_burstsize(ipu_plane->ipu_ch, 16);
ipu_ch            707 drivers/gpu/drm/imx/ipuv3-plane.c 	ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 0, eba);
ipu_ch            708 drivers/gpu/drm/imx/ipuv3-plane.c 	ipu_cpmem_set_buffer(ipu_plane->ipu_ch, 1, eba);
ipu_ch            709 drivers/gpu/drm/imx/ipuv3-plane.c 	ipu_idmac_lock_enable(ipu_plane->ipu_ch, num_bursts);
ipu_ch            731 drivers/gpu/drm/imx/ipuv3-plane.c 		return ipu_prg_channel_configure_pending(ipu_plane->ipu_ch);
ipu_ch             21 drivers/gpu/drm/imx/ipuv3-plane.h 	struct ipuv3_channel	*ipu_ch;
ipu_ch            257 drivers/video/fbdev/mx3fb.c 	enum ipu_channel		ipu_ch;
ipu_ch            826 drivers/video/fbdev/mx3fb.c 	if (mx3_fbi->ipu_ch == IDMAC_SDC_0) {
ipu_ch            865 drivers/video/fbdev/mx3fb.c 	sdc_set_window_pos(mx3fb, mx3_fbi->ipu_ch, 0, 0);
ipu_ch           1491 drivers/video/fbdev/mx3fb.c 	mx3fbi->ipu_ch		= ichan->dma_chan.chan_id;