ippn10             33 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c 	(ippn10->regs->reg)
ippn10             37 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c 	ippn10->ipp_shift->field_name, ippn10->ipp_mask->field_name
ippn10             40 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c 	ippn10->base.ctx
ippn10             63 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c 	struct dcn10_ipp *ippn10,
ippn10             70 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c 	ippn10->base.ctx = ctx;
ippn10             71 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c 	ippn10->base.inst = inst;
ippn10             72 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c 	ippn10->base.funcs = &dcn10_ipp_funcs;
ippn10             74 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c 	ippn10->regs = regs;
ippn10             75 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c 	ippn10->ipp_shift = ipp_shift;
ippn10             76 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c 	ippn10->ipp_mask = ipp_mask;
ippn10             81 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c 	struct dcn10_ipp *ippn10,
ippn10             88 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c 	ippn10->base.ctx = ctx;
ippn10             89 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c 	ippn10->base.inst = inst;
ippn10             90 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c 	ippn10->base.funcs = &dcn20_ipp_funcs;
ippn10             92 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c 	ippn10->regs = regs;
ippn10             93 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c 	ippn10->ipp_shift = ipp_shift;
ippn10             94 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c 	ippn10->ipp_mask = ipp_mask;
ippn10            192 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h void dcn10_ipp_construct(struct dcn10_ipp *ippn10,
ippn10            200 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h void dcn20_ipp_construct(struct dcn10_ipp *ippn10,