ipcc               84 drivers/mailbox/stm32-ipcc.c 	struct stm32_ipcc *ipcc = data;
ipcc               85 drivers/mailbox/stm32-ipcc.c 	struct device *dev = ipcc->controller.dev;
ipcc               91 drivers/mailbox/stm32-ipcc.c 	proc_offset = ipcc->proc_id ? -IPCC_PROC_OFFST : IPCC_PROC_OFFST;
ipcc               92 drivers/mailbox/stm32-ipcc.c 	tosr = readl_relaxed(ipcc->reg_proc + proc_offset + IPCC_XTOYSR);
ipcc               93 drivers/mailbox/stm32-ipcc.c 	mr = readl_relaxed(ipcc->reg_proc + IPCC_XMR);
ipcc               98 drivers/mailbox/stm32-ipcc.c 	for (chan = 0; chan < ipcc->n_chans; chan++) {
ipcc              104 drivers/mailbox/stm32-ipcc.c 		mbox_chan_received_data(&ipcc->controller.chans[chan], NULL);
ipcc              106 drivers/mailbox/stm32-ipcc.c 		stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XSCR,
ipcc              117 drivers/mailbox/stm32-ipcc.c 	struct stm32_ipcc *ipcc = data;
ipcc              118 drivers/mailbox/stm32-ipcc.c 	struct device *dev = ipcc->controller.dev;
ipcc              122 drivers/mailbox/stm32-ipcc.c 	tosr = readl_relaxed(ipcc->reg_proc + IPCC_XTOYSR);
ipcc              123 drivers/mailbox/stm32-ipcc.c 	mr = readl_relaxed(ipcc->reg_proc + IPCC_XMR);
ipcc              128 drivers/mailbox/stm32-ipcc.c 	for (chan = 0; chan < ipcc->n_chans ; chan++) {
ipcc              135 drivers/mailbox/stm32-ipcc.c 		stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,
ipcc              138 drivers/mailbox/stm32-ipcc.c 		mbox_chan_txdone(&ipcc->controller.chans[chan], 0);
ipcc              149 drivers/mailbox/stm32-ipcc.c 	struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc,
ipcc              152 drivers/mailbox/stm32-ipcc.c 	dev_dbg(ipcc->controller.dev, "%s: chan:%d\n", __func__, chan);
ipcc              155 drivers/mailbox/stm32-ipcc.c 	stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XSCR,
ipcc              159 drivers/mailbox/stm32-ipcc.c 	stm32_ipcc_clr_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,
ipcc              168 drivers/mailbox/stm32-ipcc.c 	struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc,
ipcc              172 drivers/mailbox/stm32-ipcc.c 	ret = clk_prepare_enable(ipcc->clk);
ipcc              174 drivers/mailbox/stm32-ipcc.c 		dev_err(ipcc->controller.dev, "can not enable the clock\n");
ipcc              179 drivers/mailbox/stm32-ipcc.c 	stm32_ipcc_clr_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,
ipcc              188 drivers/mailbox/stm32-ipcc.c 	struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc,
ipcc              192 drivers/mailbox/stm32-ipcc.c 	stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,
ipcc              195 drivers/mailbox/stm32-ipcc.c 	clk_disable_unprepare(ipcc->clk);
ipcc              208 drivers/mailbox/stm32-ipcc.c 	struct stm32_ipcc *ipcc;
ipcc              221 drivers/mailbox/stm32-ipcc.c 	ipcc = devm_kzalloc(dev, sizeof(*ipcc), GFP_KERNEL);
ipcc              222 drivers/mailbox/stm32-ipcc.c 	if (!ipcc)
ipcc              225 drivers/mailbox/stm32-ipcc.c 	spin_lock_init(&ipcc->lock);
ipcc              228 drivers/mailbox/stm32-ipcc.c 	if (of_property_read_u32(np, "st,proc-id", &ipcc->proc_id)) {
ipcc              233 drivers/mailbox/stm32-ipcc.c 	if (ipcc->proc_id >= STM32_MAX_PROCS) {
ipcc              234 drivers/mailbox/stm32-ipcc.c 		dev_err(dev, "Invalid proc_id (%d)\n", ipcc->proc_id);
ipcc              240 drivers/mailbox/stm32-ipcc.c 	ipcc->reg_base = devm_ioremap_resource(dev, res);
ipcc              241 drivers/mailbox/stm32-ipcc.c 	if (IS_ERR(ipcc->reg_base))
ipcc              242 drivers/mailbox/stm32-ipcc.c 		return PTR_ERR(ipcc->reg_base);
ipcc              244 drivers/mailbox/stm32-ipcc.c 	ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST;
ipcc              247 drivers/mailbox/stm32-ipcc.c 	ipcc->clk = devm_clk_get(dev, NULL);
ipcc              248 drivers/mailbox/stm32-ipcc.c 	if (IS_ERR(ipcc->clk))
ipcc              249 drivers/mailbox/stm32-ipcc.c 		return PTR_ERR(ipcc->clk);
ipcc              251 drivers/mailbox/stm32-ipcc.c 	ret = clk_prepare_enable(ipcc->clk);
ipcc              259 drivers/mailbox/stm32-ipcc.c 		ipcc->irqs[i] = platform_get_irq_byname(pdev, irq_name[i]);
ipcc              260 drivers/mailbox/stm32-ipcc.c 		if (ipcc->irqs[i] < 0) {
ipcc              261 drivers/mailbox/stm32-ipcc.c 			if (ipcc->irqs[i] != -EPROBE_DEFER)
ipcc              264 drivers/mailbox/stm32-ipcc.c 			ret = ipcc->irqs[i];
ipcc              268 drivers/mailbox/stm32-ipcc.c 		ret = devm_request_threaded_irq(dev, ipcc->irqs[i], NULL,
ipcc              270 drivers/mailbox/stm32-ipcc.c 						dev_name(dev), ipcc);
ipcc              278 drivers/mailbox/stm32-ipcc.c 	stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,
ipcc              280 drivers/mailbox/stm32-ipcc.c 	stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XCR,
ipcc              285 drivers/mailbox/stm32-ipcc.c 		ipcc->wkp = platform_get_irq_byname(pdev, "wakeup");
ipcc              286 drivers/mailbox/stm32-ipcc.c 		if (ipcc->wkp < 0) {
ipcc              287 drivers/mailbox/stm32-ipcc.c 			if (ipcc->wkp != -EPROBE_DEFER)
ipcc              289 drivers/mailbox/stm32-ipcc.c 			ret = ipcc->wkp;
ipcc              294 drivers/mailbox/stm32-ipcc.c 		ret = dev_pm_set_dedicated_wake_irq(dev, ipcc->wkp);
ipcc              302 drivers/mailbox/stm32-ipcc.c 	ipcc->n_chans = readl_relaxed(ipcc->reg_base + IPCC_HWCFGR);
ipcc              303 drivers/mailbox/stm32-ipcc.c 	ipcc->n_chans &= IPCFGR_CHAN_MASK;
ipcc              305 drivers/mailbox/stm32-ipcc.c 	ipcc->controller.dev = dev;
ipcc              306 drivers/mailbox/stm32-ipcc.c 	ipcc->controller.txdone_irq = true;
ipcc              307 drivers/mailbox/stm32-ipcc.c 	ipcc->controller.ops = &stm32_ipcc_ops;
ipcc              308 drivers/mailbox/stm32-ipcc.c 	ipcc->controller.num_chans = ipcc->n_chans;
ipcc              309 drivers/mailbox/stm32-ipcc.c 	ipcc->controller.chans = devm_kcalloc(dev, ipcc->controller.num_chans,
ipcc              310 drivers/mailbox/stm32-ipcc.c 					      sizeof(*ipcc->controller.chans),
ipcc              312 drivers/mailbox/stm32-ipcc.c 	if (!ipcc->controller.chans) {
ipcc              317 drivers/mailbox/stm32-ipcc.c 	for (i = 0; i < ipcc->controller.num_chans; i++)
ipcc              318 drivers/mailbox/stm32-ipcc.c 		ipcc->controller.chans[i].con_priv = (void *)i;
ipcc              320 drivers/mailbox/stm32-ipcc.c 	ret = devm_mbox_controller_register(dev, &ipcc->controller);
ipcc              324 drivers/mailbox/stm32-ipcc.c 	platform_set_drvdata(pdev, ipcc);
ipcc              326 drivers/mailbox/stm32-ipcc.c 	ip_ver = readl_relaxed(ipcc->reg_base + IPCC_VER);
ipcc              331 drivers/mailbox/stm32-ipcc.c 		 ipcc->controller.num_chans, ipcc->proc_id);
ipcc              333 drivers/mailbox/stm32-ipcc.c 	clk_disable_unprepare(ipcc->clk);
ipcc              337 drivers/mailbox/stm32-ipcc.c 	if (ipcc->wkp)
ipcc              342 drivers/mailbox/stm32-ipcc.c 	clk_disable_unprepare(ipcc->clk);
ipcc              348 drivers/mailbox/stm32-ipcc.c 	struct stm32_ipcc *ipcc = platform_get_drvdata(pdev);
ipcc              350 drivers/mailbox/stm32-ipcc.c 	if (ipcc->wkp)
ipcc              361 drivers/mailbox/stm32-ipcc.c 	struct stm32_ipcc *ipcc = dev_get_drvdata(dev);
ipcc              366 drivers/mailbox/stm32-ipcc.c 			irq_set_irq_wake(ipcc->irqs[i], enable);
ipcc              371 drivers/mailbox/stm32-ipcc.c 	struct stm32_ipcc *ipcc = dev_get_drvdata(dev);
ipcc              373 drivers/mailbox/stm32-ipcc.c 	ipcc->xmr = readl_relaxed(ipcc->reg_proc + IPCC_XMR);
ipcc              374 drivers/mailbox/stm32-ipcc.c 	ipcc->xcr = readl_relaxed(ipcc->reg_proc + IPCC_XCR);
ipcc              383 drivers/mailbox/stm32-ipcc.c 	struct stm32_ipcc *ipcc = dev_get_drvdata(dev);
ipcc              387 drivers/mailbox/stm32-ipcc.c 	writel_relaxed(ipcc->xmr, ipcc->reg_proc + IPCC_XMR);
ipcc              388 drivers/mailbox/stm32-ipcc.c 	writel_relaxed(ipcc->xcr, ipcc->reg_proc + IPCC_XCR);