IRAM_HOST_ACCESS_EN   78 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 			IRAM_HOST_ACCESS_EN, 1,
IRAM_HOST_ACCESS_EN   90 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 			IRAM_HOST_ACCESS_EN, 0,
IRAM_HOST_ACCESS_EN  103 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1);
IRAM_HOST_ACCESS_EN  116 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0);
IRAM_HOST_ACCESS_EN  329 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 			IRAM_HOST_ACCESS_EN, 1,
IRAM_HOST_ACCESS_EN  344 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 			IRAM_HOST_ACCESS_EN, 0,
IRAM_HOST_ACCESS_EN  450 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 			IRAM_HOST_ACCESS_EN, 1,
IRAM_HOST_ACCESS_EN  462 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 			IRAM_HOST_ACCESS_EN, 0,
IRAM_HOST_ACCESS_EN  492 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1);
IRAM_HOST_ACCESS_EN  505 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0);
IRAM_HOST_ACCESS_EN   85 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h 			IRAM_HOST_ACCESS_EN, mask_sh), \
IRAM_HOST_ACCESS_EN  111 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h 			IRAM_HOST_ACCESS_EN, mask_sh), \
IRAM_HOST_ACCESS_EN  133 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h 	type IRAM_HOST_ACCESS_EN; \