ioffset 1476 drivers/crypto/ccp/ccp-ops.c unsigned int ioffset, ooffset; ioffset 1577 drivers/crypto/ccp/ccp-ops.c ooffset = ioffset = CCP_SB_BYTES - SHA1_DIGEST_SIZE; ioffset 1579 drivers/crypto/ccp/ccp-ops.c ooffset = ioffset = 0; ioffset 1586 drivers/crypto/ccp/ccp-ops.c ioffset = 0; ioffset 1597 drivers/crypto/ccp/ccp-ops.c ooffset = ioffset = 0; ioffset 1604 drivers/crypto/ccp/ccp-ops.c ioffset = 0; ioffset 1612 drivers/crypto/ccp/ccp-ops.c ooffset = ioffset = 0; ioffset 1646 drivers/crypto/ccp/ccp-ops.c memcpy(ctx.address + ioffset, init, ctx_size); ioffset 10 drivers/gpu/drm/nouveau/include/nvif/cl506f.h __u64 ioffset; ioffset 10 drivers/gpu/drm/nouveau/include/nvif/cl826f.h __u64 ioffset; ioffset 10 drivers/gpu/drm/nouveau/include/nvif/cl906f.h __u64 ioffset; ioffset 10 drivers/gpu/drm/nouveau/include/nvif/cla06f.h __u64 ioffset; ioffset 10 drivers/gpu/drm/nouveau/include/nvif/clc36f.h __u64 ioffset; ioffset 261 drivers/gpu/drm/nouveau/nouveau_chan.c args.volta.ioffset = 0x10000 + chan->push.addr; ioffset 270 drivers/gpu/drm/nouveau/nouveau_chan.c args.kepler.ioffset = 0x10000 + chan->push.addr; ioffset 279 drivers/gpu/drm/nouveau/nouveau_chan.c args.fermi.ioffset = 0x10000 + chan->push.addr; ioffset 285 drivers/gpu/drm/nouveau/nouveau_chan.c args.nv50.ioffset = 0x10000 + chan->push.addr; ioffset 43 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c u64 ioffset, ilength; ioffset 52 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c args->v0.ioffset, args->v0.ilength); ioffset 68 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c ioffset = args->v0.ioffset; ioffset 75 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c nvkm_wo32(chan->ramfc, 0x50, lower_32_bits(ioffset)); ioffset 76 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c nvkm_wo32(chan->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16)); ioffset 223 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c u64 usermem, ioffset, ilength; ioffset 230 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c args->v0.version, args->v0.vmm, args->v0.ioffset, ioffset 263 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c ioffset = args->v0.ioffset; ioffset 278 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c nvkm_wo32(chan->base.inst, 0x48, lower_32_bits(ioffset)); ioffset 279 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c nvkm_wo32(chan->base.inst, 0x4c, upper_32_bits(ioffset) | ioffset 244 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c u64 vmm, u64 ioffset, u64 ilength, u64 *inst, bool priv, ioffset 313 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c nvkm_wo32(chan->base.inst, 0x48, lower_32_bits(ioffset)); ioffset 314 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c nvkm_wo32(chan->base.inst, 0x4c, upper_32_bits(ioffset) | ioffset 344 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c args->v0.version, args->v0.vmm, args->v0.ioffset, ioffset 352 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c args->v0.ioffset, ioffset 125 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c u64 vmm, u64 ioffset, u64 ilength, u64 *inst, bool priv, ioffset 207 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c nvkm_wo32(chan->base.inst, 0x048, lower_32_bits(ioffset)); ioffset 208 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c nvkm_wo32(chan->base.inst, 0x04c, upper_32_bits(ioffset) | ioffset 238 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c args->v0.version, args->v0.vmm, args->v0.ioffset, ioffset 246 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c args->v0.ioffset, ioffset 43 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c u64 ioffset, ilength; ioffset 52 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c args->v0.ioffset, args->v0.ilength); ioffset 68 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c ioffset = args->v0.ioffset; ioffset 75 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c nvkm_wo32(chan->ramfc, 0x50, lower_32_bits(ioffset)); ioffset 76 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c nvkm_wo32(chan->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16)); ioffset 66 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifotu102.c args->v0.version, args->v0.vmm, args->v0.ioffset, ioffset 74 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifotu102.c args->v0.ioffset, ioffset 1245 drivers/infiniband/hw/i40iw/i40iw_puda.c u16 ioffset = 0; ioffset 1256 drivers/infiniband/hw/i40iw/i40iw_puda.c ioffset = (u16)(buf->data - (u8 *)buf->mem.va); ioffset 1299 drivers/infiniband/hw/i40iw/i40iw_puda.c i40iw_ieq_copy_to_txbuf(buf, txbuf, ioffset, buf->hdrlen, ioffset 205 fs/efs/inode.c int ibase, ioffset, dirext, direxts, indext, indexts; ioffset 273 fs/efs/inode.c ioffset = (cur - ibase) % ioffset 293 fs/efs/inode.c extent_copy(&(exts[ioffset]), &ext); ioffset 5451 fs/ext4/extents.c loff_t new_size, ioffset; ioffset 5515 fs/ext4/extents.c ioffset = round_down(offset, PAGE_SIZE); ioffset 5520 fs/ext4/extents.c ret = filemap_write_and_wait_range(inode->i_mapping, ioffset, offset); ioffset 5532 fs/ext4/extents.c truncate_pagecache(inode, ioffset); ioffset 5602 fs/ext4/extents.c loff_t ioffset; ioffset 5668 fs/ext4/extents.c ioffset = round_down(offset, PAGE_SIZE); ioffset 5670 fs/ext4/extents.c ret = filemap_write_and_wait_range(inode->i_mapping, ioffset, ioffset 5674 fs/ext4/extents.c truncate_pagecache(inode, ioffset); ioffset 341 fs/xfs/libxfs/xfs_ialloc.c int ioffset = i << mp->m_sb.sb_inodelog; ioffset 358 fs/xfs/libxfs/xfs_ialloc.c xfs_trans_log_buf(tp, fbuf, ioffset, ioffset 359 fs/xfs/libxfs/xfs_ialloc.c ioffset + isize - 1); ioffset 2527 fs/xfs/xfs_inode.c int ioffset; ioffset 2547 fs/xfs/xfs_inode.c ioffset = inum - xic->first_ino; ioffset 2548 fs/xfs/xfs_inode.c if ((xic->alloc & XFS_INOBT_MASK(ioffset)) == 0) { ioffset 2549 fs/xfs/xfs_inode.c ASSERT(ioffset % igeo->inodes_per_cluster == 0); ioffset 850 net/rxrpc/input.c int nr_acks, offset, ioffset; ioffset 900 net/rxrpc/input.c ioffset = offset + nr_acks + 3; ioffset 901 net/rxrpc/input.c if (skb->len >= ioffset + sizeof(buf.info) && ioffset 902 net/rxrpc/input.c skb_copy_bits(skb, ioffset, &buf.info, sizeof(buf.info)) < 0)