io_base           233 arch/arm/mach-cns3xxx/pcie.c 	u16 io_base   = cnspci->res_io.start  >> 16;
io_base           241 arch/arm/mach-cns3xxx/pcie.c 	cns3xxx_write_config(cnspci, PCI_IO_BASE_UPPER16, 2, io_base);
io_base           311 arch/arm/mach-omap2/timer.c 	timer->io_base = of_iomap(np, 0);
io_base           323 arch/arm/mach-omap2/timer.c 	if (!timer->io_base)
io_base           158 arch/arm/mach-orion5x/ts78xx-setup.c 	void __iomem *io_base = chip->legacy.IO_ADDR_W;
io_base           164 arch/arm/mach-orion5x/ts78xx-setup.c 		writesb(io_base, buf, sz);
io_base           172 arch/arm/mach-orion5x/ts78xx-setup.c 		writesl(io_base, buf32, sz);
io_base           178 arch/arm/mach-orion5x/ts78xx-setup.c 		writesb(io_base, buf, len);
io_base           184 arch/arm/mach-orion5x/ts78xx-setup.c 	void __iomem *io_base = chip->legacy.IO_ADDR_R;
io_base           190 arch/arm/mach-orion5x/ts78xx-setup.c 		readsb(io_base, buf, sz);
io_base           198 arch/arm/mach-orion5x/ts78xx-setup.c 		readsl(io_base, buf32, sz);
io_base           204 arch/arm/mach-orion5x/ts78xx-setup.c 		readsb(io_base, buf, len);
io_base            78 arch/mips/ar7/setup.c 	unsigned long io_base;
io_base            84 arch/mips/ar7/setup.c 	io_base = (unsigned long)ioremap(AR7_REGS_BASE, 0x10000);
io_base            85 arch/mips/ar7/setup.c 	if (!io_base)
io_base            87 arch/mips/ar7/setup.c 	set_io_port_base(io_base);
io_base            40 arch/mips/include/asm/netlogic/psb-bootinfo.h 	uint64_t io_base;
io_base            15 arch/mips/include/asm/txx9/pci.h 			  unsigned long io_base, unsigned long io_size);
io_base           133 arch/mips/pci/ops-tx3927.c 	unsigned long io_base =
io_base           162 arch/mips/pci/ops-tx3927.c 	tx3927_pcicptr->ilbioma = io_base;
io_base           112 arch/mips/txx9/generic/pci.c 			  unsigned long io_base, unsigned long io_size)
io_base           170 arch/mips/txx9/generic/pci.c 	if (io_base) {
io_base           171 arch/mips/txx9/generic/pci.c 		pcic->mem_resource[1].start = io_base;
io_base           172 arch/mips/txx9/generic/pci.c 		pcic->mem_resource[1].end = io_base + io_size - 1;
io_base           189 arch/mips/txx9/generic/pci.c 		io_base = pcic->mem_resource[1].start;
io_base           203 arch/mips/txx9/generic/pci.c 			io_base - (mips_io_port_base - IO_BASE);
io_base           204 arch/mips/txx9/generic/pci.c 		pcic->io_offset = io_base - (mips_io_port_base - IO_BASE);
io_base           292 arch/powerpc/include/asm/fsl_lbc.h extern int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base,
io_base            48 arch/powerpc/platforms/embedded6xx/flipper-pic.c 	void __iomem *io_base = irq_data_get_irq_chip_data(d);
io_base            51 arch/powerpc/platforms/embedded6xx/flipper-pic.c 	clrbits32(io_base + FLIPPER_IMR, mask);
io_base            53 arch/powerpc/platforms/embedded6xx/flipper-pic.c 	out_be32(io_base + FLIPPER_ICR, mask);
io_base            59 arch/powerpc/platforms/embedded6xx/flipper-pic.c 	void __iomem *io_base = irq_data_get_irq_chip_data(d);
io_base            62 arch/powerpc/platforms/embedded6xx/flipper-pic.c 	out_be32(io_base + FLIPPER_ICR, 1 << irq);
io_base            68 arch/powerpc/platforms/embedded6xx/flipper-pic.c 	void __iomem *io_base = irq_data_get_irq_chip_data(d);
io_base            70 arch/powerpc/platforms/embedded6xx/flipper-pic.c 	clrbits32(io_base + FLIPPER_IMR, 1 << irq);
io_base            76 arch/powerpc/platforms/embedded6xx/flipper-pic.c 	void __iomem *io_base = irq_data_get_irq_chip_data(d);
io_base            78 arch/powerpc/platforms/embedded6xx/flipper-pic.c 	setbits32(io_base + FLIPPER_IMR, 1 << irq);
io_base           115 arch/powerpc/platforms/embedded6xx/flipper-pic.c static void __flipper_quiesce(void __iomem *io_base)
io_base           118 arch/powerpc/platforms/embedded6xx/flipper-pic.c 	out_be32(io_base + FLIPPER_IMR, 0x00000000);
io_base           119 arch/powerpc/platforms/embedded6xx/flipper-pic.c 	out_be32(io_base + FLIPPER_ICR, 0xffffffff);
io_base           127 arch/powerpc/platforms/embedded6xx/flipper-pic.c 	void __iomem *io_base;
io_base           145 arch/powerpc/platforms/embedded6xx/flipper-pic.c 	io_base = ioremap(res.start, resource_size(&res));
io_base           147 arch/powerpc/platforms/embedded6xx/flipper-pic.c 	pr_info("controller at 0x%08x mapped to 0x%p\n", res.start, io_base);
io_base           149 arch/powerpc/platforms/embedded6xx/flipper-pic.c 	__flipper_quiesce(io_base);
io_base           152 arch/powerpc/platforms/embedded6xx/flipper-pic.c 				  &flipper_irq_domain_ops, io_base);
io_base           164 arch/powerpc/platforms/embedded6xx/flipper-pic.c 	void __iomem *io_base = flipper_irq_host->host_data;
io_base           168 arch/powerpc/platforms/embedded6xx/flipper-pic.c 	irq_status = in_be32(io_base + FLIPPER_ICR) &
io_base           169 arch/powerpc/platforms/embedded6xx/flipper-pic.c 		     in_be32(io_base + FLIPPER_IMR);
io_base           210 arch/powerpc/platforms/embedded6xx/flipper-pic.c 	void __iomem *io_base = flipper_irq_host->host_data;
io_base           212 arch/powerpc/platforms/embedded6xx/flipper-pic.c 	__flipper_quiesce(io_base);
io_base           220 arch/powerpc/platforms/embedded6xx/flipper-pic.c 	void __iomem *io_base;
io_base           223 arch/powerpc/platforms/embedded6xx/flipper-pic.c 		io_base = flipper_irq_host->host_data;
io_base           224 arch/powerpc/platforms/embedded6xx/flipper-pic.c 		out_8(io_base + FLIPPER_RESET, 0x00);
io_base           233 arch/powerpc/platforms/embedded6xx/flipper-pic.c 	void __iomem *io_base;
io_base           237 arch/powerpc/platforms/embedded6xx/flipper-pic.c 		io_base = flipper_irq_host->host_data;
io_base           238 arch/powerpc/platforms/embedded6xx/flipper-pic.c 		icr = in_be32(io_base + FLIPPER_ICR);
io_base            45 arch/powerpc/platforms/embedded6xx/hlwd-pic.c 	void __iomem *io_base = irq_data_get_irq_chip_data(d);
io_base            48 arch/powerpc/platforms/embedded6xx/hlwd-pic.c 	clrbits32(io_base + HW_BROADWAY_IMR, mask);
io_base            49 arch/powerpc/platforms/embedded6xx/hlwd-pic.c 	out_be32(io_base + HW_BROADWAY_ICR, mask);
io_base            55 arch/powerpc/platforms/embedded6xx/hlwd-pic.c 	void __iomem *io_base = irq_data_get_irq_chip_data(d);
io_base            57 arch/powerpc/platforms/embedded6xx/hlwd-pic.c 	out_be32(io_base + HW_BROADWAY_ICR, 1 << irq);
io_base            63 arch/powerpc/platforms/embedded6xx/hlwd-pic.c 	void __iomem *io_base = irq_data_get_irq_chip_data(d);
io_base            65 arch/powerpc/platforms/embedded6xx/hlwd-pic.c 	clrbits32(io_base + HW_BROADWAY_IMR, 1 << irq);
io_base            71 arch/powerpc/platforms/embedded6xx/hlwd-pic.c 	void __iomem *io_base = irq_data_get_irq_chip_data(d);
io_base            73 arch/powerpc/platforms/embedded6xx/hlwd-pic.c 	setbits32(io_base + HW_BROADWAY_IMR, 1 << irq);
io_base            76 arch/powerpc/platforms/embedded6xx/hlwd-pic.c 	clrbits32(io_base + HW_STARLET_IMR, 1 << irq);
io_base           110 arch/powerpc/platforms/embedded6xx/hlwd-pic.c 	void __iomem *io_base = h->host_data;
io_base           114 arch/powerpc/platforms/embedded6xx/hlwd-pic.c 	irq_status = in_be32(io_base + HW_BROADWAY_ICR) &
io_base           115 arch/powerpc/platforms/embedded6xx/hlwd-pic.c 		     in_be32(io_base + HW_BROADWAY_IMR);
io_base           151 arch/powerpc/platforms/embedded6xx/hlwd-pic.c static void __hlwd_quiesce(void __iomem *io_base)
io_base           154 arch/powerpc/platforms/embedded6xx/hlwd-pic.c 	out_be32(io_base + HW_BROADWAY_IMR, 0);
io_base           155 arch/powerpc/platforms/embedded6xx/hlwd-pic.c 	out_be32(io_base + HW_BROADWAY_ICR, 0xffffffff);
io_base           162 arch/powerpc/platforms/embedded6xx/hlwd-pic.c 	void __iomem *io_base;
io_base           170 arch/powerpc/platforms/embedded6xx/hlwd-pic.c 	io_base = ioremap(res.start, resource_size(&res));
io_base           171 arch/powerpc/platforms/embedded6xx/hlwd-pic.c 	if (!io_base) {
io_base           176 arch/powerpc/platforms/embedded6xx/hlwd-pic.c 	pr_info("controller at 0x%08x mapped to 0x%p\n", res.start, io_base);
io_base           178 arch/powerpc/platforms/embedded6xx/hlwd-pic.c 	__hlwd_quiesce(io_base);
io_base           181 arch/powerpc/platforms/embedded6xx/hlwd-pic.c 					   &hlwd_irq_domain_ops, io_base);
io_base           184 arch/powerpc/platforms/embedded6xx/hlwd-pic.c 		iounmap(io_base);
io_base           231 arch/powerpc/platforms/embedded6xx/hlwd-pic.c 	void __iomem *io_base = hlwd_irq_host->host_data;
io_base           233 arch/powerpc/platforms/embedded6xx/hlwd-pic.c 	__hlwd_quiesce(io_base);
io_base           152 arch/powerpc/sysdev/fsl_lbc.c int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base, u32 mar)
io_base           166 arch/powerpc/sysdev/fsl_lbc.c 		out_8(io_base, 0x0);
io_base           169 arch/powerpc/sysdev/fsl_lbc.c 		out_be16(io_base, 0x0);
io_base           172 arch/powerpc/sysdev/fsl_lbc.c 		out_be32(io_base, 0x0);
io_base           705 drivers/ata/pata_hpt37x.c 	unsigned long io_base = pci_resource_start(pdev, 4);
io_base           714 drivers/ata/pata_hpt37x.c 		io_base = pci_resource_start(pdev_0, 4);
io_base           715 drivers/ata/pata_hpt37x.c 		freq = inl(io_base + 0x90);
io_base           718 drivers/ata/pata_hpt37x.c 		freq = inl(io_base + 0x90);
io_base           191 drivers/ata/pata_pcmcia.c 	unsigned long io_base, ctl_base;
io_base           211 drivers/ata/pata_pcmcia.c 	io_base = pdev->resource[0]->start;
io_base           226 drivers/ata/pata_pcmcia.c 	io_addr = devm_ioport_map(&pdev->dev, io_base, 8);
io_base           263 drivers/ata/pata_pcmcia.c 		ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", io_base, ctl_base);
io_base            34 drivers/char/hw_random/timeriomem-rng.c 	void __iomem		*io_base;
io_base            74 drivers/char/hw_random/timeriomem-rng.c 		*(u32 *)data = readl(priv->io_base);
io_base           163 drivers/char/hw_random/timeriomem-rng.c 	priv->io_base = devm_ioremap_resource(&pdev->dev, res);
io_base           164 drivers/char/hw_random/timeriomem-rng.c 	if (IS_ERR(priv->io_base)) {
io_base           165 drivers/char/hw_random/timeriomem-rng.c 		return PTR_ERR(priv->io_base);
io_base           179 drivers/char/hw_random/timeriomem-rng.c 			priv->io_base, period);
io_base           201 drivers/char/pcmcia/synclink_cs.c 	unsigned int io_base;	/* base I/O address of adapter */
io_base           321 drivers/char/pcmcia/synclink_cs.c #define write_reg(info, reg, val) outb((val),(info)->io_base + (reg))
io_base           322 drivers/char/pcmcia/synclink_cs.c #define read_reg(info, reg) inb((info)->io_base + (reg))
io_base           324 drivers/char/pcmcia/synclink_cs.c #define read_reg16(info, reg) inw((info)->io_base + (reg))
io_base           325 drivers/char/pcmcia/synclink_cs.c #define write_reg16(info, reg, val) outw((val), (info)->io_base + (reg))
io_base           600 drivers/char/pcmcia/synclink_cs.c 	info->io_base = link->resource[0]->start;
io_base          2544 drivers/char/pcmcia/synclink_cs.c 		      info->device_name, info->io_base, info->irq_level);
io_base          2711 drivers/char/pcmcia/synclink_cs.c 		info->device_name, info->io_base, info->irq_level);
io_base          3783 drivers/char/pcmcia/synclink_cs.c 			__FILE__, __LINE__, info->device_name, (unsigned short)(info->io_base));
io_base          4265 drivers/char/pcmcia/synclink_cs.c 	dev->base_addr = info->io_base;
io_base           816 drivers/clocksource/timer-ti-dm.c 	timer->io_base = devm_ioremap_resource(dev, mem);
io_base           817 drivers/clocksource/timer-ti-dm.c 	if (IS_ERR(timer->io_base))
io_base           818 drivers/clocksource/timer-ti-dm.c 		return PTR_ERR(timer->io_base);
io_base           184 drivers/crypto/atmel-aes.c 	void __iomem		*io_base;
io_base           346 drivers/crypto/atmel-aes.c 	u32 value = readl_relaxed(dd->io_base + offset);
io_base           372 drivers/crypto/atmel-aes.c 	writel_relaxed(value, dd->io_base + offset);
io_base          2689 drivers/crypto/atmel-aes.c 	aes_dd->io_base = devm_ioremap_resource(&pdev->dev, aes_res);
io_base          2690 drivers/crypto/atmel-aes.c 	if (IS_ERR(aes_dd->io_base)) {
io_base          2692 drivers/crypto/atmel-aes.c 		err = PTR_ERR(aes_dd->io_base);
io_base           134 drivers/crypto/atmel-sha.c 	void __iomem		*io_base;
io_base           254 drivers/crypto/atmel-sha.c 	u32 value = readl_relaxed(dd->io_base + offset);
io_base           280 drivers/crypto/atmel-sha.c 	writel_relaxed(value, dd->io_base + offset);
io_base          2796 drivers/crypto/atmel-sha.c 	sha_dd->io_base = devm_ioremap_resource(&pdev->dev, sha_res);
io_base          2797 drivers/crypto/atmel-sha.c 	if (IS_ERR(sha_dd->io_base)) {
io_base          2799 drivers/crypto/atmel-sha.c 		err = PTR_ERR(sha_dd->io_base);
io_base            93 drivers/crypto/atmel-tdes.c 	void __iomem		*io_base;
io_base           180 drivers/crypto/atmel-tdes.c 	return readl_relaxed(dd->io_base + offset);
io_base           186 drivers/crypto/atmel-tdes.c 	writel_relaxed(value, dd->io_base + offset);
io_base          1289 drivers/crypto/atmel-tdes.c 	tdes_dd->io_base = devm_ioremap_resource(&pdev->dev, tdes_res);
io_base          1290 drivers/crypto/atmel-tdes.c 	if (IS_ERR(tdes_dd->io_base)) {
io_base          1292 drivers/crypto/atmel-tdes.c 		err = PTR_ERR(tdes_dd->io_base);
io_base           323 drivers/crypto/hisilicon/qm.c 	return readl_relaxed_poll_timeout(qm->io_base + QM_MB_CMD_SEND_BASE,
io_base           331 drivers/crypto/hisilicon/qm.c 	void __iomem *fun_base = qm->io_base + QM_MB_CMD_SEND_BASE;
io_base           391 drivers/crypto/hisilicon/qm.c 	writeq(doorbell, qm->io_base + QM_DOORBELL_BASE_V1);
io_base           410 drivers/crypto/hisilicon/qm.c 	writeq(doorbell, qm->io_base + dbase);
io_base           425 drivers/crypto/hisilicon/qm.c 	writel(0x1, qm->io_base + QM_MEM_START_INIT);
io_base           426 drivers/crypto/hisilicon/qm.c 	return readl_relaxed_poll_timeout(qm->io_base + QM_MEM_INIT_DONE, val,
io_base           526 drivers/crypto/hisilicon/qm.c 	if (readl(qm->io_base + QM_VF_EQ_INT_SOURCE))
io_base           541 drivers/crypto/hisilicon/qm.c 	if (!readl(qm->io_base + QM_VF_AEQ_INT_SOURCE))
io_base           576 drivers/crypto/hisilicon/qm.c 	tmp = readl(qm->io_base + QM_ABNORMAL_INT_STATUS);
io_base           588 drivers/crypto/hisilicon/qm.c 	writel(error_status, qm->io_base + QM_ABNORMAL_INT_SOURCE);
io_base           696 drivers/crypto/hisilicon/qm.c 	writel(lower_32_bits(tmp), qm->io_base + QM_VFT_CFG_DATA_L);
io_base           697 drivers/crypto/hisilicon/qm.c 	writel(upper_32_bits(tmp), qm->io_base + QM_VFT_CFG_DATA_H);
io_base           706 drivers/crypto/hisilicon/qm.c 	ret = readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,
io_base           711 drivers/crypto/hisilicon/qm.c 	writel(0x0, qm->io_base + QM_VFT_CFG_OP_WR);
io_base           712 drivers/crypto/hisilicon/qm.c 	writel(type, qm->io_base + QM_VFT_CFG_TYPE);
io_base           713 drivers/crypto/hisilicon/qm.c 	writel(fun_num, qm->io_base + QM_VFT_CFG);
io_base           717 drivers/crypto/hisilicon/qm.c 	writel(0x0, qm->io_base + QM_VFT_CFG_RDY);
io_base           718 drivers/crypto/hisilicon/qm.c 	writel(0x1, qm->io_base + QM_VFT_CFG_OP_ENABLE);
io_base           720 drivers/crypto/hisilicon/qm.c 	return readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,
io_base           748 drivers/crypto/hisilicon/qm.c 	sqc_vft = readl(qm->io_base + QM_MB_CMD_DATA_ADDR_L) |
io_base           749 drivers/crypto/hisilicon/qm.c 		  ((u64)readl(qm->io_base + QM_MB_CMD_DATA_ADDR_H) << 32);
io_base           768 drivers/crypto/hisilicon/qm.c 	return readl(qm->io_base + QM_DFX_SQE_CNT_VF_SQN) >> QM_DFX_QN_SHIFT;
io_base           780 drivers/crypto/hisilicon/qm.c 	      (readl(qm->io_base + QM_DFX_SQE_CNT_VF_SQN) & CURRENT_FUN_MASK);
io_base           781 drivers/crypto/hisilicon/qm.c 	writel(tmp, qm->io_base + QM_DFX_SQE_CNT_VF_SQN);
io_base           784 drivers/crypto/hisilicon/qm.c 	      (readl(qm->io_base + QM_DFX_CQE_CNT_VF_CQN) & CURRENT_FUN_MASK);
io_base           785 drivers/crypto/hisilicon/qm.c 	writel(tmp, qm->io_base + QM_DFX_CQE_CNT_VF_CQN);
io_base           794 drivers/crypto/hisilicon/qm.c 	return readl(qm->io_base + QM_DFX_CNT_CLR_CE);
io_base           805 drivers/crypto/hisilicon/qm.c 	writel(rd_clr_ctrl, qm->io_base + QM_DFX_CNT_CLR_CE);
io_base           944 drivers/crypto/hisilicon/qm.c 		val = readl(qm->io_base + regs->reg_offset);
io_base           987 drivers/crypto/hisilicon/qm.c 	writel(QM_ABNORMAL_INT_MASK_VALUE, qm->io_base + QM_ABNORMAL_INT_MASK);
io_base          1000 drivers/crypto/hisilicon/qm.c 	writel(ce, qm->io_base + QM_RAS_CE_ENABLE);
io_base          1001 drivers/crypto/hisilicon/qm.c 	writel(QM_RAS_CE_TIMES_PER_IRQ, qm->io_base + QM_RAS_CE_THRESHOLD);
io_base          1002 drivers/crypto/hisilicon/qm.c 	writel(nfe, qm->io_base + QM_RAS_NFE_ENABLE);
io_base          1003 drivers/crypto/hisilicon/qm.c 	writel(fe, qm->io_base + QM_RAS_FE_ENABLE);
io_base          1006 drivers/crypto/hisilicon/qm.c 	writel(msi, qm->io_base + QM_RAS_MSI_INT_SEL);
io_base          1008 drivers/crypto/hisilicon/qm.c 	irq_unmask &= readl(qm->io_base + QM_ABNORMAL_INT_MASK);
io_base          1009 drivers/crypto/hisilicon/qm.c 	writel(irq_unmask, qm->io_base + QM_ABNORMAL_INT_MASK);
io_base          1024 drivers/crypto/hisilicon/qm.c 				reg_val = readl(qm->io_base +
io_base          1034 drivers/crypto/hisilicon/qm.c 				reg_val = readl(qm->io_base +
io_base          1057 drivers/crypto/hisilicon/qm.c 	tmp = readl(qm->io_base + QM_ABNORMAL_INT_STATUS);
io_base          1064 drivers/crypto/hisilicon/qm.c 		writel(error_status, qm->io_base + QM_ABNORMAL_INT_SOURCE);
io_base          1387 drivers/crypto/hisilicon/qm.c 		writel(0x1, qm->io_base + QM_CACHE_WB_START);
io_base          1388 drivers/crypto/hisilicon/qm.c 		if (readl_relaxed_poll_timeout(qm->io_base + QM_CACHE_WB_DONE,
io_base          1430 drivers/crypto/hisilicon/qm.c 	qm->io_base = ioremap(pci_resource_start(pdev, PCI_BAR_2),
io_base          1432 drivers/crypto/hisilicon/qm.c 	if (!qm->io_base) {
io_base          1468 drivers/crypto/hisilicon/qm.c 	iounmap(qm->io_base);
io_base          1498 drivers/crypto/hisilicon/qm.c 	iounmap(qm->io_base);
io_base          1675 drivers/crypto/hisilicon/qm.c 	writel(0x0, qm->io_base + QM_VF_EQ_INT_MASK);
io_base          1676 drivers/crypto/hisilicon/qm.c 	writel(0x0, qm->io_base + QM_VF_AEQ_INT_MASK);
io_base          1750 drivers/crypto/hisilicon/qm.c 	writel(0x1, qm->io_base + QM_VF_EQ_INT_MASK);
io_base          1751 drivers/crypto/hisilicon/qm.c 	writel(0x1, qm->io_base + QM_VF_AEQ_INT_MASK);
io_base          1824 drivers/crypto/hisilicon/qm.c 	writel(0x0, qm->io_base + QM_DFX_SQE_CNT_VF_SQN);
io_base          1825 drivers/crypto/hisilicon/qm.c 	writel(0x0, qm->io_base + QM_DFX_CQE_CNT_VF_CQN);
io_base          1831 drivers/crypto/hisilicon/qm.c 	writel(0x1, qm->io_base + QM_DFX_CNT_CLR_CE);
io_base          1835 drivers/crypto/hisilicon/qm.c 		readl(qm->io_base + regs->reg_offset);
io_base          1839 drivers/crypto/hisilicon/qm.c 	writel(0x0, qm->io_base + QM_DFX_CNT_CLR_CE);
io_base           131 drivers/crypto/hisilicon/qm.h 	void __iomem *io_base;
io_base           293 drivers/crypto/hisilicon/zip/zip_main.c 	void __iomem *base = hisi_zip->qm.io_base;
io_base           337 drivers/crypto/hisilicon/zip/zip_main.c 		writel(HZIP_CORE_INT_DISABLE, qm->io_base + HZIP_CORE_INT_MASK);
io_base           345 drivers/crypto/hisilicon/zip/zip_main.c 		writel(HZIP_CORE_INT_DISABLE, hisi_zip->qm.io_base +
io_base           348 drivers/crypto/hisilicon/zip/zip_main.c 		writel(0, hisi_zip->qm.io_base + HZIP_CORE_INT_MASK);
io_base           352 drivers/crypto/hisilicon/zip/zip_main.c 		       hisi_zip->qm.io_base + HZIP_CORE_INT_MASK);
io_base           367 drivers/crypto/hisilicon/zip/zip_main.c 	return readl(qm->io_base + QM_DFX_MB_CNT_VF);
io_base           392 drivers/crypto/hisilicon/zip/zip_main.c 	writel(val, qm->io_base + QM_DFX_MB_CNT_VF);
io_base           393 drivers/crypto/hisilicon/zip/zip_main.c 	writel(val, qm->io_base + QM_DFX_DB_CNT_VF);
io_base           396 drivers/crypto/hisilicon/zip/zip_main.c 	      (readl(qm->io_base + QM_DFX_SQE_CNT_VF_SQN) & CURRENT_Q_MASK);
io_base           397 drivers/crypto/hisilicon/zip/zip_main.c 	writel(tmp, qm->io_base + QM_DFX_SQE_CNT_VF_SQN);
io_base           400 drivers/crypto/hisilicon/zip/zip_main.c 	      (readl(qm->io_base + QM_DFX_CQE_CNT_VF_CQN) & CURRENT_Q_MASK);
io_base           401 drivers/crypto/hisilicon/zip/zip_main.c 	writel(tmp, qm->io_base + QM_DFX_CQE_CNT_VF_CQN);
io_base           410 drivers/crypto/hisilicon/zip/zip_main.c 	return readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) &
io_base           422 drivers/crypto/hisilicon/zip/zip_main.c 	tmp = (readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) &
io_base           424 drivers/crypto/hisilicon/zip/zip_main.c 	writel(tmp, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE);
io_base           534 drivers/crypto/hisilicon/zip/zip_main.c 		regset->base = qm->io_base + core_offsets[i];
io_base           598 drivers/crypto/hisilicon/zip/zip_main.c 	writel(0x0, qm->io_base + QM_DFX_MB_CNT_VF);
io_base           599 drivers/crypto/hisilicon/zip/zip_main.c 	writel(0x0, qm->io_base + QM_DFX_DB_CNT_VF);
io_base           600 drivers/crypto/hisilicon/zip/zip_main.c 	writel(0x0, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE);
io_base           873 drivers/crypto/hisilicon/zip/zip_main.c 				err_val = readl(hisi_zip->qm.io_base +
io_base           891 drivers/crypto/hisilicon/zip/zip_main.c 	err_sts = readl(hisi_zip->qm.io_base + HZIP_CORE_INT_STATUS);
io_base           896 drivers/crypto/hisilicon/zip/zip_main.c 		writel(err_sts, hisi_zip->qm.io_base + HZIP_CORE_INT_SOURCE);
io_base           120 drivers/crypto/img-hash.c 	void __iomem		*io_base;
io_base           149 drivers/crypto/img-hash.c 	return readl_relaxed(hdev->io_base + offset);
io_base           155 drivers/crypto/img-hash.c 	writel_relaxed(value, hdev->io_base + offset);
io_base           961 drivers/crypto/img-hash.c 	hdev->io_base = devm_platform_ioremap_resource(pdev, 0);
io_base           962 drivers/crypto/img-hash.c 	if (IS_ERR(hdev->io_base)) {
io_base           963 drivers/crypto/img-hash.c 		err = PTR_ERR(hdev->io_base);
io_base            52 drivers/crypto/omap-aes.c 	_read_ret = __raw_readl(dd->io_base + offset);		\
io_base            60 drivers/crypto/omap-aes.c 	return __raw_readl(dd->io_base + offset);
io_base            69 drivers/crypto/omap-aes.c 		__raw_writel(value, dd->io_base + offset);		\
io_base            75 drivers/crypto/omap-aes.c 	__raw_writel(value, dd->io_base + offset);
io_base          1145 drivers/crypto/omap-aes.c 	dd->io_base = devm_ioremap_resource(dev, &res);
io_base          1146 drivers/crypto/omap-aes.c 	if (IS_ERR(dd->io_base)) {
io_base          1147 drivers/crypto/omap-aes.c 		err = PTR_ERR(dd->io_base);
io_base           155 drivers/crypto/omap-aes.h 	void __iomem		*io_base;
io_base           134 drivers/crypto/omap-des.c 	void __iomem		*io_base;
io_base           177 drivers/crypto/omap-des.c 	 _read_ret = __raw_readl(dd->io_base + offset);          \
io_base           185 drivers/crypto/omap-des.c 	return __raw_readl(dd->io_base + offset);
io_base           194 drivers/crypto/omap-des.c 		__raw_writel(value, dd->io_base + offset);              \
io_base           200 drivers/crypto/omap-des.c 	__raw_writel(value, dd->io_base + offset);
io_base          1003 drivers/crypto/omap-des.c 	dd->io_base = devm_ioremap_resource(dev, res);
io_base          1004 drivers/crypto/omap-des.c 	if (IS_ERR(dd->io_base)) {
io_base          1005 drivers/crypto/omap-des.c 		err = PTR_ERR(dd->io_base);
io_base           219 drivers/crypto/omap-sham.c 	void __iomem		*io_base;
io_base           249 drivers/crypto/omap-sham.c 	return __raw_readl(dd->io_base + offset);
io_base           255 drivers/crypto/omap-sham.c 	__raw_writel(value, dd->io_base + offset);
io_base          2110 drivers/crypto/omap-sham.c 	dd->io_base = devm_ioremap_resource(dev, &res);
io_base          2111 drivers/crypto/omap-sham.c 	if (IS_ERR(dd->io_base)) {
io_base          2112 drivers/crypto/omap-sham.c 		err = PTR_ERR(dd->io_base);
io_base           165 drivers/crypto/stm32/stm32-hash.c 	void __iomem		*io_base;
io_base           196 drivers/crypto/stm32/stm32-hash.c 	return readl_relaxed(hdev->io_base + offset);
io_base           202 drivers/crypto/stm32/stm32-hash.c 	writel_relaxed(value, hdev->io_base + offset);
io_base           209 drivers/crypto/stm32/stm32-hash.c 	return readl_relaxed_poll_timeout(hdev->io_base + HASH_SR, status,
io_base           614 drivers/crypto/stm32/stm32-hash.c 			writesl(hdev->io_base + HASH_DIN, buffer,
io_base          1442 drivers/crypto/stm32/stm32-hash.c 	hdev->io_base = devm_ioremap_resource(dev, res);
io_base          1443 drivers/crypto/stm32/stm32-hash.c 	if (IS_ERR(hdev->io_base))
io_base          1444 drivers/crypto/stm32/stm32-hash.c 		return PTR_ERR(hdev->io_base);
io_base            31 drivers/fpga/ts73xx-fpga.c 	void __iomem	*io_base;
io_base            47 drivers/fpga/ts73xx-fpga.c 	writeb(0, priv->io_base + TS73XX_FPGA_CONFIG_REG);
io_base            49 drivers/fpga/ts73xx-fpga.c 	writeb(TS73XX_FPGA_RESET, priv->io_base + TS73XX_FPGA_CONFIG_REG);
io_base            64 drivers/fpga/ts73xx-fpga.c 		ret = readb_poll_timeout(priv->io_base + TS73XX_FPGA_CONFIG_REG,
io_base            70 drivers/fpga/ts73xx-fpga.c 		writeb(buf[i], priv->io_base + TS73XX_FPGA_DATA_REG);
io_base            84 drivers/fpga/ts73xx-fpga.c 	reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG);
io_base            86 drivers/fpga/ts73xx-fpga.c 	writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG);
io_base            89 drivers/fpga/ts73xx-fpga.c 	reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG);
io_base            91 drivers/fpga/ts73xx-fpga.c 	writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG);
io_base            93 drivers/fpga/ts73xx-fpga.c 	reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG);
io_base           121 drivers/fpga/ts73xx-fpga.c 	priv->io_base = devm_ioremap_resource(kdev, res);
io_base           122 drivers/fpga/ts73xx-fpga.c 	if (IS_ERR(priv->io_base)) {
io_base           124 drivers/fpga/ts73xx-fpga.c 		return PTR_ERR(priv->io_base);
io_base            22 drivers/fpga/xilinx-pr-decoupler.c 	void __iomem *io_base;
io_base            29 drivers/fpga/xilinx-pr-decoupler.c 	writel(val, d->io_base + offset);
io_base            35 drivers/fpga/xilinx-pr-decoupler.c 	return readl(d->io_base + offset);
io_base            67 drivers/fpga/xilinx-pr-decoupler.c 	status = readl(priv->io_base);
io_base            98 drivers/fpga/xilinx-pr-decoupler.c 	priv->io_base = devm_ioremap_resource(&pdev->dev, res);
io_base            99 drivers/fpga/xilinx-pr-decoupler.c 	if (IS_ERR(priv->io_base))
io_base           100 drivers/fpga/xilinx-pr-decoupler.c 		return PTR_ERR(priv->io_base);
io_base           126 drivers/fpga/zynq-fpga.c 	void __iomem *io_base;
io_base           140 drivers/fpga/zynq-fpga.c 	writel(val, priv->io_base + offset);
io_base           146 drivers/fpga/zynq-fpga.c 	return readl(priv->io_base + offset);
io_base           150 drivers/fpga/zynq-fpga.c 	readl_poll_timeout(priv->io_base + addr, val, cond, sleep_us, \
io_base           567 drivers/fpga/zynq-fpga.c 	priv->io_base = devm_ioremap_resource(dev, res);
io_base           568 drivers/fpga/zynq-fpga.c 	if (IS_ERR(priv->io_base))
io_base           569 drivers/fpga/zynq-fpga.c 		return PTR_ERR(priv->io_base);
io_base            64 drivers/gpio/gpio-it87.c 	u16 io_base;
io_base           194 drivers/gpio/gpio-it87.c 	reg = (gpio_num / 8) + it87_gpio->io_base;
io_base           232 drivers/gpio/gpio-it87.c 	reg = (gpio_num / 8) + it87_gpio->io_base;
io_base           351 drivers/gpio/gpio-it87.c 	it87_gpio->io_base = superio_inw(gpio_ba_reg);
io_base           357 drivers/gpio/gpio-it87.c 		it87_gpio->io_base);
io_base           359 drivers/gpio/gpio-it87.c 	if (!request_region(it87_gpio->io_base, it87_gpio->io_size,
io_base           401 drivers/gpio/gpio-it87.c 	release_region(it87_gpio->io_base, it87_gpio->io_size);
io_base           410 drivers/gpio/gpio-it87.c 	release_region(it87_gpio->io_base, it87_gpio->io_size);
io_base            38 drivers/gpio/gpio-tqmx86.c 	void __iomem		*io_base;
io_base            46 drivers/gpio/gpio-tqmx86.c 	return ioread8(gd->io_base + reg);
io_base            52 drivers/gpio/gpio-tqmx86.c 	iowrite8(val, gd->io_base + reg);
io_base           234 drivers/gpio/gpio-tqmx86.c 	void __iomem *io_base;
io_base           248 drivers/gpio/gpio-tqmx86.c 	io_base = devm_ioport_map(&pdev->dev, res->start, resource_size(res));
io_base           249 drivers/gpio/gpio-tqmx86.c 	if (!io_base)
io_base           257 drivers/gpio/gpio-tqmx86.c 	gpio->io_base = io_base;
io_base            90 drivers/gpu/drm/meson/meson_crtc.c 	       priv->io_base + _REG(VPP_PREBLEND_VD1_V_START_END));
io_base            95 drivers/gpu/drm/meson/meson_crtc.c 	       priv->io_base + _REG(VPP_POSTBLEND_H_SIZE));
io_base            99 drivers/gpu/drm/meson/meson_crtc.c 			priv->io_base + _REG(VPP_OSD1_BLD_H_SCOPE));
io_base           102 drivers/gpu/drm/meson/meson_crtc.c 			priv->io_base + _REG(VPP_OSD1_BLD_V_SCOPE));
io_base           105 drivers/gpu/drm/meson/meson_crtc.c 			priv->io_base + _REG(VPP_OUT_H_V_SIZE));
io_base           126 drivers/gpu/drm/meson/meson_crtc.c 	       priv->io_base + _REG(VPP_POSTBLEND_H_SIZE));
io_base           130 drivers/gpu/drm/meson/meson_crtc.c 			priv->io_base + _REG(VPP_PREBLEND_VD1_V_START_END));
io_base           133 drivers/gpu/drm/meson/meson_crtc.c 			    priv->io_base + _REG(VPP_MISC));
io_base           182 drivers/gpu/drm/meson/meson_crtc.c 			    priv->io_base + _REG(VPP_MISC));
io_base           236 drivers/gpu/drm/meson/meson_crtc.c 			    priv->io_base + _REG(VPP_MISC));
io_base           242 drivers/gpu/drm/meson/meson_crtc.c 		       priv->io_base +
io_base           245 drivers/gpu/drm/meson/meson_crtc.c 		       priv->io_base +
io_base           248 drivers/gpu/drm/meson/meson_crtc.c 		       priv->io_base +
io_base           251 drivers/gpu/drm/meson/meson_crtc.c 		       priv->io_base +
io_base           254 drivers/gpu/drm/meson/meson_crtc.c 			    priv->io_base + _REG(OSD1_BLEND_SRC_CTRL));
io_base           263 drivers/gpu/drm/meson/meson_crtc.c 			    priv->io_base + _REG(VPP_MISC));
io_base           272 drivers/gpu/drm/meson/meson_crtc.c 		       priv->io_base + _REG(VD1_BLEND_SRC_CTRL));
io_base           283 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + _REG(VIU_OSD1_CTRL_STAT));
io_base           285 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W0));
io_base           287 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W1));
io_base           289 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W2));
io_base           291 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W3));
io_base           293 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W4));
io_base           295 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + _REG(VPP_OSD_SC_CTRL0));
io_base           297 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + _REG(VPP_OSD_SCI_WH_M1));
io_base           299 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + _REG(VPP_OSD_SCO_H_START_END));
io_base           301 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + _REG(VPP_OSD_SCO_V_START_END));
io_base           303 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + _REG(VPP_OSD_VSC_INI_PHASE));
io_base           305 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + _REG(VPP_OSD_VSC_PHASE_STEP));
io_base           307 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + _REG(VPP_OSD_HSC_INI_PHASE));
io_base           309 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + _REG(VPP_OSD_HSC_PHASE_STEP));
io_base           311 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + _REG(VPP_OSD_HSC_CTRL0));
io_base           313 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + _REG(VPP_OSD_VSC_CTRL0));
io_base           363 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + meson_crtc->viu_offset +
io_base           366 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + meson_crtc->viu_offset +
io_base           369 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + meson_crtc->viu_offset +
io_base           372 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + meson_crtc->viu_offset +
io_base           375 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + meson_crtc->viu_offset +
io_base           378 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + meson_crtc->viu_offset +
io_base           381 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + meson_crtc->viu_offset +
io_base           384 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + meson_crtc->viu_offset +
io_base           387 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + meson_crtc->viu_offset +
io_base           390 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + meson_crtc->viu_offset +
io_base           393 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + meson_crtc->viu_offset +
io_base           396 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + meson_crtc->viu_offset +
io_base           399 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + meson_crtc->viu_offset +
io_base           402 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + meson_crtc->viu_offset +
io_base           405 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + meson_crtc->viu_offset +
io_base           408 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + meson_crtc->viu_offset +
io_base           411 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + meson_crtc->viu_offset +
io_base           414 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + meson_crtc->viu_offset +
io_base           417 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + meson_crtc->viu_offset +
io_base           420 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + meson_crtc->viu_offset +
io_base           423 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + meson_crtc->viu_offset +
io_base           426 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + meson_crtc->viu_offset +
io_base           429 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + meson_crtc->viu_offset +
io_base           432 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + meson_crtc->viu_offset +
io_base           435 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + meson_crtc->viu_offset +
io_base           438 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + meson_crtc->viu_offset +
io_base           441 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + meson_crtc->viu_offset +
io_base           444 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + meson_crtc->viu_offset +
io_base           447 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + meson_crtc->viu_offset +
io_base           450 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + meson_crtc->viu_offset +
io_base           453 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + meson_crtc->viu_offset +
io_base           456 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + meson_crtc->viu_offset +
io_base           459 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + meson_crtc->viu_offset +
io_base           462 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + meson_crtc->viu_offset +
io_base           465 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + meson_crtc->viu_offset +
io_base           468 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + meson_crtc->viu_offset +
io_base           471 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + meson_crtc->viu_offset +
io_base           473 drivers/gpu/drm/meson/meson_crtc.c 		writel_relaxed(0, priv->io_base + meson_crtc->viu_offset +
io_base           475 drivers/gpu/drm/meson/meson_crtc.c 		writel_relaxed(0, priv->io_base + meson_crtc->viu_offset +
io_base           477 drivers/gpu/drm/meson/meson_crtc.c 		writel_relaxed(0, priv->io_base + meson_crtc->viu_offset +
io_base           479 drivers/gpu/drm/meson/meson_crtc.c 		writel_relaxed(0, priv->io_base + meson_crtc->viu_offset +
io_base           482 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + meson_crtc->viu_offset +
io_base           485 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + meson_crtc->viu_offset +
io_base           488 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + meson_crtc->viu_offset +
io_base           496 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + _REG(VPP_SC_MISC));
io_base           498 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + _REG(VPP_PIC_IN_HEIGHT));
io_base           500 drivers/gpu/drm/meson/meson_crtc.c 			priv->io_base + _REG(VPP_POSTBLEND_VD1_H_START_END));
io_base           502 drivers/gpu/drm/meson/meson_crtc.c 			priv->io_base + _REG(VPP_BLEND_VD2_H_START_END));
io_base           504 drivers/gpu/drm/meson/meson_crtc.c 			priv->io_base + _REG(VPP_POSTBLEND_VD1_V_START_END));
io_base           506 drivers/gpu/drm/meson/meson_crtc.c 			priv->io_base + _REG(VPP_BLEND_VD2_V_START_END));
io_base           508 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + _REG(VPP_HSC_REGION12_STARTP));
io_base           510 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + _REG(VPP_HSC_REGION34_STARTP));
io_base           512 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + _REG(VPP_HSC_REGION4_ENDP));
io_base           514 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + _REG(VPP_HSC_START_PHASE_STEP));
io_base           516 drivers/gpu/drm/meson/meson_crtc.c 			priv->io_base + _REG(VPP_HSC_REGION1_PHASE_SLOPE));
io_base           518 drivers/gpu/drm/meson/meson_crtc.c 			priv->io_base + _REG(VPP_HSC_REGION3_PHASE_SLOPE));
io_base           520 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + _REG(VPP_LINE_IN_LENGTH));
io_base           522 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + _REG(VPP_PREBLEND_H_SIZE));
io_base           524 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + _REG(VPP_VSC_REGION12_STARTP));
io_base           526 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + _REG(VPP_VSC_REGION34_STARTP));
io_base           528 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + _REG(VPP_VSC_REGION4_ENDP));
io_base           530 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + _REG(VPP_VSC_START_PHASE_STEP));
io_base           532 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + _REG(VPP_VSC_INI_PHASE));
io_base           534 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + _REG(VPP_VSC_PHASE_CTRL));
io_base           536 drivers/gpu/drm/meson/meson_crtc.c 				priv->io_base + _REG(VPP_HSC_PHASE_CTRL));
io_base           537 drivers/gpu/drm/meson/meson_crtc.c 		writel_relaxed(0x42, priv->io_base + _REG(VPP_SCALE_COEF_IDX));
io_base            69 drivers/gpu/drm/meson/meson_drv.c 	(void)readl_relaxed(priv->io_base + _REG(VENC_INTFLAG));
io_base           151 drivers/gpu/drm/meson/meson_drv.c 	writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L1C1));
io_base           155 drivers/gpu/drm/meson/meson_drv.c 	writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L1C2));
io_base           160 drivers/gpu/drm/meson/meson_drv.c 	writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L2C1));
io_base           164 drivers/gpu/drm/meson/meson_drv.c 	writel_relaxed(value, priv->io_base + _REG(VPU_WRARB_MODE_L2C1));
io_base           221 drivers/gpu/drm/meson/meson_drv.c 	priv->io_base = regs;
io_base            30 drivers/gpu/drm/meson/meson_drv.h 	void __iomem *io_base;
io_base           415 drivers/gpu/drm/meson/meson_dw_hdmi.c 		readl_relaxed(priv->io_base + _REG(VPU_HDMI_SETTING));
io_base           489 drivers/gpu/drm/meson/meson_dw_hdmi.c 		writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN));
io_base           491 drivers/gpu/drm/meson/meson_dw_hdmi.c 		writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN));
io_base           495 drivers/gpu/drm/meson/meson_dw_hdmi.c 			    priv->io_base + _REG(VPU_HDMI_SETTING));
io_base           497 drivers/gpu/drm/meson/meson_dw_hdmi.c 			    priv->io_base + _REG(VPU_HDMI_SETTING));
io_base           501 drivers/gpu/drm/meson/meson_dw_hdmi.c 		writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN));
io_base           503 drivers/gpu/drm/meson/meson_dw_hdmi.c 		writel_relaxed(1, priv->io_base + _REG(ENCP_VIDEO_EN));
io_base           507 drivers/gpu/drm/meson/meson_dw_hdmi.c 			    priv->io_base + _REG(VPU_HDMI_SETTING));
io_base           512 drivers/gpu/drm/meson/meson_dw_hdmi.c 				    priv->io_base + _REG(VPU_HDMI_SETTING));
io_base           515 drivers/gpu/drm/meson/meson_dw_hdmi.c 				    priv->io_base + _REG(VPU_HDMI_SETTING));
io_base           690 drivers/gpu/drm/meson/meson_dw_hdmi.c 			    priv->io_base + _REG(VPU_HDMI_SETTING));
io_base           692 drivers/gpu/drm/meson/meson_dw_hdmi.c 	writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN));
io_base           693 drivers/gpu/drm/meson/meson_dw_hdmi.c 	writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN));
io_base           704 drivers/gpu/drm/meson/meson_dw_hdmi.c 		writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN));
io_base           706 drivers/gpu/drm/meson/meson_dw_hdmi.c 		writel_relaxed(1, priv->io_base + _REG(ENCP_VIDEO_EN));
io_base           726 drivers/gpu/drm/meson/meson_dw_hdmi.c 	writel_relaxed(0, priv->io_base + _REG(VPU_HDMI_FMT_CTRL));
io_base           517 drivers/gpu/drm/meson/meson_overlay.c 		writel_relaxed(0, priv->io_base + _REG(VD1_BLEND_SRC_CTRL));
io_base           518 drivers/gpu/drm/meson/meson_overlay.c 		writel_relaxed(0, priv->io_base + _REG(VD2_BLEND_SRC_CTRL));
io_base           519 drivers/gpu/drm/meson/meson_overlay.c 		writel_relaxed(0, priv->io_base + _REG(VD1_IF0_GEN_REG + 0x17b0));
io_base           520 drivers/gpu/drm/meson/meson_overlay.c 		writel_relaxed(0, priv->io_base + _REG(VD2_IF0_GEN_REG + 0x17b0));
io_base           523 drivers/gpu/drm/meson/meson_overlay.c 				    priv->io_base + _REG(VPP_MISC));
io_base           148 drivers/gpu/drm/meson/meson_plane.c 				    priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
io_base           155 drivers/gpu/drm/meson/meson_plane.c 				    priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
io_base           162 drivers/gpu/drm/meson/meson_plane.c 				    priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
io_base           169 drivers/gpu/drm/meson/meson_plane.c 				    priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
io_base           332 drivers/gpu/drm/meson/meson_plane.c 				    priv->io_base + _REG(OSD1_BLEND_SRC_CTRL));
io_base           335 drivers/gpu/drm/meson/meson_plane.c 				    priv->io_base + _REG(VPP_MISC));
io_base          1042 drivers/gpu/drm/meson/meson_venc.c 			priv->io_base + _REG(VENC_VDAC_SETTING));
io_base          1044 drivers/gpu/drm/meson/meson_venc.c 	writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN));
io_base          1045 drivers/gpu/drm/meson/meson_venc.c 	writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN));
io_base          1053 drivers/gpu/drm/meson/meson_venc.c 			       priv->io_base + _REG(ENCI_CFILT_CTRL));
io_base          1056 drivers/gpu/drm/meson/meson_venc.c 			       priv->io_base + _REG(ENCI_CFILT_CTRL2));
io_base          1059 drivers/gpu/drm/meson/meson_venc.c 		writel_relaxed(0, priv->io_base + _REG(VENC_DVI_SETTING));
io_base          1062 drivers/gpu/drm/meson/meson_venc.c 		writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE));
io_base          1063 drivers/gpu/drm/meson/meson_venc.c 		writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));
io_base          1067 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCI_SYNC_HSO_BEGIN));
io_base          1069 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCI_SYNC_HSO_END));
io_base          1073 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCI_SYNC_VSO_EVNLN));
io_base          1075 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCI_SYNC_VSO_ODDLN));
io_base          1080 drivers/gpu/drm/meson/meson_venc.c 			       priv->io_base + _REG(ENCI_MACV_MAX_AMP));
io_base          1084 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(VENC_VIDEO_PROG_MODE));
io_base          1086 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCI_VIDEO_MODE));
io_base          1100 drivers/gpu/drm/meson/meson_venc.c 			       priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));
io_base          1103 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCI_VIDEO_SCH));
io_base          1106 drivers/gpu/drm/meson/meson_venc.c 		writel_relaxed(0x07, priv->io_base + _REG(ENCI_SYNC_MODE));
io_base          1110 drivers/gpu/drm/meson/meson_venc.c 					priv->io_base + _REG(ENCI_YC_DELAY));
io_base          1114 drivers/gpu/drm/meson/meson_venc.c 		writel_relaxed(0, priv->io_base + _REG(ENCI_DBG_PX_RST));
io_base          1126 drivers/gpu/drm/meson/meson_venc.c 			       priv->io_base + _REG(ENCI_VFIFO2VD_CTL));
io_base          1130 drivers/gpu/drm/meson/meson_venc.c 			priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_START));
io_base          1132 drivers/gpu/drm/meson/meson_venc.c 			priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_END));
io_base          1135 drivers/gpu/drm/meson/meson_venc.c 			priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_START));
io_base          1137 drivers/gpu/drm/meson/meson_venc.c 			priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_END));
io_base          1140 drivers/gpu/drm/meson/meson_venc.c 			priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_START));
io_base          1142 drivers/gpu/drm/meson/meson_venc.c 			priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_END));
io_base          1149 drivers/gpu/drm/meson/meson_venc.c 			       priv->io_base + _REG(ENCI_VIDEO_EN));
io_base          1154 drivers/gpu/drm/meson/meson_venc.c 		de_h_begin = modulo(readl_relaxed(priv->io_base +
io_base          1162 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCI_DE_H_BEGIN));
io_base          1164 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCI_DE_H_END));
io_base          1166 drivers/gpu/drm/meson/meson_venc.c 		de_v_begin_even = readl_relaxed(priv->io_base +
io_base          1169 drivers/gpu/drm/meson/meson_venc.c 		de_v_begin_odd = readl_relaxed(priv->io_base +
io_base          1174 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCI_DE_V_BEGIN_EVEN));
io_base          1176 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCI_DE_V_END_EVEN));
io_base          1178 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCI_DE_V_BEGIN_ODD));
io_base          1180 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCI_DE_V_END_ODD));
io_base          1195 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCI_DVI_HSO_BEGIN));
io_base          1197 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCI_DVI_HSO_END));
io_base          1208 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCI_DVI_VSO_BLINE_EVN));
io_base          1211 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCI_DVI_VSO_ELINE_EVN));
io_base          1214 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCI_DVI_VSO_BEGIN_EVN));
io_base          1216 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCI_DVI_VSO_END_EVN));
io_base          1223 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCI_DVI_VSO_BLINE_ODD));
io_base          1226 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCI_DVI_VSO_BEGIN_ODD));
io_base          1233 drivers/gpu/drm/meson/meson_venc.c 				writel_relaxed(vs_eline_evn, priv->io_base
io_base          1236 drivers/gpu/drm/meson/meson_venc.c 				writel_relaxed(hs_begin, priv->io_base
io_base          1242 drivers/gpu/drm/meson/meson_venc.c 				writel_relaxed(vs_eline_odd, priv->io_base
io_base          1245 drivers/gpu/drm/meson/meson_venc.c 				writel_relaxed(hs_begin, priv->io_base
io_base          1258 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCI_DVI_VSO_BLINE_ODD));
io_base          1261 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCI_DVI_VSO_ELINE_ODD));
io_base          1268 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCI_DVI_VSO_BEGIN_ODD));
io_base          1270 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCI_DVI_VSO_END_ODD));
io_base          1276 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCI_DVI_VSO_BLINE_EVN));
io_base          1282 drivers/gpu/drm/meson/meson_venc.c 			writel_relaxed(vso_begin_evn, priv->io_base
io_base          1290 drivers/gpu/drm/meson/meson_venc.c 				writel_relaxed(vs_eline_odd, priv->io_base
io_base          1293 drivers/gpu/drm/meson/meson_venc.c 				writel_relaxed(vso_begin_evn, priv->io_base
io_base          1298 drivers/gpu/drm/meson/meson_venc.c 				writel_relaxed(vs_eline_evn, priv->io_base
io_base          1301 drivers/gpu/drm/meson/meson_venc.c 				writel_relaxed(vso_begin_evn, priv->io_base
io_base          1307 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(VENC_DVI_SETTING));
io_base          1309 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCP_VIDEO_MODE));
io_base          1311 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCP_VIDEO_MODE_ADV));
io_base          1314 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(VENC_VIDEO_PROG_MODE));
io_base          1317 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCP_VIDEO_SYNC_MODE));
io_base          1320 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCP_VIDEO_YC_DLY));
io_base          1323 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCP_VIDEO_RGB_CTRL));
io_base          1326 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCP_VIDEO_FILT_CTRL));
io_base          1329 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base
io_base          1332 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCP_VIDEO_YFP1_HTIME));
io_base          1334 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCP_VIDEO_YFP2_HTIME));
io_base          1336 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCP_VIDEO_MAX_PXCNT));
io_base          1338 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCP_VIDEO_HSPULS_BEGIN));
io_base          1340 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCP_VIDEO_HSPULS_END));
io_base          1342 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCP_VIDEO_HSPULS_SWITCH));
io_base          1344 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCP_VIDEO_VSPULS_BEGIN));
io_base          1346 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCP_VIDEO_VSPULS_END));
io_base          1348 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCP_VIDEO_VSPULS_BLINE));
io_base          1350 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCP_VIDEO_VSPULS_ELINE));
io_base          1353 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCP_VIDEO_EQPULS_BEGIN));
io_base          1356 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCP_VIDEO_EQPULS_END));
io_base          1359 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCP_VIDEO_EQPULS_BLINE));
io_base          1362 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCP_VIDEO_EQPULS_ELINE));
io_base          1364 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCP_VIDEO_HAVON_BEGIN));
io_base          1366 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCP_VIDEO_HAVON_END));
io_base          1368 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCP_VIDEO_VAVON_BLINE));
io_base          1370 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCP_VIDEO_VAVON_ELINE));
io_base          1372 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCP_VIDEO_HSO_BEGIN));
io_base          1374 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCP_VIDEO_HSO_END));
io_base          1376 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCP_VIDEO_VSO_BEGIN));
io_base          1378 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCP_VIDEO_VSO_END));
io_base          1380 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCP_VIDEO_VSO_BLINE));
io_base          1383 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCP_VIDEO_VSO_ELINE));
io_base          1386 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCP_VIDEO_SY_VAL));
io_base          1389 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCP_VIDEO_SY2_VAL));
io_base          1391 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCP_VIDEO_MAX_LNCNT));
io_base          1393 drivers/gpu/drm/meson/meson_venc.c 		writel_relaxed(1, priv->io_base + _REG(ENCP_VIDEO_EN));
io_base          1398 drivers/gpu/drm/meson/meson_venc.c 				    priv->io_base + _REG(ENCP_VIDEO_MODE));
io_base          1401 drivers/gpu/drm/meson/meson_venc.c 		de_h_begin = modulo(readl_relaxed(priv->io_base +
io_base          1409 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCP_DE_H_BEGIN));
io_base          1411 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCP_DE_H_END));
io_base          1414 drivers/gpu/drm/meson/meson_venc.c 		de_v_begin_even = readl_relaxed(priv->io_base
io_base          1423 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCP_DE_V_BEGIN_EVEN));
io_base          1425 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCP_DE_V_END_EVEN));
io_base          1430 drivers/gpu/drm/meson/meson_venc.c 				readl_relaxed(priv->io_base +
io_base          1438 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCP_DE_V_BEGIN_ODD));
io_base          1440 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCP_DE_V_END_ODD));
io_base          1459 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCP_DVI_HSO_BEGIN));
io_base          1461 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCP_DVI_HSO_END));
io_base          1481 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCP_DVI_VSO_BLINE_EVN));
io_base          1483 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCP_DVI_VSO_ELINE_EVN));
io_base          1487 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCP_DVI_VSO_BEGIN_EVN));
io_base          1489 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCP_DVI_VSO_END_EVN));
io_base          1503 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCP_DVI_VSO_BLINE_ODD));
io_base          1505 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCP_DVI_VSO_ELINE_ODD));
io_base          1507 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCP_DVI_VSO_BEGIN_ODD));
io_base          1509 drivers/gpu/drm/meson/meson_venc.c 				priv->io_base + _REG(ENCP_DVI_VSO_END_ODD));
io_base          1548 drivers/gpu/drm/meson/meson_venc.c 	writel_relaxed(reg, priv->io_base + _REG(VPU_HDMI_SETTING));
io_base          1568 drivers/gpu/drm/meson/meson_venc.c 		       priv->io_base + _REG(ENCI_CFILT_CTRL));
io_base          1571 drivers/gpu/drm/meson/meson_venc.c 		       priv->io_base + _REG(ENCI_CFILT_CTRL2));
io_base          1574 drivers/gpu/drm/meson/meson_venc.c 	writel_relaxed(0, priv->io_base + _REG(VENC_DVI_SETTING));
io_base          1577 drivers/gpu/drm/meson/meson_venc.c 	writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE));
io_base          1578 drivers/gpu/drm/meson/meson_venc.c 	writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));
io_base          1582 drivers/gpu/drm/meson/meson_venc.c 			priv->io_base + _REG(ENCI_SYNC_HSO_BEGIN));
io_base          1584 drivers/gpu/drm/meson/meson_venc.c 			priv->io_base + _REG(ENCI_SYNC_HSO_END));
io_base          1588 drivers/gpu/drm/meson/meson_venc.c 			priv->io_base + _REG(ENCI_SYNC_VSO_EVNLN));
io_base          1590 drivers/gpu/drm/meson/meson_venc.c 			priv->io_base + _REG(ENCI_SYNC_VSO_ODDLN));
io_base          1595 drivers/gpu/drm/meson/meson_venc.c 		       priv->io_base + _REG(ENCI_MACV_MAX_AMP));
io_base          1599 drivers/gpu/drm/meson/meson_venc.c 			priv->io_base + _REG(VENC_VIDEO_PROG_MODE));
io_base          1601 drivers/gpu/drm/meson/meson_venc.c 			priv->io_base + _REG(ENCI_VIDEO_MODE));
io_base          1615 drivers/gpu/drm/meson/meson_venc.c 		       priv->io_base + _REG(ENCI_VIDEO_MODE_ADV));
io_base          1617 drivers/gpu/drm/meson/meson_venc.c 	writel(mode->sch_adjust, priv->io_base + _REG(ENCI_VIDEO_SCH));
io_base          1620 drivers/gpu/drm/meson/meson_venc.c 	writel_relaxed(0x07, priv->io_base + _REG(ENCI_SYNC_MODE));
io_base          1623 drivers/gpu/drm/meson/meson_venc.c 	writel_relaxed(mode->yc_delay, priv->io_base + _REG(ENCI_YC_DELAY));
io_base          1627 drivers/gpu/drm/meson/meson_venc.c 			priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_START));
io_base          1629 drivers/gpu/drm/meson/meson_venc.c 			priv->io_base + _REG(ENCI_VFIFO2VD_PIXEL_END));
io_base          1632 drivers/gpu/drm/meson/meson_venc.c 			priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_START));
io_base          1634 drivers/gpu/drm/meson/meson_venc.c 			priv->io_base + _REG(ENCI_VFIFO2VD_LINE_TOP_END));
io_base          1637 drivers/gpu/drm/meson/meson_venc.c 			priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_START));
io_base          1639 drivers/gpu/drm/meson/meson_venc.c 			priv->io_base + _REG(ENCI_VFIFO2VD_LINE_BOT_END));
io_base          1642 drivers/gpu/drm/meson/meson_venc.c 	writel_relaxed(0, priv->io_base + _REG(VENC_SYNC_ROUTE));
io_base          1645 drivers/gpu/drm/meson/meson_venc.c 	writel_relaxed(0, priv->io_base + _REG(ENCI_DBG_PX_RST));
io_base          1657 drivers/gpu/drm/meson/meson_venc.c 		       priv->io_base + _REG(ENCI_VFIFO2VD_CTL));
io_base          1660 drivers/gpu/drm/meson/meson_venc.c 	writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_SETTING));
io_base          1676 drivers/gpu/drm/meson/meson_venc.c 		       priv->io_base + _REG(VENC_UPSAMPLE_CTRL0));
io_base          1683 drivers/gpu/drm/meson/meson_venc.c 		       priv->io_base + _REG(VENC_UPSAMPLE_CTRL1));
io_base          1690 drivers/gpu/drm/meson/meson_venc.c 		       priv->io_base + _REG(VENC_UPSAMPLE_CTRL2));
io_base          1693 drivers/gpu/drm/meson/meson_venc.c 	writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL0));
io_base          1694 drivers/gpu/drm/meson/meson_venc.c 	writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL1));
io_base          1695 drivers/gpu/drm/meson/meson_venc.c 	writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL2));
io_base          1696 drivers/gpu/drm/meson/meson_venc.c 	writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL3));
io_base          1697 drivers/gpu/drm/meson/meson_venc.c 	writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL4));
io_base          1698 drivers/gpu/drm/meson/meson_venc.c 	writel_relaxed(0, priv->io_base + _REG(VENC_VDAC_DACSEL5));
io_base          1705 drivers/gpu/drm/meson/meson_venc.c 		       priv->io_base + _REG(VENC_VDAC_FIFO_CTRL));
io_base          1708 drivers/gpu/drm/meson/meson_venc.c 	writel_relaxed(0x11, priv->io_base + _REG(ENCI_DACSEL_0));
io_base          1709 drivers/gpu/drm/meson/meson_venc.c 	writel_relaxed(0x11, priv->io_base + _REG(ENCI_DACSEL_1));
io_base          1713 drivers/gpu/drm/meson/meson_venc.c 		       priv->io_base + _REG(ENCI_VIDEO_EN));
io_base          1717 drivers/gpu/drm/meson/meson_venc.c 			priv->io_base + _REG(ENCI_VIDEO_SAT));
io_base          1719 drivers/gpu/drm/meson/meson_venc.c 			priv->io_base + _REG(ENCI_VIDEO_CONT));
io_base          1721 drivers/gpu/drm/meson/meson_venc.c 			priv->io_base + _REG(ENCI_VIDEO_BRIGHT));
io_base          1723 drivers/gpu/drm/meson/meson_venc.c 			priv->io_base + _REG(ENCI_VIDEO_HUE));
io_base          1727 drivers/gpu/drm/meson/meson_venc.c 		       priv->io_base + _REG(VENC_VDAC_DAC0_FILT_CTRL0));
io_base          1728 drivers/gpu/drm/meson/meson_venc.c 	writel_relaxed(0xfc48, priv->io_base + _REG(VENC_VDAC_DAC0_FILT_CTRL1));
io_base          1731 drivers/gpu/drm/meson/meson_venc.c 	writel_relaxed(0, priv->io_base + _REG(ENCI_MACV_N0));
io_base          1735 drivers/gpu/drm/meson/meson_venc.c 			priv->io_base + _REG(ENCI_SYNC_ADJ));
io_base          1743 drivers/gpu/drm/meson/meson_venc.c 	return readl_relaxed(priv->io_base + _REG(ENCI_INFO_READ)) & BIT(29);
io_base          1749 drivers/gpu/drm/meson/meson_venc.c 		       priv->io_base + _REG(VENC_INTCTRL));
io_base          1756 drivers/gpu/drm/meson/meson_venc.c 	writel_relaxed(0, priv->io_base + _REG(VENC_INTCTRL));
io_base          1771 drivers/gpu/drm/meson/meson_venc.c 	writel_relaxed(0xff, priv->io_base + _REG(VENC_VDAC_SETTING));
io_base          1779 drivers/gpu/drm/meson/meson_venc.c 			    priv->io_base + _REG(VPU_HDMI_SETTING));
io_base          1782 drivers/gpu/drm/meson/meson_venc.c 	writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN));
io_base          1783 drivers/gpu/drm/meson/meson_venc.c 	writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN));
io_base          1784 drivers/gpu/drm/meson/meson_venc.c 	writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN));
io_base           188 drivers/gpu/drm/meson/meson_venc_cvbs.c 			    priv->io_base + _REG(VENC_VDAC_DACSEL0));
io_base            83 drivers/gpu/drm/meson/meson_viu.c 		priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_PRE_OFFSET0_1));
io_base            85 drivers/gpu/drm/meson/meson_viu.c 		priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_PRE_OFFSET2));
io_base            87 drivers/gpu/drm/meson/meson_viu.c 		priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF00_01));
io_base            89 drivers/gpu/drm/meson/meson_viu.c 		priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF02_10));
io_base            91 drivers/gpu/drm/meson/meson_viu.c 		priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF11_12));
io_base            93 drivers/gpu/drm/meson/meson_viu.c 		priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF20_21));
io_base            95 drivers/gpu/drm/meson/meson_viu.c 		priv->io_base +	_REG(VPP_WRAP_OSD1_MATRIX_COEF22));
io_base            98 drivers/gpu/drm/meson/meson_viu.c 		priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_OFFSET0_1));
io_base           100 drivers/gpu/drm/meson/meson_viu.c 		priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_OFFSET2));
io_base           103 drivers/gpu/drm/meson/meson_viu.c 		priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_EN_CTRL));
io_base           113 drivers/gpu/drm/meson/meson_viu.c 			priv->io_base + _REG(VIU_OSD1_MATRIX_PRE_OFFSET0_1));
io_base           115 drivers/gpu/drm/meson/meson_viu.c 			priv->io_base + _REG(VIU_OSD1_MATRIX_PRE_OFFSET2));
io_base           117 drivers/gpu/drm/meson/meson_viu.c 			priv->io_base + _REG(VIU_OSD1_MATRIX_COEF00_01));
io_base           119 drivers/gpu/drm/meson/meson_viu.c 			priv->io_base + _REG(VIU_OSD1_MATRIX_COEF02_10));
io_base           121 drivers/gpu/drm/meson/meson_viu.c 			priv->io_base + _REG(VIU_OSD1_MATRIX_COEF11_12));
io_base           123 drivers/gpu/drm/meson/meson_viu.c 			priv->io_base + _REG(VIU_OSD1_MATRIX_COEF20_21));
io_base           127 drivers/gpu/drm/meson/meson_viu.c 				priv->io_base +
io_base           130 drivers/gpu/drm/meson/meson_viu.c 				priv->io_base +
io_base           133 drivers/gpu/drm/meson/meson_viu.c 				priv->io_base +
io_base           135 drivers/gpu/drm/meson/meson_viu.c 			writel(m[17] & 0x1fff, priv->io_base +
io_base           138 drivers/gpu/drm/meson/meson_viu.c 			writel((m[11] & 0x1fff) << 16, priv->io_base +
io_base           142 drivers/gpu/drm/meson/meson_viu.c 			priv->io_base + _REG(VIU_OSD1_MATRIX_OFFSET0_1));
io_base           144 drivers/gpu/drm/meson/meson_viu.c 			priv->io_base + _REG(VIU_OSD1_MATRIX_OFFSET2));
io_base           147 drivers/gpu/drm/meson/meson_viu.c 			priv->io_base + _REG(VIU_OSD1_MATRIX_COLMOD_COEF42));
io_base           149 drivers/gpu/drm/meson/meson_viu.c 			priv->io_base + _REG(VIU_OSD1_MATRIX_COLMOD_COEF42));
io_base           153 drivers/gpu/drm/meson/meson_viu.c 			priv->io_base + _REG(VIU_OSD1_MATRIX_CTRL));
io_base           155 drivers/gpu/drm/meson/meson_viu.c 			priv->io_base + _REG(VIU_OSD1_MATRIX_CTRL));
io_base           162 drivers/gpu/drm/meson/meson_viu.c 				(m[i * 2 + 1] & 0x1fff), priv->io_base +
io_base           166 drivers/gpu/drm/meson/meson_viu.c 			priv->io_base + _REG(VIU_OSD1_EOTF_CTL));
io_base           168 drivers/gpu/drm/meson/meson_viu.c 			priv->io_base + _REG(VIU_OSD1_EOTF_CTL));
io_base           197 drivers/gpu/drm/meson/meson_viu.c 		writel(0, priv->io_base + _REG(addr_port));
io_base           201 drivers/gpu/drm/meson/meson_viu.c 				priv->io_base + _REG(data_port));
io_base           204 drivers/gpu/drm/meson/meson_viu.c 			priv->io_base + _REG(data_port));
io_base           208 drivers/gpu/drm/meson/meson_viu.c 				priv->io_base + _REG(data_port));
io_base           212 drivers/gpu/drm/meson/meson_viu.c 				priv->io_base + _REG(data_port));
io_base           215 drivers/gpu/drm/meson/meson_viu.c 			priv->io_base + _REG(data_port));
io_base           219 drivers/gpu/drm/meson/meson_viu.c 					    priv->io_base + _REG(ctrl_port));
io_base           222 drivers/gpu/drm/meson/meson_viu.c 					    priv->io_base + _REG(ctrl_port));
io_base           224 drivers/gpu/drm/meson/meson_viu.c 		writel(0, priv->io_base + _REG(addr_port));
io_base           228 drivers/gpu/drm/meson/meson_viu.c 				priv->io_base + _REG(data_port));
io_base           231 drivers/gpu/drm/meson/meson_viu.c 			priv->io_base + _REG(data_port));
io_base           235 drivers/gpu/drm/meson/meson_viu.c 				priv->io_base + _REG(data_port));
io_base           239 drivers/gpu/drm/meson/meson_viu.c 				priv->io_base + _REG(data_port));
io_base           242 drivers/gpu/drm/meson/meson_viu.c 			priv->io_base + _REG(data_port));
io_base           246 drivers/gpu/drm/meson/meson_viu.c 					    priv->io_base + _REG(ctrl_port));
io_base           249 drivers/gpu/drm/meson/meson_viu.c 					    priv->io_base + _REG(ctrl_port));
io_base           252 drivers/gpu/drm/meson/meson_viu.c 				    priv->io_base + _REG(ctrl_port));
io_base           318 drivers/gpu/drm/meson/meson_viu.c 				priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT));
io_base           320 drivers/gpu/drm/meson/meson_viu.c 				priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
io_base           324 drivers/gpu/drm/meson/meson_viu.c 			    priv->io_base + _REG(VIU_SW_RESET));
io_base           326 drivers/gpu/drm/meson/meson_viu.c 			    priv->io_base + _REG(VIU_SW_RESET));
io_base           330 drivers/gpu/drm/meson/meson_viu.c 		       priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT));
io_base           332 drivers/gpu/drm/meson/meson_viu.c 		       priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
io_base           351 drivers/gpu/drm/meson/meson_viu.c 			    priv->io_base + _REG(VIU_OSD1_CTRL_STAT));
io_base           353 drivers/gpu/drm/meson/meson_viu.c 			    priv->io_base + _REG(VIU_OSD2_CTRL_STAT));
io_base           375 drivers/gpu/drm/meson/meson_viu.c 	writel_relaxed(reg, priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT));
io_base           376 drivers/gpu/drm/meson/meson_viu.c 	writel_relaxed(reg, priv->io_base + _REG(VIU_OSD2_FIFO_CTRL_STAT));
io_base           381 drivers/gpu/drm/meson/meson_viu.c 			    priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
io_base           384 drivers/gpu/drm/meson/meson_viu.c 			    priv->io_base + _REG(VIU_OSD2_CTRL_STAT2));
io_base           389 drivers/gpu/drm/meson/meson_viu.c 			    priv->io_base + _REG(VIU_MISC_CTRL0));
io_base           390 drivers/gpu/drm/meson/meson_viu.c 	writel_relaxed(0, priv->io_base + _REG(AFBC_ENABLE));
io_base           393 drivers/gpu/drm/meson/meson_viu.c 			priv->io_base + _REG(VD1_IF0_LUMA_FIFO_SIZE));
io_base           395 drivers/gpu/drm/meson/meson_viu.c 			priv->io_base + _REG(VD2_IF0_LUMA_FIFO_SIZE));
io_base           408 drivers/gpu/drm/meson/meson_viu.c 			       priv->io_base + _REG(VIU_OSD_BLEND_CTRL));
io_base           411 drivers/gpu/drm/meson/meson_viu.c 			       priv->io_base + _REG(OSD1_BLEND_SRC_CTRL));
io_base           413 drivers/gpu/drm/meson/meson_viu.c 			       priv->io_base + _REG(OSD2_BLEND_SRC_CTRL));
io_base           414 drivers/gpu/drm/meson/meson_viu.c 		writel_relaxed(0, priv->io_base + _REG(VD1_BLEND_SRC_CTRL));
io_base           415 drivers/gpu/drm/meson/meson_viu.c 		writel_relaxed(0, priv->io_base + _REG(VD2_BLEND_SRC_CTRL));
io_base           417 drivers/gpu/drm/meson/meson_viu.c 				priv->io_base + _REG(VIU_OSD_BLEND_DUMMY_DATA0));
io_base           419 drivers/gpu/drm/meson/meson_viu.c 				priv->io_base + _REG(VIU_OSD_BLEND_DUMMY_ALPHA));
io_base           422 drivers/gpu/drm/meson/meson_viu.c 				    priv->io_base + _REG(DOLBY_PATH_CTRL));
io_base            38 drivers/gpu/drm/meson/meson_vpp.c 	writel(mux, priv->io_base + _REG(VPU_VIU_VENC_MUX_CTRL));
io_base            60 drivers/gpu/drm/meson/meson_vpp.c 			priv->io_base + _REG(VPP_OSD_SCALE_COEF_IDX));
io_base            63 drivers/gpu/drm/meson/meson_vpp.c 				priv->io_base + _REG(VPP_OSD_SCALE_COEF));
io_base            85 drivers/gpu/drm/meson/meson_vpp.c 			priv->io_base + _REG(VPP_SCALE_COEF_IDX));
io_base            88 drivers/gpu/drm/meson/meson_vpp.c 				priv->io_base + _REG(VPP_SCALE_COEF));
io_base            95 drivers/gpu/drm/meson/meson_vpp.c 		writel_relaxed(0x108080, priv->io_base + _REG(VPP_DUMMY_DATA1));
io_base            98 drivers/gpu/drm/meson/meson_vpp.c 				    priv->io_base + _REG(VIU_MISC_CTRL1));
io_base           100 drivers/gpu/drm/meson/meson_vpp.c 			       priv->io_base + _REG(VPP_DOLBY_CTRL));
io_base           102 drivers/gpu/drm/meson/meson_vpp.c 				priv->io_base + _REG(VPP_DUMMY_DATA1));
io_base           104 drivers/gpu/drm/meson/meson_vpp.c 		writel_relaxed(0xf, priv->io_base + _REG(DOLBY_PATH_CTRL));
io_base           109 drivers/gpu/drm/meson/meson_vpp.c 			       priv->io_base + _REG(VPP_OFIFO_SIZE));
io_base           112 drivers/gpu/drm/meson/meson_vpp.c 				    priv->io_base + _REG(VPP_OFIFO_SIZE));
io_base           114 drivers/gpu/drm/meson/meson_vpp.c 		       priv->io_base + _REG(VPP_HOLD_LINES));
io_base           119 drivers/gpu/drm/meson/meson_vpp.c 				    priv->io_base + _REG(VPP_MISC));
io_base           123 drivers/gpu/drm/meson/meson_vpp.c 				    priv->io_base + _REG(VPP_MISC));
io_base           129 drivers/gpu/drm/meson/meson_vpp.c 				    priv->io_base + _REG(VPP_MISC));
io_base           133 drivers/gpu/drm/meson/meson_vpp.c 				priv->io_base + _REG(VPP_PREBLEND_VD1_H_START_END));
io_base           135 drivers/gpu/drm/meson/meson_vpp.c 				priv->io_base + _REG(VPP_BLEND_VD2_H_START_END));
io_base           139 drivers/gpu/drm/meson/meson_vpp.c 	writel_relaxed(0, priv->io_base + _REG(VPP_OSD_SC_CTRL0));
io_base           140 drivers/gpu/drm/meson/meson_vpp.c 	writel_relaxed(0, priv->io_base + _REG(VPP_OSD_VSC_CTRL0));
io_base           141 drivers/gpu/drm/meson/meson_vpp.c 	writel_relaxed(0, priv->io_base + _REG(VPP_OSD_HSC_CTRL0));
io_base           146 drivers/gpu/drm/meson/meson_vpp.c 		       priv->io_base + _REG(VPP_SC_MISC));
io_base           150 drivers/gpu/drm/meson/meson_vpp.c 		       priv->io_base + _REG(VPP_VADJ_CTRL));
io_base           290 drivers/gpu/drm/qxl/qxl_cmd.c 	long addr = qdev->io_base + port;
io_base           363 drivers/gpu/drm/qxl/qxl_cmd.c 	outb(0, qdev->io_base + QXL_IO_NOTIFY_OOM);
io_base           368 drivers/gpu/drm/qxl/qxl_cmd.c 	outb(0, qdev->io_base + QXL_IO_FLUSH_RELEASE);
io_base           418 drivers/gpu/drm/qxl/qxl_cmd.c 	outb(0, qdev->io_base + QXL_IO_RESET);
io_base           214 drivers/gpu/drm/qxl/qxl_drv.h 	int io_base;
io_base            70 drivers/gpu/drm/qxl/qxl_irq.c 	outb(0, qdev->io_base + QXL_IO_UPDATE_IRQ);
io_base           134 drivers/gpu/drm/qxl/qxl_kms.c 	qdev->io_base = pci_resource_start(pdev, 3);
io_base           208 drivers/gpu/drm/qxl/qxl_kms.c 					     qdev->io_base + QXL_IO_NOTIFY_CMD,
io_base           221 drivers/gpu/drm/qxl/qxl_kms.c 				qdev->io_base + QXL_IO_NOTIFY_CMD,
io_base            80 drivers/hwspinlock/omap_hwspinlock.c 	void __iomem *io_base;
io_base            92 drivers/hwspinlock/omap_hwspinlock.c 	io_base = ioremap(res->start, resource_size(res));
io_base            93 drivers/hwspinlock/omap_hwspinlock.c 	if (!io_base)
io_base           108 drivers/hwspinlock/omap_hwspinlock.c 	i = readl(io_base + SYSSTATUS_OFFSET);
io_base           136 drivers/hwspinlock/omap_hwspinlock.c 		hwlock->priv = io_base + LOCK_BASE_OFFSET + sizeof(u32) * i;
io_base           152 drivers/hwspinlock/omap_hwspinlock.c 	iounmap(io_base);
io_base           159 drivers/hwspinlock/omap_hwspinlock.c 	void __iomem *io_base = bank->lock[0].priv - LOCK_BASE_OFFSET;
io_base           169 drivers/hwspinlock/omap_hwspinlock.c 	iounmap(io_base);
io_base            23 drivers/hwspinlock/sirf_hwspinlock.c 	void __iomem *io_base;
io_base            72 drivers/hwspinlock/sirf_hwspinlock.c 	hwspin->io_base = of_iomap(pdev->dev.of_node, 0);
io_base            73 drivers/hwspinlock/sirf_hwspinlock.c 	if (!hwspin->io_base)
io_base            78 drivers/hwspinlock/sirf_hwspinlock.c 		hwlock->priv = hwspin->io_base + HW_SPINLOCK_OFFSET(idx);
io_base            95 drivers/hwspinlock/sirf_hwspinlock.c 	iounmap(hwspin->io_base);
io_base           113 drivers/hwspinlock/sirf_hwspinlock.c 	iounmap(hwspin->io_base);
io_base            60 drivers/hwspinlock/stm32_hwspinlock.c 	void __iomem *io_base;
io_base            66 drivers/hwspinlock/stm32_hwspinlock.c 	io_base = devm_ioremap_resource(&pdev->dev, res);
io_base            67 drivers/hwspinlock/stm32_hwspinlock.c 	if (IS_ERR(io_base))
io_base            68 drivers/hwspinlock/stm32_hwspinlock.c 		return PTR_ERR(io_base);
io_base            80 drivers/hwspinlock/stm32_hwspinlock.c 		hw->bank.lock[i].priv = io_base + i * sizeof(u32);
io_base            92 drivers/hwspinlock/u8500_hsem.c 	void __iomem *io_base;
io_base           103 drivers/hwspinlock/u8500_hsem.c 	io_base = ioremap(res->start, resource_size(res));
io_base           104 drivers/hwspinlock/u8500_hsem.c 	if (!io_base)
io_base           108 drivers/hwspinlock/u8500_hsem.c 	val = readl(io_base + HSEM_CTRL_REG);
io_base           109 drivers/hwspinlock/u8500_hsem.c 	writel((val & ~HSEM_PROTOCOL_1), io_base + HSEM_CTRL_REG);
io_base           112 drivers/hwspinlock/u8500_hsem.c 	writel(0xFFFF, io_base + HSEM_ICRALL);
io_base           123 drivers/hwspinlock/u8500_hsem.c 		hwlock->priv = io_base + HSEM_REGISTER_OFFSET + sizeof(u32) * i;
io_base           139 drivers/hwspinlock/u8500_hsem.c 	iounmap(io_base);
io_base           146 drivers/hwspinlock/u8500_hsem.c 	void __iomem *io_base = bank->lock[0].priv - HSEM_REGISTER_OFFSET;
io_base           150 drivers/hwspinlock/u8500_hsem.c 	writel(0xFFFF, io_base + HSEM_ICRALL);
io_base           159 drivers/hwspinlock/u8500_hsem.c 	iounmap(io_base);
io_base            36 drivers/i2c/busses/i2c-pca-platform.c 	unsigned long			io_base;
io_base           160 drivers/i2c/busses/i2c-pca-platform.c 	i2c->io_base = res->start;
io_base           908 drivers/ide/hpt366.c 	unsigned long io_base	= pci_resource_start(dev, 4);
io_base           940 drivers/ide/hpt366.c 			outb(0x0e, io_base + 0x9c);
io_base           967 drivers/ide/hpt366.c 			unsigned long io_base = pci_resource_start(dev1, 4);
io_base           969 drivers/ide/hpt366.c 			temp =	inl(io_base + 0x90);
io_base           972 drivers/ide/hpt366.c 			temp =	inl(io_base + 0x90);
io_base          1143 drivers/ide/hpt366.c 		outb(inb(io_base + 0x9c) | 0x04, io_base + 0x9c);
io_base           193 drivers/ide/ide-cs.c     unsigned long io_base, ctl_base;
io_base           207 drivers/ide/ide-cs.c     io_base = link->resource[0]->start;
io_base           227 drivers/ide/ide-cs.c      host = idecs_register(io_base, ctl_base, link->irq, link);
io_base           230 drivers/ide/ide-cs.c 	    host = idecs_register(io_base + 0x10, ctl_base + 0x10,
io_base            57 drivers/input/keyboard/spear-keyboard.c 	void __iomem *io_base;
io_base            76 drivers/input/keyboard/spear-keyboard.c 	sts = readl_relaxed(kbd->io_base + STATUS_REG);
io_base            86 drivers/input/keyboard/spear-keyboard.c 	val = readl_relaxed(kbd->io_base + DATA_REG) &
io_base            97 drivers/input/keyboard/spear-keyboard.c 	writel_relaxed(0, kbd->io_base + STATUS_REG);
io_base           121 drivers/input/keyboard/spear-keyboard.c 	writel_relaxed(val, kbd->io_base + MODE_CTL_REG);
io_base           122 drivers/input/keyboard/spear-keyboard.c 	writel_relaxed(1, kbd->io_base + STATUS_REG);
io_base           125 drivers/input/keyboard/spear-keyboard.c 	val = readl_relaxed(kbd->io_base + MODE_CTL_REG);
io_base           127 drivers/input/keyboard/spear-keyboard.c 	writel_relaxed(val, kbd->io_base + MODE_CTL_REG);
io_base           138 drivers/input/keyboard/spear-keyboard.c 	val = readl_relaxed(kbd->io_base + MODE_CTL_REG);
io_base           140 drivers/input/keyboard/spear-keyboard.c 	writel_relaxed(val, kbd->io_base + MODE_CTL_REG);
io_base           223 drivers/input/keyboard/spear-keyboard.c 	kbd->io_base = devm_ioremap_resource(&pdev->dev, res);
io_base           224 drivers/input/keyboard/spear-keyboard.c 	if (IS_ERR(kbd->io_base))
io_base           225 drivers/input/keyboard/spear-keyboard.c 		return PTR_ERR(kbd->io_base);
io_base           299 drivers/input/keyboard/spear-keyboard.c 	mode_ctl_reg = readl_relaxed(kbd->io_base + MODE_CTL_REG);
io_base           318 drivers/input/keyboard/spear-keyboard.c 		writel_relaxed(val, kbd->io_base + MODE_CTL_REG);
io_base           323 drivers/input/keyboard/spear-keyboard.c 					kbd->io_base + MODE_CTL_REG);
io_base           360 drivers/input/keyboard/spear-keyboard.c 		writel_relaxed(kbd->mode_ctl_reg, kbd->io_base + MODE_CTL_REG);
io_base            27 drivers/leds/leds-nic78bx.c 	u16 io_base;
io_base            52 drivers/leds/leds-nic78bx.c 	value = inb(nled->data->io_base);
io_base            61 drivers/leds/leds-nic78bx.c 	outb(value, nled->data->io_base);
io_base            72 drivers/leds/leds-nic78bx.c 	value = inb(nled->data->io_base);
io_base           152 drivers/leds/leds-nic78bx.c 	led_data->io_base = io_rc->start;
io_base           165 drivers/leds/leds-nic78bx.c 	     led_data->io_base + NIC78BX_LOCK_REG_OFFSET);
io_base           176 drivers/leds/leds-nic78bx.c 	     led_data->io_base + NIC78BX_LOCK_REG_OFFSET);
io_base           138 drivers/media/platform/atmel/atmel-sama5d2-isc.c 	void __iomem *io_base;
io_base           151 drivers/media/platform/atmel/atmel-sama5d2-isc.c 	io_base = devm_ioremap_resource(dev, res);
io_base           152 drivers/media/platform/atmel/atmel-sama5d2-isc.c 	if (IS_ERR(io_base))
io_base           153 drivers/media/platform/atmel/atmel-sama5d2-isc.c 		return PTR_ERR(io_base);
io_base           155 drivers/media/platform/atmel/atmel-sama5d2-isc.c 	isc->regmap = devm_regmap_init_mmio(dev, io_base, &isc_regmap_config);
io_base           426 drivers/media/platform/s3c-camif/camif-core.c 	camif->io_base = devm_ioremap_resource(dev, mres);
io_base           427 drivers/media/platform/s3c-camif/camif-core.c 	if (IS_ERR(camif->io_base))
io_base           428 drivers/media/platform/s3c-camif/camif-core.c 		return PTR_ERR(camif->io_base);
io_base           296 drivers/media/platform/s3c-camif/camif-core.h 	void __iomem			*io_base;
io_base            13 drivers/media/platform/s3c-camif/camif-regs.c #define camif_write(_camif, _off, _val)	writel(_val, (_camif)->io_base + (_off))
io_base            14 drivers/media/platform/s3c-camif/camif-regs.c #define camif_read(_camif, _off)	readl((_camif)->io_base + (_off))
io_base           600 drivers/media/platform/s3c-camif/camif-regs.c 		u32 cfg = readl(camif->io_base + registers[i].offset);
io_base           264 drivers/media/platform/s3c-camif/camif-regs.h 	return readl(vp->camif->io_base + S3C_CAMIF_REG_CISTATUS(vp->id,
io_base           834 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c 	void __iomem *io_base;
io_base           839 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c 	io_base = devm_ioremap_resource(&pdev->dev, res);
io_base           840 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c 	if (IS_ERR(io_base))
io_base           841 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c 		return PTR_ERR(io_base);
io_base           843 drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c 	sdev->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "bus", io_base,
io_base           453 drivers/mfd/kempld-core.c 	pld->io_base = devm_ioport_map(dev, ioport->start,
io_base           455 drivers/mfd/kempld-core.c 	if (!pld->io_base)
io_base           458 drivers/mfd/kempld-core.c 	pld->io_index = pld->io_base;
io_base           459 drivers/mfd/kempld-core.c 	pld->io_data = pld->io_base + 1;
io_base           165 drivers/mfd/tqmx86.c 	void __iomem *io_base;
io_base           186 drivers/mfd/tqmx86.c 	io_base = devm_ioport_map(dev, TQMX86_IOBASE, TQMX86_IOSIZE);
io_base           187 drivers/mfd/tqmx86.c 	if (!io_base)
io_base           190 drivers/mfd/tqmx86.c 	board_id = ioread8(io_base + TQMX86_REG_BOARD_ID);
io_base           192 drivers/mfd/tqmx86.c 	rev = ioread8(io_base + TQMX86_REG_BOARD_REV);
io_base           198 drivers/mfd/tqmx86.c 	i2c_det = ioread8(io_base + TQMX86_REG_I2C_DETECT);
io_base           199 drivers/mfd/tqmx86.c 	i2c_ien = ioread8(io_base + TQMX86_REG_I2C_INT_EN);
io_base           204 drivers/mfd/tqmx86.c 		iowrite8(io_ext_int_val, io_base + TQMX86_REG_IO_EXT_INT);
io_base           205 drivers/mfd/tqmx86.c 		readback = ioread8(io_base + TQMX86_REG_IO_EXT_INT);
io_base           174 drivers/mtd/devices/spear_smi.c 	void __iomem *io_base;
io_base           229 drivers/mtd/devices/spear_smi.c 	ctrlreg1 = readl(dev->io_base + SMI_CR1);
io_base           231 drivers/mtd/devices/spear_smi.c 	writel(ctrlreg1 & ~(SW_MODE | WB_MODE), dev->io_base + SMI_CR1);
io_base           235 drivers/mtd/devices/spear_smi.c 			dev->io_base + SMI_CR2);
io_base           248 drivers/mtd/devices/spear_smi.c 	writel(ctrlreg1, dev->io_base + SMI_CR1);
io_base           249 drivers/mtd/devices/spear_smi.c 	writel(0, dev->io_base + SMI_CR2);
io_base           301 drivers/mtd/devices/spear_smi.c 	status = readl(dev->io_base + SMI_SR);
io_base           307 drivers/mtd/devices/spear_smi.c 	writel(0, dev->io_base + SMI_SR);
io_base           343 drivers/mtd/devices/spear_smi.c 	writel(0, dev->io_base + SMI_SR);
io_base           345 drivers/mtd/devices/spear_smi.c 	writel(val, dev->io_base + SMI_CR1);
io_base           387 drivers/mtd/devices/spear_smi.c 	ctrlreg1 = readl(dev->io_base + SMI_CR1);
io_base           389 drivers/mtd/devices/spear_smi.c 	writel(ctrlreg1 & ~SW_MODE, dev->io_base + SMI_CR1);
io_base           392 drivers/mtd/devices/spear_smi.c 	writel((bank << BANK_SHIFT) | WE | TFIE, dev->io_base + SMI_CR2);
io_base           398 drivers/mtd/devices/spear_smi.c 	writel(ctrlreg1, dev->io_base + SMI_CR1);
io_base           399 drivers/mtd/devices/spear_smi.c 	writel(0, dev->io_base + SMI_CR2);
io_base           460 drivers/mtd/devices/spear_smi.c 	ctrlreg1 = readl(dev->io_base + SMI_CR1);
io_base           461 drivers/mtd/devices/spear_smi.c 	writel((ctrlreg1 | SW_MODE) & ~WB_MODE, dev->io_base + SMI_CR1);
io_base           464 drivers/mtd/devices/spear_smi.c 	writel(command, dev->io_base + SMI_TR);
io_base           467 drivers/mtd/devices/spear_smi.c 			dev->io_base + SMI_CR2);
io_base           479 drivers/mtd/devices/spear_smi.c 	writel(ctrlreg1, dev->io_base + SMI_CR1);
io_base           480 drivers/mtd/devices/spear_smi.c 	writel(0, dev->io_base + SMI_CR2);
io_base           576 drivers/mtd/devices/spear_smi.c 	ctrlreg1 = val = readl(dev->io_base + SMI_CR1);
io_base           581 drivers/mtd/devices/spear_smi.c 	writel(val, dev->io_base + SMI_CR1);
io_base           586 drivers/mtd/devices/spear_smi.c 	writel(ctrlreg1, dev->io_base + SMI_CR1);
io_base           634 drivers/mtd/devices/spear_smi.c 	ctrlreg1 = readl(dev->io_base + SMI_CR1);
io_base           635 drivers/mtd/devices/spear_smi.c 	writel((ctrlreg1 | WB_MODE) & ~SW_MODE, dev->io_base + SMI_CR1);
io_base           655 drivers/mtd/devices/spear_smi.c 	writel(ctrlreg1, dev->io_base + SMI_CR1);
io_base           758 drivers/mtd/devices/spear_smi.c 	val = readl(dev->io_base + SMI_CR1);
io_base           759 drivers/mtd/devices/spear_smi.c 	writel(val | SW_MODE, dev->io_base + SMI_CR1);
io_base           762 drivers/mtd/devices/spear_smi.c 	writel(OPCODE_RDID, dev->io_base + SMI_TR);
io_base           766 drivers/mtd/devices/spear_smi.c 	writel(val, dev->io_base + SMI_CR2);
io_base           777 drivers/mtd/devices/spear_smi.c 	val = readl(dev->io_base + SMI_RR);
io_base           783 drivers/mtd/devices/spear_smi.c 	val = readl(dev->io_base + SMI_CR1);
io_base           784 drivers/mtd/devices/spear_smi.c 	writel(val & ~SW_MODE, dev->io_base + SMI_CR1);
io_base           984 drivers/mtd/devices/spear_smi.c 	dev->io_base = devm_ioremap_resource(&pdev->dev, smi_base);
io_base           985 drivers/mtd/devices/spear_smi.c 	if (IS_ERR(dev->io_base)) {
io_base           986 drivers/mtd/devices/spear_smi.c 		ret = PTR_ERR(dev->io_base);
io_base            36 drivers/mtd/nand/raw/fsl_upm.c 	void __iomem *io_base;
io_base           114 drivers/mtd/nand/raw/fsl_upm.c 		chip->legacy.IO_ADDR_R = fun->io_base + fun->mchip_offsets[mchip_nr];
io_base           159 drivers/mtd/nand/raw/fsl_upm.c 	fun->chip.legacy.IO_ADDR_R = fun->io_base;
io_base           160 drivers/mtd/nand/raw/fsl_upm.c 	fun->chip.legacy.IO_ADDR_W = fun->io_base;
io_base           288 drivers/mtd/nand/raw/fsl_upm.c 	fun->io_base = devm_ioremap_nocache(&ofdev->dev, io_res.start,
io_base           290 drivers/mtd/nand/raw/fsl_upm.c 	if (!fun->io_base) {
io_base           181 drivers/mtd/nand/raw/lpc32xx_mlc.c 	void __iomem		*io_base;
io_base           237 drivers/mtd/nand/raw/lpc32xx_mlc.c 	writel(MLCCMD_RESET, MLC_CMD(host->io_base));
io_base           247 drivers/mtd/nand/raw/lpc32xx_mlc.c 	writew(MLCLOCKPR_MAGIC, MLC_LOCK_PR(host->io_base));
io_base           251 drivers/mtd/nand/raw/lpc32xx_mlc.c 	writel(tmp, MLC_ICR(host->io_base));
io_base           255 drivers/mtd/nand/raw/lpc32xx_mlc.c 	writew(MLCLOCKPR_MAGIC, MLC_LOCK_PR(host->io_base));
io_base           266 drivers/mtd/nand/raw/lpc32xx_mlc.c 	writel(tmp, MLC_TIME_REG(host->io_base));
io_base           270 drivers/mtd/nand/raw/lpc32xx_mlc.c 			MLC_IRQ_MR(host->io_base));
io_base           273 drivers/mtd/nand/raw/lpc32xx_mlc.c 	writel(MLCCEH_NORMAL, MLC_CEH(host->io_base));
io_base           286 drivers/mtd/nand/raw/lpc32xx_mlc.c 			writel(cmd, MLC_CMD(host->io_base));
io_base           288 drivers/mtd/nand/raw/lpc32xx_mlc.c 			writel(cmd, MLC_ADDR(host->io_base));
io_base           299 drivers/mtd/nand/raw/lpc32xx_mlc.c 	if ((readb(MLC_ISR(host->io_base)) &
io_base           312 drivers/mtd/nand/raw/lpc32xx_mlc.c 	sr = readb(MLC_IRQ_SR(host->io_base));
io_base           326 drivers/mtd/nand/raw/lpc32xx_mlc.c 	if (readb(MLC_ISR(host->io_base)) & MLCISR_NAND_READY)
io_base           331 drivers/mtd/nand/raw/lpc32xx_mlc.c 	while (!(readb(MLC_ISR(host->io_base)) & MLCISR_NAND_READY)) {
io_base           346 drivers/mtd/nand/raw/lpc32xx_mlc.c 	if (readb(MLC_ISR(host->io_base)) & MLCISR_CONTROLLER_READY)
io_base           351 drivers/mtd/nand/raw/lpc32xx_mlc.c 	while (!(readb(MLC_ISR(host->io_base)) &
io_base           460 drivers/mtd/nand/raw/lpc32xx_mlc.c 		writeb(0x00, MLC_ECC_AUTO_DEC_REG(host->io_base));
io_base           466 drivers/mtd/nand/raw/lpc32xx_mlc.c 		mlc_isr = readl(MLC_ISR(host->io_base));
io_base           483 drivers/mtd/nand/raw/lpc32xx_mlc.c 					readl(MLC_BUFF(host->io_base));
io_base           489 drivers/mtd/nand/raw/lpc32xx_mlc.c 				readl(MLC_BUFF(host->io_base));
io_base           520 drivers/mtd/nand/raw/lpc32xx_mlc.c 		writeb(0x00, MLC_ECC_ENC_REG(host->io_base));
io_base           531 drivers/mtd/nand/raw/lpc32xx_mlc.c 				       MLC_BUFF(host->io_base));
io_base           535 drivers/mtd/nand/raw/lpc32xx_mlc.c 		writel(*((uint32_t *)(oobbuf)), MLC_BUFF(host->io_base));
io_base           537 drivers/mtd/nand/raw/lpc32xx_mlc.c 		writew(*((uint16_t *)(oobbuf)), MLC_BUFF(host->io_base));
io_base           541 drivers/mtd/nand/raw/lpc32xx_mlc.c 		writeb(0x00, MLC_ECC_AUTO_ENC_REG(host->io_base));
io_base           690 drivers/mtd/nand/raw/lpc32xx_mlc.c 	host->io_base = devm_ioremap_resource(&pdev->dev, rc);
io_base           691 drivers/mtd/nand/raw/lpc32xx_mlc.c 	if (IS_ERR(host->io_base))
io_base           692 drivers/mtd/nand/raw/lpc32xx_mlc.c 		return PTR_ERR(host->io_base);
io_base           735 drivers/mtd/nand/raw/lpc32xx_mlc.c 	nand_chip->legacy.IO_ADDR_R = MLC_DATA(host->io_base);
io_base           736 drivers/mtd/nand/raw/lpc32xx_mlc.c 	nand_chip->legacy.IO_ADDR_W = MLC_DATA(host->io_base);
io_base           769 drivers/mtd/nand/raw/lpc32xx_mlc.c 	readb(MLC_IRQ_SR(host->io_base));
io_base           221 drivers/mtd/nand/raw/lpc32xx_slc.c 	void __iomem		*io_base;
io_base           243 drivers/mtd/nand/raw/lpc32xx_slc.c 	writel(SLCCTRL_SW_RESET, SLC_CTRL(host->io_base));
io_base           247 drivers/mtd/nand/raw/lpc32xx_slc.c 	writel(0, SLC_CFG(host->io_base));
io_base           248 drivers/mtd/nand/raw/lpc32xx_slc.c 	writel(0, SLC_IEN(host->io_base));
io_base           250 drivers/mtd/nand/raw/lpc32xx_slc.c 		SLC_ICR(host->io_base));
io_base           266 drivers/mtd/nand/raw/lpc32xx_slc.c 	writel(tmp, SLC_TAC(host->io_base));
io_base           279 drivers/mtd/nand/raw/lpc32xx_slc.c 	tmp = readl(SLC_CFG(host->io_base));
io_base           284 drivers/mtd/nand/raw/lpc32xx_slc.c 	writel(tmp, SLC_CFG(host->io_base));
io_base           288 drivers/mtd/nand/raw/lpc32xx_slc.c 			writel(cmd, SLC_CMD(host->io_base));
io_base           290 drivers/mtd/nand/raw/lpc32xx_slc.c 			writel(cmd, SLC_ADDR(host->io_base));
io_base           302 drivers/mtd/nand/raw/lpc32xx_slc.c 	if ((readl(SLC_STAT(host->io_base)) & SLCSTAT_NAND_READY) != 0)
io_base           355 drivers/mtd/nand/raw/lpc32xx_slc.c 	return (uint8_t)readl(SLC_DATA(host->io_base));
io_base           367 drivers/mtd/nand/raw/lpc32xx_slc.c 		*buf++ = (uint8_t)readl(SLC_DATA(host->io_base));
io_base           380 drivers/mtd/nand/raw/lpc32xx_slc.c 		writel((uint32_t)*buf++, SLC_DATA(host->io_base));
io_base           511 drivers/mtd/nand/raw/lpc32xx_slc.c 		writel(readl(SLC_CFG(host->io_base)) |
io_base           513 drivers/mtd/nand/raw/lpc32xx_slc.c 		       SLCCFG_DMA_BURST, SLC_CFG(host->io_base));
io_base           515 drivers/mtd/nand/raw/lpc32xx_slc.c 		writel((readl(SLC_CFG(host->io_base)) |
io_base           518 drivers/mtd/nand/raw/lpc32xx_slc.c 			SLC_CFG(host->io_base));
io_base           522 drivers/mtd/nand/raw/lpc32xx_slc.c 	writel(SLCCTRL_ECC_CLEAR, SLC_CTRL(host->io_base));
io_base           525 drivers/mtd/nand/raw/lpc32xx_slc.c 	writel(mtd->writesize, SLC_TC(host->io_base));
io_base           528 drivers/mtd/nand/raw/lpc32xx_slc.c 	writel(readl(SLC_CTRL(host->io_base)) | SLCCTRL_DMA_START,
io_base           529 drivers/mtd/nand/raw/lpc32xx_slc.c 	       SLC_CTRL(host->io_base));
io_base           557 drivers/mtd/nand/raw/lpc32xx_slc.c 	if (readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO) {
io_base           560 drivers/mtd/nand/raw/lpc32xx_slc.c 		while ((readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO) &&
io_base           573 drivers/mtd/nand/raw/lpc32xx_slc.c 		readl(SLC_ECC(host->io_base));
io_base           578 drivers/mtd/nand/raw/lpc32xx_slc.c 	if (readl(SLC_STAT(host->io_base)) & SLCSTAT_DMA_FIFO ||
io_base           579 drivers/mtd/nand/raw/lpc32xx_slc.c 	    readl(SLC_TC(host->io_base))) {
io_base           586 drivers/mtd/nand/raw/lpc32xx_slc.c 	writel(readl(SLC_CTRL(host->io_base)) & ~SLCCTRL_DMA_START,
io_base           587 drivers/mtd/nand/raw/lpc32xx_slc.c 	       SLC_CTRL(host->io_base));
io_base           588 drivers/mtd/nand/raw/lpc32xx_slc.c 	writel(readl(SLC_CFG(host->io_base)) &
io_base           590 drivers/mtd/nand/raw/lpc32xx_slc.c 		 SLCCFG_DMA_BURST), SLC_CFG(host->io_base));
io_base           830 drivers/mtd/nand/raw/lpc32xx_slc.c 	host->io_base = devm_ioremap_resource(&pdev->dev, rc);
io_base           831 drivers/mtd/nand/raw/lpc32xx_slc.c 	if (IS_ERR(host->io_base))
io_base           832 drivers/mtd/nand/raw/lpc32xx_slc.c 		return PTR_ERR(host->io_base);
io_base           872 drivers/mtd/nand/raw/lpc32xx_slc.c 	chip->legacy.IO_ADDR_R = SLC_DATA(host->io_base);
io_base           873 drivers/mtd/nand/raw/lpc32xx_slc.c 	chip->legacy.IO_ADDR_W = SLC_DATA(host->io_base);
io_base           955 drivers/mtd/nand/raw/lpc32xx_slc.c 	tmp = readl(SLC_CTRL(host->io_base));
io_base           957 drivers/mtd/nand/raw/lpc32xx_slc.c 	writel(tmp, SLC_CTRL(host->io_base));
io_base           991 drivers/mtd/nand/raw/lpc32xx_slc.c 	tmp = readl(SLC_CTRL(host->io_base));
io_base           993 drivers/mtd/nand/raw/lpc32xx_slc.c 	writel(tmp, SLC_CTRL(host->io_base));
io_base            53 drivers/mtd/nand/raw/orion_nand.c 	void __iomem *io_base = chip->legacy.IO_ADDR_R;
io_base            60 drivers/mtd/nand/raw/orion_nand.c 		*buf++ = readb(io_base);
io_base            73 drivers/mtd/nand/raw/orion_nand.c 		asm volatile ("ldrd\t%0, [%1]" : "=&r" (x) : "r" (io_base));
io_base            78 drivers/mtd/nand/raw/orion_nand.c 	readsl(io_base, buf, len/4);
io_base            82 drivers/mtd/nand/raw/orion_nand.c 		buf[i++] = readb(io_base);
io_base            92 drivers/mtd/nand/raw/orion_nand.c 	void __iomem *io_base;
io_base           105 drivers/mtd/nand/raw/orion_nand.c 	io_base = devm_ioremap_resource(&pdev->dev, res);
io_base           107 drivers/mtd/nand/raw/orion_nand.c 	if (IS_ERR(io_base))
io_base           108 drivers/mtd/nand/raw/orion_nand.c 		return PTR_ERR(io_base);
io_base           139 drivers/mtd/nand/raw/orion_nand.c 	nc->legacy.IO_ADDR_R = nc->legacy.IO_ADDR_W = io_base;
io_base            32 drivers/mtd/nand/raw/oxnas_nand.c 	void __iomem *io_base;
io_base            41 drivers/mtd/nand/raw/oxnas_nand.c 	return readb(oxnas->io_base);
io_base            48 drivers/mtd/nand/raw/oxnas_nand.c 	ioread8_rep(oxnas->io_base, buf, len);
io_base            56 drivers/mtd/nand/raw/oxnas_nand.c 	iowrite8_rep(oxnas->io_base, buf, len);
io_base            66 drivers/mtd/nand/raw/oxnas_nand.c 		writeb(cmd, oxnas->io_base + OXNAS_NAND_CMD_CLE);
io_base            68 drivers/mtd/nand/raw/oxnas_nand.c 		writeb(cmd, oxnas->io_base + OXNAS_NAND_CMD_ALE);
io_base            95 drivers/mtd/nand/raw/oxnas_nand.c 	oxnas->io_base = devm_ioremap_resource(&pdev->dev, res);
io_base            96 drivers/mtd/nand/raw/oxnas_nand.c 	if (IS_ERR(oxnas->io_base))
io_base            97 drivers/mtd/nand/raw/oxnas_nand.c 		return PTR_ERR(oxnas->io_base);
io_base            18 drivers/mtd/nand/raw/plat_nand.c 	void __iomem		*io_base;
io_base            50 drivers/mtd/nand/raw/plat_nand.c 	data->io_base = devm_ioremap_resource(&pdev->dev, res);
io_base            51 drivers/mtd/nand/raw/plat_nand.c 	if (IS_ERR(data->io_base))
io_base            52 drivers/mtd/nand/raw/plat_nand.c 		return PTR_ERR(data->io_base);
io_base            58 drivers/mtd/nand/raw/plat_nand.c 	data->chip.legacy.IO_ADDR_R = data->io_base;
io_base            59 drivers/mtd/nand/raw/plat_nand.c 	data->chip.legacy.IO_ADDR_W = data->io_base;
io_base            26 drivers/mtd/nand/raw/socrates_nand.c 	void __iomem		*io_base;
io_base            43 drivers/mtd/nand/raw/socrates_nand.c 		out_be32(host->io_base, FPGA_NAND_ENABLE |
io_base            64 drivers/mtd/nand/raw/socrates_nand.c 	out_be32(host->io_base, val);
io_base            66 drivers/mtd/nand/raw/socrates_nand.c 		buf[i] = (in_be32(host->io_base) >>
io_base           104 drivers/mtd/nand/raw/socrates_nand.c 	out_be32(host->io_base, val);
io_base           114 drivers/mtd/nand/raw/socrates_nand.c 	if (in_be32(host->io_base) & FPGA_NAND_BUSY)
io_base           134 drivers/mtd/nand/raw/socrates_nand.c 	host->io_base = of_iomap(ofdev->dev.of_node, 0);
io_base           135 drivers/mtd/nand/raw/socrates_nand.c 	if (host->io_base == NULL) {
io_base           175 drivers/mtd/nand/raw/socrates_nand.c 	iounmap(host->io_base);
io_base           188 drivers/mtd/nand/raw/socrates_nand.c 	iounmap(host->io_base);
io_base           254 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	void __iomem *io_base;
io_base           290 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	u32 pcr = readl_relaxed(fmc2->io_base + FMC2_PCR);
io_base           311 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	writel_relaxed(pcr, fmc2->io_base + FMC2_PCR);
io_base           312 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	writel_relaxed(pmem, fmc2->io_base + FMC2_PMEM);
io_base           313 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	writel_relaxed(patt, fmc2->io_base + FMC2_PATT);
io_base           320 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	u32 pcr = readl_relaxed(fmc2->io_base + FMC2_PCR);
io_base           341 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	writel_relaxed(pcr, fmc2->io_base + FMC2_PCR);
io_base           413 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	u32 pcr = readl_relaxed(fmc2->io_base + FMC2_PCR);
io_base           418 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	writel_relaxed(pcr, fmc2->io_base + FMC2_PCR);
io_base           424 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	u32 pcr = readl(fmc2->io_base + FMC2_PCR);
io_base           429 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	writel(pcr, fmc2->io_base + FMC2_PCR);
io_base           435 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	u32 csqier = readl_relaxed(fmc2->io_base + FMC2_CSQIER);
io_base           441 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	writel_relaxed(csqier, fmc2->io_base + FMC2_CSQIER);
io_base           447 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	u32 csqier = readl_relaxed(fmc2->io_base + FMC2_CSQIER);
io_base           451 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	writel_relaxed(csqier, fmc2->io_base + FMC2_CSQIER);
io_base           459 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	writel_relaxed(FMC2_CSQICR_CLEAR_IRQ, fmc2->io_base + FMC2_CSQICR);
io_base           466 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	u32 bchier = readl_relaxed(fmc2->io_base + FMC2_BCHIER);
io_base           475 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	writel_relaxed(bchier, fmc2->io_base + FMC2_BCHIER);
io_base           481 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	u32 bchier = readl_relaxed(fmc2->io_base + FMC2_BCHIER);
io_base           486 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	writel_relaxed(bchier, fmc2->io_base + FMC2_BCHIER);
io_base           494 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	writel_relaxed(FMC2_BCHICR_CLEAR_IRQ, fmc2->io_base + FMC2_BCHICR);
io_base           508 drivers/mtd/nand/raw/stm32_fmc2_nand.c 		u32 pcr = readl_relaxed(fmc2->io_base + FMC2_PCR);
io_base           514 drivers/mtd/nand/raw/stm32_fmc2_nand.c 		writel_relaxed(pcr, fmc2->io_base + FMC2_PCR);
io_base           543 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	ret = readl_relaxed_poll_timeout(fmc2->io_base + FMC2_SR,
io_base           551 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	heccr = readl_relaxed(fmc2->io_base + FMC2_HECCR);
io_base           633 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	bchpbr = readl_relaxed(fmc2->io_base + FMC2_BCHPBR1);
io_base           639 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	bchpbr = readl_relaxed(fmc2->io_base + FMC2_BCHPBR2);
io_base           647 drivers/mtd/nand/raw/stm32_fmc2_nand.c 		bchpbr = readl_relaxed(fmc2->io_base + FMC2_BCHPBR3);
io_base           653 drivers/mtd/nand/raw/stm32_fmc2_nand.c 		bchpbr = readl_relaxed(fmc2->io_base + FMC2_BCHPBR4);
io_base           717 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	ecc_sta[0] = readl_relaxed(fmc2->io_base + FMC2_BCHDSR0);
io_base           718 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	ecc_sta[1] = readl_relaxed(fmc2->io_base + FMC2_BCHDSR1);
io_base           719 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	ecc_sta[2] = readl_relaxed(fmc2->io_base + FMC2_BCHDSR2);
io_base           720 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	ecc_sta[3] = readl_relaxed(fmc2->io_base + FMC2_BCHDSR3);
io_base           721 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	ecc_sta[4] = readl_relaxed(fmc2->io_base + FMC2_BCHDSR4);
io_base           800 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	u32 pcr = readl_relaxed(fmc2->io_base + FMC2_PCR);
io_base           806 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	writel_relaxed(pcr, fmc2->io_base + FMC2_PCR);
io_base           880 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	writel_relaxed(csqcfgr1, fmc2->io_base + FMC2_CSQCFGR1);
io_base           881 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	writel_relaxed(csqcfgr2, fmc2->io_base + FMC2_CSQCFGR2);
io_base           882 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	writel_relaxed(csqcfgr3, fmc2->io_base + FMC2_CSQCFGR3);
io_base           883 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	writel_relaxed(csqar1, fmc2->io_base + FMC2_CSQAR1);
io_base           884 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	writel_relaxed(csqar2, fmc2->io_base + FMC2_CSQAR2);
io_base           902 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	u32 csqcr = readl_relaxed(fmc2->io_base + FMC2_CSQCR);
io_base           980 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	writel_relaxed(csqcr, fmc2->io_base + FMC2_CSQCR);
io_base          1083 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	u32 csqemsr = readl_relaxed(fmc2->io_base + FMC2_CSQEMSR);
io_base          1341 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	if (readl_relaxed_poll_timeout_atomic(fmc2->io_base + FMC2_SR, sr,
io_base          1351 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	writel_relaxed(FMC2_ICR_CIHLF, fmc2->io_base + FMC2_ICR);
io_base          1354 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	return readl_relaxed_poll_timeout_atomic(fmc2->io_base + FMC2_ISR,
io_base          1415 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	u32 pcr = readl_relaxed(fmc2->io_base + FMC2_PCR);
io_base          1416 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	u32 bcr1 = readl_relaxed(fmc2->io_base + FMC2_BCR1);
io_base          1449 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	writel_relaxed(bcr1, fmc2->io_base + FMC2_BCR1);
io_base          1450 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	writel_relaxed(pcr, fmc2->io_base + FMC2_PCR);
io_base          1451 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	writel_relaxed(FMC2_PMEM_DEFAULT, fmc2->io_base + FMC2_PMEM);
io_base          1452 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	writel_relaxed(FMC2_PATT_DEFAULT, fmc2->io_base + FMC2_PATT);
io_base          1885 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	fmc2->io_base = devm_ioremap_resource(dev, res);
io_base          1886 drivers/mtd/nand/raw/stm32_fmc2_nand.c 	if (IS_ERR(fmc2->io_base))
io_base          1887 drivers/mtd/nand/raw/stm32_fmc2_nand.c 		return PTR_ERR(fmc2->io_base);
io_base            57 drivers/mtd/spi-nor/nxp-spifi.c 	void __iomem *io_base;
io_base            69 drivers/mtd/spi-nor/nxp-spifi.c 	ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat,
io_base            82 drivers/mtd/spi-nor/nxp-spifi.c 	writel(SPIFI_STAT_RESET, spifi->io_base + SPIFI_STAT);
io_base            83 drivers/mtd/spi-nor/nxp-spifi.c 	ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat,
io_base           115 drivers/mtd/spi-nor/nxp-spifi.c 	writel(spifi->mcmd, spifi->io_base + SPIFI_MCMD);
io_base           116 drivers/mtd/spi-nor/nxp-spifi.c 	ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat,
io_base           140 drivers/mtd/spi-nor/nxp-spifi.c 	writel(cmd, spifi->io_base + SPIFI_CMD);
io_base           143 drivers/mtd/spi-nor/nxp-spifi.c 		*buf++ = readb(spifi->io_base + SPIFI_DATA);
io_base           163 drivers/mtd/spi-nor/nxp-spifi.c 	writel(cmd, spifi->io_base + SPIFI_CMD);
io_base           166 drivers/mtd/spi-nor/nxp-spifi.c 		writeb(*buf++, spifi->io_base + SPIFI_DATA);
io_base           198 drivers/mtd/spi-nor/nxp-spifi.c 	writel(to, spifi->io_base + SPIFI_ADDR);
io_base           205 drivers/mtd/spi-nor/nxp-spifi.c 	writel(cmd, spifi->io_base + SPIFI_CMD);
io_base           208 drivers/mtd/spi-nor/nxp-spifi.c 		writeb(buf[i], spifi->io_base + SPIFI_DATA);
io_base           227 drivers/mtd/spi-nor/nxp-spifi.c 	writel(offs, spifi->io_base + SPIFI_ADDR);
io_base           232 drivers/mtd/spi-nor/nxp-spifi.c 	writel(cmd, spifi->io_base + SPIFI_CMD);
io_base           330 drivers/mtd/spi-nor/nxp-spifi.c 	writel(ctrl, spifi->io_base + SPIFI_CTRL);
io_base           385 drivers/mtd/spi-nor/nxp-spifi.c 	spifi->io_base = devm_ioremap_resource(&pdev->dev, res);
io_base           386 drivers/mtd/spi-nor/nxp-spifi.c 	if (IS_ERR(spifi->io_base))
io_base           387 drivers/mtd/spi-nor/nxp-spifi.c 		return PTR_ERR(spifi->io_base);
io_base           423 drivers/mtd/spi-nor/nxp-spifi.c 	writel(0, spifi->io_base + SPIFI_IDATA);
io_base           424 drivers/mtd/spi-nor/nxp-spifi.c 	writel(0, spifi->io_base + SPIFI_MCMD);
io_base           433 drivers/net/ethernet/broadcom/bnx2.c 	cp->io_base = bp->regview;
io_base          15155 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c 	cp->io_base = bp->regview;
io_base          5326 drivers/net/ethernet/broadcom/cnic.c 	dev->regview = ethdev->io_base;
io_base           211 drivers/net/ethernet/broadcom/cnic_if.h 	void __iomem	*io_base;
io_base           267 drivers/net/ethernet/hisilicon/hns/hnae.h 	u8 __iomem *io_base; /* base io address for the ring */
io_base           353 drivers/net/ethernet/hisilicon/hns/hnae.h 	u8 __iomem *io_base;
io_base           586 drivers/net/ethernet/hisilicon/hns/hnae.h 	(q)->tx_ring.io_base + RCB_REG_TAIL)
io_base           736 drivers/net/ethernet/hisilicon/hns/hns_dsaf_gmac.c 	mac_drv->io_base = mac_param->vaddr;
io_base           972 drivers/net/ethernet/hisilicon/hns/hns_dsaf_mac.c 	u8 __iomem *base = dsaf_dev->io_base;
io_base           401 drivers/net/ethernet/hisilicon/hns/hns_dsaf_mac.h 	u8 __iomem *io_base;
io_base           159 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c 		dsaf_dev->io_base = devm_ioremap_resource(&pdev->dev, res);
io_base           160 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c 		if (IS_ERR(dsaf_dev->io_base))
io_base           161 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c 			return PTR_ERR(dsaf_dev->io_base);
io_base           328 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.h 	u8 __iomem *io_base;
io_base            97 drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.c 	ppe_common->io_base = hns_ppe_common_get_ioaddr(ppe_common);
io_base           128 drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.c 		ppe_cb->io_base = hns_ppe_get_iobase(ppe_common, i);
io_base            79 drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.h 	u8 __iomem *io_base;
io_base            88 drivers/net/ethernet/hisilicon/hns/hns_dsaf_ppe.h 	u8 __iomem *io_base;
io_base           452 drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.c 		ring->io_base = ring_pair_cb->q.io_base;
io_base           457 drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.c 		ring->io_base = ring_pair_cb->q.io_base +
io_base           529 drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.c 		ring_pair_cb->q.io_base =
io_base           530 drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.c 			RCB_COMM_BASE_TO_RING_BASE(rcb_common->io_base, i);
io_base           804 drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.c 	rcb_common->io_base = hns_rcb_common_get_vaddr(rcb_common);
io_base           101 drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.h 	u8 __iomem *io_base;
io_base          1023 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h 	dsaf_write_reg((a)->io_base, (reg), (value))
io_base          1041 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h 	dsaf_read_reg((a)->io_base, (reg))
io_base          1062 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h 	dsaf_set_reg_field((dev)->io_base, (reg), (mask), (shift), (val))
io_base          1065 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h 	dsaf_set_reg_field((dev)->io_base, (reg), (1ull << (bit)), (bit), (val))
io_base          1082 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h 	dsaf_get_reg_field((dev)->io_base, (reg), (mask), (shift))
io_base          1085 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h 	dsaf_get_reg_field((dev)->io_base, (reg), (1ull << (bit)), (bit))
io_base          1093 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h 	readq((__iomem void *)(((drv)->io_base + 0xc00 + (offset))))
io_base           809 drivers/net/ethernet/hisilicon/hns/hns_dsaf_xgmac.c 	mac_drv->io_base = mac_param->vaddr;
io_base           691 drivers/net/ethernet/hisilicon/hns/hns_enet.c 	writel_relaxed(i, ring->io_base + RCB_REG_HEAD);
io_base           830 drivers/net/ethernet/hisilicon/hns/hns_enet.c 	num = readl_relaxed(ring->io_base + RCB_REG_FBDNUM);
io_base           882 drivers/net/ethernet/hisilicon/hns/hns_enet.c 	num = readl_relaxed(ring->io_base + RCB_REG_FBDNUM);
io_base           905 drivers/net/ethernet/hisilicon/hns/hns_enet.c 	num = readl_relaxed(ring->io_base + RCB_REG_FBDNUM);
io_base           958 drivers/net/ethernet/hisilicon/hns/hns_enet.c 	head = readl_relaxed(ring->io_base + RCB_REG_HEAD);
io_base          1010 drivers/net/ethernet/hisilicon/hns/hns_enet.c 	head = readl_relaxed(ring->io_base + RCB_REG_HEAD);
io_base          1025 drivers/net/ethernet/hisilicon/hns/hns_enet.c 	int head = readl_relaxed(ring->io_base + RCB_REG_HEAD);
io_base          1656 drivers/net/ethernet/hisilicon/hns/hns_enet.c 		head = readl_relaxed(ring->io_base + RCB_REG_HEAD);
io_base          1657 drivers/net/ethernet/hisilicon/hns/hns_enet.c 		tail = readl_relaxed(ring->io_base + RCB_REG_TAIL);
io_base            87 drivers/net/ethernet/hisilicon/hns3/hnae3.h 	void __iomem *io_base;
io_base            58 drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c 		base_add_h = readl_relaxed(ring->tqp->io_base +
io_base            60 drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c 		base_add_l = readl_relaxed(ring->tqp->io_base +
io_base            65 drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c 		value = readl_relaxed(ring->tqp->io_base +
io_base            69 drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c 		value = readl_relaxed(ring->tqp->io_base +
io_base            73 drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c 		value = readl_relaxed(ring->tqp->io_base +
io_base            77 drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c 		value = readl_relaxed(ring->tqp->io_base +
io_base            81 drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c 		value = readl_relaxed(ring->tqp->io_base +
io_base            85 drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c 		value = readl_relaxed(ring->tqp->io_base +
io_base            90 drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c 		base_add_h = readl_relaxed(ring->tqp->io_base +
io_base            92 drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c 		base_add_l = readl_relaxed(ring->tqp->io_base +
io_base            97 drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c 		value = readl_relaxed(ring->tqp->io_base +
io_base           101 drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c 		value = readl_relaxed(ring->tqp->io_base +
io_base           105 drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c 		value = readl_relaxed(ring->tqp->io_base +
io_base           109 drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c 		value = readl_relaxed(ring->tqp->io_base +
io_base           113 drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c 		value = readl_relaxed(ring->tqp->io_base +
io_base           117 drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c 		value = readl_relaxed(ring->tqp->io_base +
io_base           121 drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c 		value = readl_relaxed(ring->tqp->io_base +
io_base           188 drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c 	value = readl_relaxed(ring->tqp->io_base + HNS3_RING_TX_RING_TAIL_REG);
io_base           218 drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c 	value = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_TAIL_REG);
io_base          1746 drivers/net/ethernet/hisilicon/hns3/hns3_enet.c 	hw_head = readl_relaxed(tx_ring->tqp->io_base +
io_base          1748 drivers/net/ethernet/hisilicon/hns3/hns3_enet.c 	hw_tail = readl_relaxed(tx_ring->tqp->io_base +
io_base          1750 drivers/net/ethernet/hisilicon/hns3/hns3_enet.c 	fbd_num = readl_relaxed(tx_ring->tqp->io_base +
io_base          1752 drivers/net/ethernet/hisilicon/hns3/hns3_enet.c 	fbd_oft = readl_relaxed(tx_ring->tqp->io_base +
io_base          1754 drivers/net/ethernet/hisilicon/hns3/hns3_enet.c 	ebd_num = readl_relaxed(tx_ring->tqp->io_base +
io_base          1756 drivers/net/ethernet/hisilicon/hns3/hns3_enet.c 	ebd_oft = readl_relaxed(tx_ring->tqp->io_base +
io_base          1758 drivers/net/ethernet/hisilicon/hns3/hns3_enet.c 	bd_num = readl_relaxed(tx_ring->tqp->io_base +
io_base          1760 drivers/net/ethernet/hisilicon/hns3/hns3_enet.c 	bd_err = readl_relaxed(tx_ring->tqp->io_base +
io_base          1762 drivers/net/ethernet/hisilicon/hns3/hns3_enet.c 	ring_en = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_EN_REG);
io_base          1763 drivers/net/ethernet/hisilicon/hns3/hns3_enet.c 	tc = readl_relaxed(tx_ring->tqp->io_base + HNS3_RING_TX_RING_TC_REG);
io_base          2338 drivers/net/ethernet/hisilicon/hns3/hns3_enet.c 	head = readl_relaxed(ring->tqp->io_base + HNS3_RING_TX_RING_HEAD_REG);
io_base          2429 drivers/net/ethernet/hisilicon/hns3/hns3_enet.c 	writel_relaxed(i, ring->tqp->io_base + HNS3_RING_RX_RING_HEAD_REG);
io_base          2958 drivers/net/ethernet/hisilicon/hns3/hns3_enet.c 	num = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_FBDNUM_REG);
io_base          3503 drivers/net/ethernet/hisilicon/hns3/hns3_enet.c 		ring->io_base = (u8 __iomem *)q->io_base + HNS3_TX_REG_OFFSET;
io_base          3508 drivers/net/ethernet/hisilicon/hns3/hns3_enet.c 		ring->io_base = q->io_base;
io_base           402 drivers/net/ethernet/hisilicon/hns3/hns3_enet.h 	u8 __iomem *io_base; /* base io address for the ring */
io_base           599 drivers/net/ethernet/hisilicon/hns3/hns3_enet.h 	hns3_read_reg((a)->io_base, (reg))
io_base           609 drivers/net/ethernet/hisilicon/hns3/hns3_enet.h 	hns3_write_reg((a)->io_base, (reg), (value))
io_base           612 drivers/net/ethernet/hisilicon/hns3/hns3_enet.h 		(tqp)->io_base + HNS3_RING_TX_RING_TAIL_REG)
io_base          1073 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h 	hclge_write_reg((a)->io_base, (reg), (value))
io_base          1075 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h 	hclge_read_reg((a)->io_base, (reg))
io_base          1467 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c 		tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET +
io_base          2289 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c 	roce->rinfo.roce_io_base = vport->back->hw.io_base;
io_base          3044 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c 	vector->addr = hdev->hw.io_base + HCLGE_MISC_VECTOR_REG_BASE;
io_base          3949 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c 				vector->io_addr = hdev->hw.io_base +
io_base          9059 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c 	hw->io_base = pcim_iomap(pdev, 2, 0);
io_base          9060 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c 	if (!hw->io_base) {
io_base          9082 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c 	pcim_iounmap(pdev, hdev->hw.io_base);
io_base          9361 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c 	pcim_iounmap(pdev, hdev->hw.io_base);
io_base           275 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h 	void __iomem *io_base;
io_base           269 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h 	hclgevf_write_reg((a)->io_base, (reg), (value))
io_base           271 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h 	hclgevf_read_reg((a)->io_base, (reg))
io_base           373 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c 		tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET +
io_base           519 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c 				vector->io_addr = hdev->hw.io_base +
io_base          1412 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c 		ret = readl_poll_timeout(hdev->hw.io_base +
io_base          1418 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c 		ret = readl_poll_timeout(hdev->hw.io_base +
io_base          1694 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c 	vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE;
io_base          2036 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c 	roce->rinfo.roce_io_base = hdev->hw.io_base;
io_base          2502 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c 	hw->io_base = pci_iomap(pdev, 2, 0);
io_base          2503 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c 	if (!hw->io_base) {
io_base          2524 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c 	pci_iounmap(pdev, hdev->hw.io_base);
io_base           167 drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h 	void __iomem *io_base;
io_base          4877 drivers/net/ethernet/intel/e1000/e1000_hw.c 	unsigned long io_addr = hw->io_base;
io_base          4878 drivers/net/ethernet/intel/e1000/e1000_hw.c 	unsigned long io_data = hw->io_base + 4;
io_base          1347 drivers/net/ethernet/intel/e1000/e1000_hw.h 	unsigned long io_base;
io_base           984 drivers/net/ethernet/intel/e1000/e1000_main.c 				hw->io_base = pci_resource_start(pdev, i);
io_base           522 drivers/net/ethernet/intel/igb/e1000_hw.h 	unsigned long io_base;
io_base           221 drivers/net/ethernet/intel/igbvf/vf.h 	unsigned long io_base;
io_base           197 drivers/net/ethernet/intel/igc/igc_hw.h 	unsigned long io_base;
io_base           667 drivers/net/ethernet/intel/ixgb/ixgb_hw.h 	unsigned long io_base;	/* Our I/O mapped location */
io_base           419 drivers/net/ethernet/intel/ixgb/ixgb_main.c 			adapter->hw.io_base = pci_resource_start(pdev, i);
io_base          2020 drivers/net/ethernet/ti/tlan.c static void tlan_print_dio(u16 io_base)
io_base          2026 drivers/net/ethernet/ti/tlan.c 		io_base);
io_base          2029 drivers/net/ethernet/ti/tlan.c 		data0 = tlan_dio_read32(io_base, i);
io_base          2030 drivers/net/ethernet/ti/tlan.c 		data1 = tlan_dio_read32(io_base, i + 0x4);
io_base          3090 drivers/net/ethernet/ti/tlan.c static void tlan_ee_send_start(u16 io_base)
io_base          3094 drivers/net/ethernet/ti/tlan.c 	outw(TLAN_NET_SIO, io_base + TLAN_DIO_ADR);
io_base          3095 drivers/net/ethernet/ti/tlan.c 	sio = io_base + TLAN_DIO_DATA + TLAN_NET_SIO;
io_base          3130 drivers/net/ethernet/ti/tlan.c static int tlan_ee_send_byte(u16 io_base, u8 data, int stop)
io_base          3136 drivers/net/ethernet/ti/tlan.c 	outw(TLAN_NET_SIO, io_base + TLAN_DIO_ADR);
io_base          3137 drivers/net/ethernet/ti/tlan.c 	sio = io_base + TLAN_DIO_DATA + TLAN_NET_SIO;
io_base          3192 drivers/net/ethernet/ti/tlan.c static void tlan_ee_receive_byte(u16 io_base, u8 *data, int stop)
io_base          3197 drivers/net/ethernet/ti/tlan.c 	outw(TLAN_NET_SIO, io_base + TLAN_DIO_ADR);
io_base          3198 drivers/net/ethernet/ti/tlan.c 	sio = io_base + TLAN_DIO_DATA + TLAN_NET_SIO;
io_base           211 drivers/ntb/test/ntb_tool.c 		u8 __iomem *io_base;
io_base           737 drivers/ntb/test/ntb_tool.c 	if (outmw->io_base == NULL)
io_base           750 drivers/ntb/test/ntb_tool.c 	memcpy_fromio(buf, outmw->io_base + pos, size);
io_base           775 drivers/ntb/test/ntb_tool.c 	if (outmw->io_base == NULL)
io_base           797 drivers/ntb/test/ntb_tool.c 	memcpy_toio(outmw->io_base + pos, buf, size);
io_base           818 drivers/ntb/test/ntb_tool.c 	if (outmw->io_base != NULL)
io_base           829 drivers/ntb/test/ntb_tool.c 	outmw->io_base = ioremap_wc(map_base, map_size);
io_base           830 drivers/ntb/test/ntb_tool.c 	if (outmw->io_base == NULL) {
io_base           858 drivers/ntb/test/ntb_tool.c 	if (outmw->io_base != NULL) {
io_base           859 drivers/ntb/test/ntb_tool.c 		iounmap(tc->outmws[widx].io_base);
io_base           863 drivers/ntb/test/ntb_tool.c 	outmw->io_base = NULL;
io_base           896 drivers/ntb/test/ntb_tool.c 	if (outmw->io_base != NULL) {
io_base           907 drivers/ntb/test/ntb_tool.c 			 "Virtual address     \t0x%pK\n", outmw->io_base);
io_base           347 drivers/pci/controller/dwc/pcie-designware-host.c 					&bridge->windows, &pp->io_base);
io_base           360 drivers/pci/controller/dwc/pcie-designware-host.c 						     pp->io_base);
io_base           562 drivers/pci/controller/dwc/pcie-designware-host.c 					  PCIE_ATU_TYPE_IO, pp->io_base,
io_base           705 drivers/pci/controller/dwc/pcie-designware-host.c 						  PCIE_ATU_TYPE_IO, pp->io_base,
io_base           173 drivers/pci/controller/dwc/pcie-designware.h 	resource_size_t		io_base;
io_base           433 drivers/pci/controller/pci-ftpci100.c 	resource_size_t io_base;
io_base           484 drivers/pci/controller/pci-ftpci100.c 						    &res, &io_base);
io_base           506 drivers/pci/controller/pci-ftpci100.c 			ret = devm_pci_remap_iospace(dev, io, io_base);
io_base           523 drivers/pci/controller/pci-v3-semi.c 				 resource_size_t io_base,
io_base           536 drivers/pci/controller/pci-v3-semi.c 		v3->io_mem = io_base;
io_base           540 drivers/pci/controller/pci-v3-semi.c 		ret = devm_pci_remap_iospace(dev, io, io_base);
io_base           735 drivers/pci/controller/pci-v3-semi.c 	resource_size_t io_base;
io_base           797 drivers/pci/controller/pci-v3-semi.c 						    &io_base);
io_base           856 drivers/pci/controller/pci-v3-semi.c 		ret = v3_pci_setup_resource(v3, io_base, host, win);
io_base           410 drivers/pci/controller/pci-xgene.c 				 resource_size_t io_base)
io_base           424 drivers/pci/controller/pci-xgene.c 			xgene_pcie_setup_ob_reg(port, res, OMR3BARL, io_base,
io_base           426 drivers/pci/controller/pci-xgene.c 			ret = devm_pci_remap_iospace(dev, res, io_base);
io_base           571 drivers/pci/controller/pci-xgene.c 			    resource_size_t io_base)
io_base           583 drivers/pci/controller/pci-xgene.c 	ret = xgene_pcie_map_ranges(port, res, io_base);
io_base          1027 drivers/pci/controller/pcie-mediatek.c 	resource_size_t io_base;
io_base          1031 drivers/pci/controller/pcie-mediatek.c 						    windows, &io_base);
io_base          1043 drivers/pci/controller/pcie-mediatek.c 			err = devm_pci_remap_iospace(dev, win->res, io_base);
io_base           954 drivers/pci/controller/pcie-rockchip-host.c 	resource_size_t io_base;
io_base           999 drivers/pci/controller/pcie-rockchip-host.c 						    &res, &io_base);
io_base          1015 drivers/pci/controller/pcie-rockchip-host.c 			err = pci_remap_iospace(io, io_base);
io_base           201 drivers/pci/hotplug/cpqphp.h 	u16 io_base;
io_base           217 drivers/pci/hotplug/cpqphp.h 	IO_BASE =		offsetof(struct slot_rt, io_base),
io_base          1248 drivers/pci/hotplug/cpqphp_pci.c 		u16 io_base = readw(one_slot + IO_BASE);
io_base          1256 drivers/pci/hotplug/cpqphp_pci.c 		    dev_func, io_base, io_length, mem_base, mem_length, pre_mem_base, pre_mem_length,
io_base          1300 drivers/pci/hotplug/cpqphp_pci.c 		temp_dword = io_base + io_length;
io_base          1302 drivers/pci/hotplug/cpqphp_pci.c 		if ((io_base) && (temp_dword < 0x10000)) {
io_base          1307 drivers/pci/hotplug/cpqphp_pci.c 			io_node->base = io_base;
io_base           550 drivers/pci/hotplug/ibmphp_pci.c 	u8 io_base;
io_base           919 drivers/pci/hotplug/ibmphp_pci.c 		pci_bus_read_config_byte(ibmphp_pci_bus, devfn, PCI_IO_BASE, &io_base);
io_base           922 drivers/pci/hotplug/ibmphp_pci.c 		if ((io_base & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
io_base           260 drivers/pci/of.c 			struct list_head *resources, resource_size_t *io_base)
io_base           270 drivers/pci/of.c 	if (io_base)
io_base           271 drivers/pci/of.c 		*io_base = (resource_size_t)OF_BAD_ADDR;
io_base           328 drivers/pci/of.c 			if (!io_base) {
io_base           334 drivers/pci/of.c 			if (*io_base != (resource_size_t)OF_BAD_ADDR)
io_base           337 drivers/pci/of.c 			*io_base = range.cpu_addr;
io_base           640 drivers/pci/pci.h 			struct list_head *resources, resource_size_t *io_base);
io_base           644 drivers/pci/pci.h 			struct list_head *resources, resource_size_t *io_base)
io_base           370 drivers/pcmcia/bcm63xx_pcmcia.c 	skt->io_base = ioremap(res->start, iomem_size);
io_base           371 drivers/pcmcia/bcm63xx_pcmcia.c 	if (!skt->io_base) {
io_base           382 drivers/pcmcia/bcm63xx_pcmcia.c 	sock->io_offset = (unsigned long)skt->io_base;
io_base           429 drivers/pcmcia/bcm63xx_pcmcia.c 	if (skt->io_base)
io_base           430 drivers/pcmcia/bcm63xx_pcmcia.c 		iounmap(skt->io_base);
io_base           447 drivers/pcmcia/bcm63xx_pcmcia.c 	iounmap(skt->io_base);
io_base            58 drivers/pcmcia/bcm63xx_pcmcia.h 	void __iomem *io_base;
io_base            41 drivers/pcmcia/electra_cf.c 	unsigned int		io_base;
io_base           227 drivers/pcmcia/electra_cf.c 	cf->io_base = (unsigned long)cf->io_virt - VMALLOC_END;
io_base           264 drivers/pcmcia/electra_cf.c 	cf->socket.io_offset = cf->io_base;
io_base           273 drivers/pcmcia/electra_cf.c 	if (!request_region(cf->io_base, cf->io_size, driver_name)) {
io_base           301 drivers/pcmcia/electra_cf.c 	release_region(cf->io_base, cf->io_size);
io_base           337 drivers/pcmcia/electra_cf.c 	release_region(cf->io_base, cf->io_size);
io_base            60 drivers/pcmcia/i82092.c 	unsigned int io_base; 	/* base io address of the socket */
io_base           108 drivers/pcmcia/i82092.c 		sockets[i].io_base = pci_resource_start(dev, 0);
io_base           189 drivers/pcmcia/i82092.c 	port = sockets[socket].io_base;
io_base           204 drivers/pcmcia/i82092.c 	port = sockets[socket].io_base;
io_base           221 drivers/pcmcia/i82092.c 	port = sockets[socket].io_base; 
io_base           234 drivers/pcmcia/i82092.c 	port = sockets[socket].io_base; 
io_base           251 drivers/pcmcia/i82092.c 	port = sockets[socket].io_base; 
io_base           267 drivers/pcmcia/i82092.c 	port = sockets[socket].io_base; 
io_base           367 drivers/pcmcia/i82092.c 	if (sockets[socketno].io_base == 0)
io_base           698 drivers/pcmcia/i82092.c 	if (sockets[0].io_base>0)
io_base           699 drivers/pcmcia/i82092.c 			 release_region(sockets[0].io_base, 2);
io_base            70 drivers/pcmcia/pd6729.c 	port = socket->io_base;
io_base            87 drivers/pcmcia/pd6729.c 	port = socket->io_base;
io_base           106 drivers/pcmcia/pd6729.c 	port = socket->io_base;
io_base           121 drivers/pcmcia/pd6729.c 	port = socket->io_base;
io_base           139 drivers/pcmcia/pd6729.c 	port = socket->io_base;
io_base           157 drivers/pcmcia/pd6729.c 	port = socket->io_base;
io_base           682 drivers/pcmcia/pd6729.c 		socket[i].io_base = pci_resource_start(dev, 0);
io_base            19 drivers/pcmcia/pd6729.h 	unsigned long io_base;	/* base io address of the socket */
io_base           165 drivers/platform/x86/fujitsu-tablet.c 	int io_base;
io_base           171 drivers/platform/x86/fujitsu-tablet.c 	return inb(fujitsu.io_base + 2);
io_base           176 drivers/platform/x86/fujitsu-tablet.c 	return inb(fujitsu.io_base + 6);
io_base           181 drivers/platform/x86/fujitsu-tablet.c 	outb(addr, fujitsu.io_base);
io_base           182 drivers/platform/x86/fujitsu-tablet.c 	return inb(fujitsu.io_base + 4);
io_base           430 drivers/platform/x86/fujitsu-tablet.c 		fujitsu.io_base = res->data.io.minimum;
io_base           435 drivers/platform/x86/fujitsu-tablet.c 		if (fujitsu.irq && fujitsu.io_base)
io_base           455 drivers/platform/x86/fujitsu-tablet.c 	if (ACPI_FAILURE(status) || !fujitsu.irq || !fujitsu.io_base)
io_base           469 drivers/platform/x86/fujitsu-tablet.c 	if (!request_region(fujitsu.io_base, fujitsu.io_length, MODULENAME)) {
io_base           479 drivers/platform/x86/fujitsu-tablet.c 		release_region(fujitsu.io_base, fujitsu.io_length);
io_base           490 drivers/platform/x86/fujitsu-tablet.c 	release_region(fujitsu.io_base, fujitsu.io_length);
io_base           118 drivers/scsi/arm/arxescsi.c 	void __iomem *base = info->info.scsi.io_base;
io_base           280 drivers/scsi/arm/arxescsi.c 	info->info.scsi.io_base		= base + 0x2000;
io_base           403 drivers/scsi/arm/cumana_2.c 	info->info.scsi.io_base		= base + CUMANASCSI2_FAS216_OFFSET;
io_base           522 drivers/scsi/arm/eesox.c 	info->info.scsi.io_base		= base + EESOX_FAS216_OFFSET;
io_base           144 drivers/scsi/arm/fas216.c 	return readb(info->scsi.io_base + off);
io_base           150 drivers/scsi/arm/fas216.c 	writeb(val, info->scsi.io_base + off);
io_base          2968 drivers/scsi/arm/fas216.c 			info->scsi.type, info->scsi.io_base,
io_base           234 drivers/scsi/arm/fas216.h 		void __iomem	*io_base;		/* iomem base of FAS216			*/
io_base           329 drivers/scsi/arm/powertec.c 	info->info.scsi.io_base		= base + POWERTEC_FAS216_OFFSET;
io_base           165 drivers/scsi/myrb.c 	void __iomem *base = cb->io_base;
io_base           810 drivers/scsi/myrb.c 	void __iomem *base = cb->io_base;
io_base          1244 drivers/scsi/myrb.c 		cb->disable_intr(cb->io_base);
io_base          1261 drivers/scsi/myrb.c 	cb->reset(cb->io_base);
io_base          2772 drivers/scsi/myrb.c 	void __iomem *base = cb->io_base;
io_base          3050 drivers/scsi/myrb.c 	void __iomem *base = cb->io_base;
io_base          3204 drivers/scsi/myrb.c 	void __iomem *base = cb->io_base;
io_base          3258 drivers/scsi/myrb.c 	void __iomem *base = cb->io_base;
io_base          3343 drivers/scsi/myrb.c 	void __iomem *base = cb->io_base;
io_base          3424 drivers/scsi/myrb.c 	void __iomem *base = cb->io_base;
io_base          3541 drivers/scsi/myrb.c 	cb->io_base = cb->mmio_base + (cb->pci_addr & ~PAGE_MASK);
io_base          3542 drivers/scsi/myrb.c 	if (privdata->hw_init(pdev, cb, cb->io_base))
io_base           739 drivers/scsi/myrb.h 	void __iomem *io_base;
io_base           106 drivers/scsi/myrs.c 	void __iomem *base = cs->io_base;
io_base           485 drivers/scsi/myrs.c 	void __iomem *base = cs->io_base;
io_base          1537 drivers/scsi/myrs.c 	cs->reset(cs->io_base);
io_base          2321 drivers/scsi/myrs.c 	cs->io_base = cs->mmio_base + (cs->pci_addr & ~PAGE_MASK);
io_base          2322 drivers/scsi/myrs.c 	if (privdata->hw_init(pdev, cs, cs->io_base))
io_base          2617 drivers/scsi/myrs.c 	void __iomem *base = cs->io_base;
io_base          2867 drivers/scsi/myrs.c 	void __iomem *base = cs->io_base;
io_base          3117 drivers/scsi/myrs.c 	void __iomem *base = cs->io_base;
io_base           888 drivers/scsi/myrs.h 	void __iomem *io_base;
io_base           101 drivers/spi/spi-stm32-qspi.c 	void __iomem *io_base;
io_base           129 drivers/spi/spi-stm32-qspi.c 	sr = readl_relaxed(qspi->io_base + QSPI_SR);
io_base           133 drivers/spi/spi-stm32-qspi.c 		cr = readl_relaxed(qspi->io_base + QSPI_CR);
io_base           135 drivers/spi/spi-stm32-qspi.c 		writel_relaxed(cr, qspi->io_base + QSPI_CR);
io_base           170 drivers/spi/spi-stm32-qspi.c 		ret = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR,
io_base           178 drivers/spi/spi-stm32-qspi.c 		tx_fifo(buf++, qspi->io_base + QSPI_DR);
io_base           233 drivers/spi/spi-stm32-qspi.c 	cr = readl_relaxed(qspi->io_base + QSPI_CR);
io_base           245 drivers/spi/spi-stm32-qspi.c 	writel_relaxed(cr | CR_DMAEN, qspi->io_base + QSPI_CR);
io_base           256 drivers/spi/spi-stm32-qspi.c 	writel_relaxed(cr & ~CR_DMAEN, qspi->io_base + QSPI_CR);
io_base           282 drivers/spi/spi-stm32-qspi.c 	return readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR, sr,
io_base           296 drivers/spi/spi-stm32-qspi.c 	if (readl_relaxed(qspi->io_base + QSPI_SR) & SR_TCF)
io_base           300 drivers/spi/spi-stm32-qspi.c 	cr = readl_relaxed(qspi->io_base + QSPI_CR);
io_base           301 drivers/spi/spi-stm32-qspi.c 	writel_relaxed(cr | CR_TCIE | CR_TEIE, qspi->io_base + QSPI_CR);
io_base           307 drivers/spi/spi-stm32-qspi.c 		sr = readl_relaxed(qspi->io_base + QSPI_SR);
io_base           314 drivers/spi/spi-stm32-qspi.c 	writel_relaxed(FCR_CTCF | FCR_CTEF, qspi->io_base + QSPI_FCR);
io_base           355 drivers/spi/spi-stm32-qspi.c 	cr = readl_relaxed(qspi->io_base + QSPI_CR);
io_base           359 drivers/spi/spi-stm32-qspi.c 	writel_relaxed(cr, qspi->io_base + QSPI_CR);
io_base           363 drivers/spi/spi-stm32-qspi.c 			       qspi->io_base + QSPI_DLR);
io_base           387 drivers/spi/spi-stm32-qspi.c 	writel_relaxed(ccr, qspi->io_base + QSPI_CCR);
io_base           390 drivers/spi/spi-stm32-qspi.c 		writel_relaxed(op->addr.val, qspi->io_base + QSPI_AR);
io_base           412 drivers/spi/spi-stm32-qspi.c 	cr = readl_relaxed(qspi->io_base + QSPI_CR) | CR_ABORT;
io_base           413 drivers/spi/spi-stm32-qspi.c 	writel_relaxed(cr, qspi->io_base + QSPI_CR);
io_base           416 drivers/spi/spi-stm32-qspi.c 	timeout = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_CR,
io_base           420 drivers/spi/spi-stm32-qspi.c 	writel_relaxed(FCR_CTCF, qspi->io_base + QSPI_FCR);
io_base           463 drivers/spi/spi-stm32-qspi.c 	writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR);
io_base           467 drivers/spi/spi-stm32-qspi.c 	writel_relaxed(qspi->dcr_reg, qspi->io_base + QSPI_DCR);
io_base           527 drivers/spi/spi-stm32-qspi.c 	writel_relaxed(0, qspi->io_base + QSPI_CR);
io_base           550 drivers/spi/spi-stm32-qspi.c 	qspi->io_base = devm_ioremap_resource(dev, res);
io_base           551 drivers/spi/spi-stm32-qspi.c 	if (IS_ERR(qspi->io_base)) {
io_base           552 drivers/spi/spi-stm32-qspi.c 		ret = PTR_ERR(qspi->io_base);
io_base           658 drivers/spi/spi-stm32-qspi.c 	writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR);
io_base           659 drivers/spi/spi-stm32-qspi.c 	writel_relaxed(qspi->dcr_reg, qspi->io_base + QSPI_DCR);
io_base           117 drivers/staging/comedi/drivers/adl_pci9111.c static void plx9050_interrupt_control(unsigned long io_base,
io_base           138 drivers/staging/comedi/drivers/adl_pci9111.c 	outb(flags, io_base + PLX9052_INTCSR);
io_base            91 drivers/staging/most/dim2/dim2.c 	void __iomem *io_base;
io_base           759 drivers/staging/most/dim2/dim2.c 	dev->io_base = devm_ioremap_resource(&pdev->dev, res);
io_base           760 drivers/staging/most/dim2/dim2.c 	if (IS_ERR(dev->io_base))
io_base           761 drivers/staging/most/dim2/dim2.c 		return PTR_ERR(dev->io_base);
io_base           772 drivers/staging/most/dim2/dim2.c 	hal_ret = dim_startup(dev->io_base, dev->clk_speed, fcnt);
io_base           940 drivers/staging/most/dim2/dim2.c 		writel(0x888, dev->io_base + 0x38);
io_base           976 drivers/staging/most/dim2/dim2.c 		writel(0x03, dev->io_base + 0x600);
io_base           978 drivers/staging/most/dim2/dim2.c 		writel(0x888, dev->io_base + 0x38);
io_base           981 drivers/staging/most/dim2/dim2.c 		writel(0x04, dev->io_base + 0x600);
io_base           986 drivers/staging/most/dim2/dim2.c 	writel(0x03, dev->io_base + 0x500);
io_base           987 drivers/staging/most/dim2/dim2.c 	writel(0x0002FF02, dev->io_base + 0x508);
io_base           999 drivers/staging/most/dim2/dim2.c 	writel(0x0, dev->io_base + 0x600);
io_base          1021 drivers/staging/most/dim2/dim2.c 	writel(0x04, dev->io_base + 0x600);
io_base          1023 drivers/staging/most/dim2/dim2.c 	writel(enable_512fs, dev->io_base + 0x604);
io_base          1026 drivers/staging/most/dim2/dim2.c 	writel(0x03, dev->io_base + 0x500);
io_base          1027 drivers/staging/most/dim2/dim2.c 	writel(0x0002FF02, dev->io_base + 0x508);
io_base          1039 drivers/staging/most/dim2/dim2.c 	writel(0x0, dev->io_base + 0x600);
io_base            62 drivers/staging/vt6655/mac.c 	void __iomem *io_base = priv->PortOffset;
io_base            64 drivers/staging/vt6655/mac.c 	return !(ioread8(io_base + byRegOfs) & byTestBits);
io_base            82 drivers/staging/vt6655/mac.c 	void __iomem *io_base = priv->PortOffset;
io_base            84 drivers/staging/vt6655/mac.c 	if (ioread32(io_base + MAC_REG_IMR))
io_base           107 drivers/staging/vt6655/mac.c 	void __iomem *io_base = priv->PortOffset;
io_base           109 drivers/staging/vt6655/mac.c 	iowrite8(byRetryLimit, io_base + MAC_REG_SRT);
io_base           129 drivers/staging/vt6655/mac.c 	void __iomem *io_base = priv->PortOffset;
io_base           131 drivers/staging/vt6655/mac.c 	iowrite8(byRetryLimit, io_base + MAC_REG_LRT);
io_base           150 drivers/staging/vt6655/mac.c 	void __iomem *io_base = priv->PortOffset;
io_base           154 drivers/staging/vt6655/mac.c 	iowrite8((ioread8(io_base + MAC_REG_TEST) & 0x3f) | byLoopbackMode,
io_base           155 drivers/staging/vt6655/mac.c 		 io_base + MAC_REG_TEST);
io_base           173 drivers/staging/vt6655/mac.c 	void __iomem *io_base = priv->PortOffset;
io_base           176 drivers/staging/vt6655/mac.c 	memcpy_fromio(cxt_buf, io_base, MAC_MAX_CONTEXT_SIZE_PAGE0);
io_base           178 drivers/staging/vt6655/mac.c 	MACvSelectPage1(io_base);
io_base           181 drivers/staging/vt6655/mac.c 	memcpy_fromio(cxt_buf + MAC_MAX_CONTEXT_SIZE_PAGE0, io_base,
io_base           184 drivers/staging/vt6655/mac.c 	MACvSelectPage0(io_base);
io_base           203 drivers/staging/vt6655/mac.c 	void __iomem *io_base = priv->PortOffset;
io_base           205 drivers/staging/vt6655/mac.c 	MACvSelectPage1(io_base);
io_base           207 drivers/staging/vt6655/mac.c 	memcpy_toio(io_base, cxt_buf + MAC_MAX_CONTEXT_SIZE_PAGE0,
io_base           210 drivers/staging/vt6655/mac.c 	MACvSelectPage0(io_base);
io_base           213 drivers/staging/vt6655/mac.c 	memcpy_toio(io_base + MAC_REG_RCR, cxt_buf + MAC_REG_RCR,
io_base           217 drivers/staging/vt6655/mac.c 	memcpy_toio(io_base + MAC_REG_LRT, cxt_buf + MAC_REG_LRT,
io_base           220 drivers/staging/vt6655/mac.c 	iowrite8(*(cxt_buf + MAC_REG_CFG), io_base + MAC_REG_CFG);
io_base           223 drivers/staging/vt6655/mac.c 	memcpy_toio(io_base + MAC_REG_PSCFG, cxt_buf + MAC_REG_PSCFG,
io_base           228 drivers/staging/vt6655/mac.c 		  io_base + MAC_REG_TXDMAPTR0);
io_base           230 drivers/staging/vt6655/mac.c 		  io_base + MAC_REG_AC0DMAPTR);
io_base           232 drivers/staging/vt6655/mac.c 		  io_base + MAC_REG_BCNDMAPTR);
io_base           234 drivers/staging/vt6655/mac.c 		  io_base + MAC_REG_RXDMAPTR0);
io_base           236 drivers/staging/vt6655/mac.c 		  io_base + MAC_REG_RXDMAPTR1);
io_base           254 drivers/staging/vt6655/mac.c 	void __iomem *io_base = priv->PortOffset;
io_base           258 drivers/staging/vt6655/mac.c 	iowrite8(0x01, io_base + MAC_REG_HOSTCR);
io_base           261 drivers/staging/vt6655/mac.c 		if (!(ioread8(io_base + MAC_REG_HOSTCR) & HOSTCR_SOFTRST))
io_base           317 drivers/staging/vt6655/mac.c 	void __iomem *io_base = priv->PortOffset;
io_base           323 drivers/staging/vt6655/mac.c 	iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_RXDMACTL0);
io_base           324 drivers/staging/vt6655/mac.c 	iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_RXDMACTL1);
io_base           326 drivers/staging/vt6655/mac.c 		if (!(ioread32(io_base + MAC_REG_RXDMACTL0) & DMACTL_RUN))
io_base           334 drivers/staging/vt6655/mac.c 		if (!(ioread32(io_base + MAC_REG_RXDMACTL1) & DMACTL_RUN))
io_base           343 drivers/staging/vt6655/mac.c 	MACvRegBitsOff(io_base, MAC_REG_HOSTCR, HOSTCR_RXON);
io_base           346 drivers/staging/vt6655/mac.c 		if (!(ioread8(io_base + MAC_REG_HOSTCR) & HOSTCR_RXONST))
io_base           371 drivers/staging/vt6655/mac.c 	void __iomem *io_base = priv->PortOffset;
io_base           376 drivers/staging/vt6655/mac.c 	iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_TXDMACTL0);
io_base           378 drivers/staging/vt6655/mac.c 	iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_AC0DMACTL);
io_base           381 drivers/staging/vt6655/mac.c 		if (!(ioread32(io_base + MAC_REG_TXDMACTL0) & DMACTL_RUN))
io_base           389 drivers/staging/vt6655/mac.c 		if (!(ioread32(io_base + MAC_REG_AC0DMACTL) & DMACTL_RUN))
io_base           398 drivers/staging/vt6655/mac.c 	MACvRegBitsOff(io_base, MAC_REG_HOSTCR, HOSTCR_TXON);
io_base           402 drivers/staging/vt6655/mac.c 		if (!(ioread8(io_base + MAC_REG_HOSTCR) & HOSTCR_TXONST))
io_base           427 drivers/staging/vt6655/mac.c 	void __iomem *io_base = priv->PortOffset;
io_base           429 drivers/staging/vt6655/mac.c 	MACvRegBitsOff(io_base, MAC_REG_TCR, TCR_AUTOBCNTX);
io_base           442 drivers/staging/vt6655/mac.c 	MACvRegBitsOff(io_base, MAC_REG_HOSTCR, HOSTCR_MACEN);
io_base           462 drivers/staging/vt6655/mac.c 	void __iomem *io_base = priv->PortOffset;
io_base           464 drivers/staging/vt6655/mac.c 	MACvIntDisable(io_base);
io_base           490 drivers/staging/vt6655/mac.c 	void __iomem *io_base = priv->PortOffset;
io_base           492 drivers/staging/vt6655/mac.c 	MACvClearStckDS(io_base);
io_base           494 drivers/staging/vt6655/mac.c 	iowrite8(PME_OVR, io_base + MAC_REG_PMC1);
io_base           501 drivers/staging/vt6655/mac.c 	iowrite8(TFTCTL_TSFCNTRST, io_base + MAC_REG_TFTCTL);
io_base           503 drivers/staging/vt6655/mac.c 	iowrite8(TFTCTL_TSFCNTREN, io_base + MAC_REG_TFTCTL);
io_base           522 drivers/staging/vt6655/mac.c 	void __iomem *io_base = priv->PortOffset;
io_base           526 drivers/staging/vt6655/mac.c 	org_dma_ctl = ioread8(io_base + MAC_REG_RXDMACTL0);
io_base           528 drivers/staging/vt6655/mac.c 		iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL0 + 2);
io_base           531 drivers/staging/vt6655/mac.c 		if (!(ioread8(io_base + MAC_REG_RXDMACTL0) & DMACTL_RUN))
io_base           535 drivers/staging/vt6655/mac.c 	iowrite32(curr_desc_addr, io_base + MAC_REG_RXDMAPTR0);
io_base           537 drivers/staging/vt6655/mac.c 		iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL0);
io_base           556 drivers/staging/vt6655/mac.c 	void __iomem *io_base = priv->PortOffset;
io_base           560 drivers/staging/vt6655/mac.c 	org_dma_ctl = ioread8(io_base + MAC_REG_RXDMACTL1);
io_base           562 drivers/staging/vt6655/mac.c 		iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL1 + 2);
io_base           565 drivers/staging/vt6655/mac.c 		if (!(ioread8(io_base + MAC_REG_RXDMACTL1) & DMACTL_RUN))
io_base           569 drivers/staging/vt6655/mac.c 	iowrite32(curr_desc_addr, io_base + MAC_REG_RXDMAPTR1);
io_base           571 drivers/staging/vt6655/mac.c 		iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL1);
io_base           591 drivers/staging/vt6655/mac.c 	void __iomem *io_base = priv->PortOffset;
io_base           595 drivers/staging/vt6655/mac.c 	org_dma_ctl = ioread8(io_base + MAC_REG_TXDMACTL0);
io_base           597 drivers/staging/vt6655/mac.c 		iowrite8(DMACTL_RUN, io_base + MAC_REG_TXDMACTL0 + 2);
io_base           600 drivers/staging/vt6655/mac.c 		if (!(ioread8(io_base + MAC_REG_TXDMACTL0) & DMACTL_RUN))
io_base           604 drivers/staging/vt6655/mac.c 	iowrite32(curr_desc_addr, io_base + MAC_REG_TXDMAPTR0);
io_base           606 drivers/staging/vt6655/mac.c 		iowrite8(DMACTL_RUN, io_base + MAC_REG_TXDMACTL0);
io_base           627 drivers/staging/vt6655/mac.c 	void __iomem *io_base = priv->PortOffset;
io_base           631 drivers/staging/vt6655/mac.c 	org_dma_ctl = ioread8(io_base + MAC_REG_AC0DMACTL);
io_base           633 drivers/staging/vt6655/mac.c 		iowrite8(DMACTL_RUN, io_base + MAC_REG_AC0DMACTL + 2);
io_base           636 drivers/staging/vt6655/mac.c 		if (!(ioread8(io_base + MAC_REG_AC0DMACTL) & DMACTL_RUN))
io_base           641 drivers/staging/vt6655/mac.c 	iowrite32(curr_desc_addr, io_base + MAC_REG_AC0DMAPTR);
io_base           643 drivers/staging/vt6655/mac.c 		iowrite8(DMACTL_RUN, io_base + MAC_REG_AC0DMACTL);
io_base           671 drivers/staging/vt6655/mac.c 	void __iomem *io_base = priv->PortOffset;
io_base           675 drivers/staging/vt6655/mac.c 	iowrite8(0, io_base + MAC_REG_TMCTL0);
io_base           676 drivers/staging/vt6655/mac.c 	iowrite32(uDelay, io_base + MAC_REG_TMDATA0);
io_base           677 drivers/staging/vt6655/mac.c 	iowrite8((TMCTL_TMD | TMCTL_TE), io_base + MAC_REG_TMCTL0);
io_base           680 drivers/staging/vt6655/mac.c 			byValue = ioread8(io_base + MAC_REG_TMCTL0);
io_base           683 drivers/staging/vt6655/mac.c 				iowrite8(0, io_base + MAC_REG_TMCTL0);
io_base           688 drivers/staging/vt6655/mac.c 	iowrite8(0, io_base + MAC_REG_TMCTL0);
io_base           708 drivers/staging/vt6655/mac.c 	void __iomem *io_base = priv->PortOffset;
io_base           710 drivers/staging/vt6655/mac.c 	iowrite8(0, io_base + MAC_REG_TMCTL1);
io_base           711 drivers/staging/vt6655/mac.c 	iowrite32(uDelayTime, io_base + MAC_REG_TMDATA1);
io_base           712 drivers/staging/vt6655/mac.c 	iowrite8((TMCTL_TMD | TMCTL_TE), io_base + MAC_REG_TMCTL1);
io_base           718 drivers/staging/vt6655/mac.c 	void __iomem *io_base = priv->PortOffset;
io_base           722 drivers/staging/vt6655/mac.c 	iowrite16(offset, io_base + MAC_REG_MISCFFNDEX);
io_base           723 drivers/staging/vt6655/mac.c 	iowrite32(data, io_base + MAC_REG_MISCFFDATA);
io_base           724 drivers/staging/vt6655/mac.c 	iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
io_base           729 drivers/staging/vt6655/mac.c 	void __iomem *io_base = priv->PortOffset;
io_base           736 drivers/staging/vt6655/mac.c 	MACvRegBitsOff(io_base, MAC_REG_PSCTL, PSCTL_PSEN);
io_base           740 drivers/staging/vt6655/mac.c 		if (ioread8(io_base + MAC_REG_PSCTL) & PSCTL_WAKEDONE)
io_base           770 drivers/staging/vt6655/mac.c 	void __iomem *io_base = priv->PortOffset;
io_base           789 drivers/staging/vt6655/mac.c 	iowrite16(offset, io_base + MAC_REG_MISCFFNDEX);
io_base           790 drivers/staging/vt6655/mac.c 	iowrite32(data, io_base + MAC_REG_MISCFFDATA);
io_base           791 drivers/staging/vt6655/mac.c 	iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
io_base           804 drivers/staging/vt6655/mac.c 	iowrite16(offset, io_base + MAC_REG_MISCFFNDEX);
io_base           805 drivers/staging/vt6655/mac.c 	iowrite32(data, io_base + MAC_REG_MISCFFDATA);
io_base           806 drivers/staging/vt6655/mac.c 	iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
io_base           814 drivers/staging/vt6655/mac.c 		iowrite16(offset + ii, io_base + MAC_REG_MISCFFNDEX);
io_base           815 drivers/staging/vt6655/mac.c 		iowrite32(*pdwKey++, io_base + MAC_REG_MISCFFDATA);
io_base           816 drivers/staging/vt6655/mac.c 		iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
io_base           836 drivers/staging/vt6655/mac.c 	void __iomem *io_base = priv->PortOffset;
io_base           842 drivers/staging/vt6655/mac.c 	iowrite16(offset, io_base + MAC_REG_MISCFFNDEX);
io_base           843 drivers/staging/vt6655/mac.c 	iowrite32(0, io_base + MAC_REG_MISCFFDATA);
io_base           844 drivers/staging/vt6655/mac.c 	iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
io_base           259 drivers/tty/synclink.c 	unsigned int io_base;		/* base I/O address of adapter */
io_base          1458 drivers/tty/synclink.c 		outw( (inw(info->io_base + CCAR) & 0x0780) | (RDR+LSBONLY),
io_base          1459 drivers/tty/synclink.c 		      info->io_base + CCAR );
io_base          1460 drivers/tty/synclink.c 		DataByte = inb( info->io_base + CCAR );
io_base          3437 drivers/tty/synclink.c 			info->device_name, info->io_base, info->irq_level,
io_base          3441 drivers/tty/synclink.c 			info->device_name, info->io_base, 
io_base          3513 drivers/tty/synclink.c 	u16 Ccar = inw( info->io_base + CCAR );
io_base          4028 drivers/tty/synclink.c 	if (request_region(info->io_base,info->io_addr_size,"synclink") == NULL) {
io_base          4030 drivers/tty/synclink.c 			__FILE__,__LINE__,info->device_name, info->io_base);
io_base          4128 drivers/tty/synclink.c 		release_region(info->io_base,info->io_addr_size);
io_base          4205 drivers/tty/synclink.c 			info->hw_version + 1, info->device_name, info->io_base, info->irq_level,
io_base          4210 drivers/tty/synclink.c 			info->device_name, info->io_base, info->irq_level, info->dma_level,
io_base          4420 drivers/tty/synclink.c 	outw( Cmd + info->loopback_bits, info->io_base + CCAR );
io_base          4424 drivers/tty/synclink.c 		inw( info->io_base + CCAR );
io_base          4445 drivers/tty/synclink.c 	outw( Cmd + info->mbre_bit, info->io_base );
io_base          4449 drivers/tty/synclink.c 		inw( info->io_base );
io_base          4474 drivers/tty/synclink.c 	outw( RegAddr + info->mbre_bit, info->io_base );
io_base          4475 drivers/tty/synclink.c 	outw( RegValue, info->io_base );
io_base          4479 drivers/tty/synclink.c 		inw( info->io_base );
io_base          4503 drivers/tty/synclink.c 	outw( RegAddr + info->mbre_bit, info->io_base );
io_base          4504 drivers/tty/synclink.c 	return inw( info->io_base );
io_base          4527 drivers/tty/synclink.c 	outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
io_base          4528 drivers/tty/synclink.c 	outw( RegValue, info->io_base + CCAR );
io_base          4532 drivers/tty/synclink.c 		inw( info->io_base + CCAR );
io_base          4552 drivers/tty/synclink.c 	outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
io_base          4553 drivers/tty/synclink.c 	return inw( info->io_base + CCAR );
io_base          4987 drivers/tty/synclink.c 	outw( 0, info->io_base ); 			/* clear Master Bus Enable (DCAR) */
io_base          4990 drivers/tty/synclink.c 	outw( BIT8, info->io_base );			/* set Master Bus Enable (DCAR) */
io_base          5174 drivers/tty/synclink.c 		outw( 0x0300, info->io_base + CCAR );
io_base          5181 drivers/tty/synclink.c 		outw( 0,info->io_base + CCAR );
io_base          5651 drivers/tty/synclink.c 			outw( *((u16 *)TwoBytes), info->io_base + DATAREG);
io_base          5658 drivers/tty/synclink.c 			outw( (inw( info->io_base + CCAR) & 0x0780) | (TDR+LSBONLY),
io_base          5659 drivers/tty/synclink.c 				info->io_base + CCAR );
io_base          5663 drivers/tty/synclink.c 				outw( info->x_char,info->io_base + CCAR );
io_base          5666 drivers/tty/synclink.c 				outw( info->xmit_buf[info->xmit_tail++],info->io_base + CCAR );
io_base          5721 drivers/tty/synclink.c 		outb( 0,info->io_base + 8 );
io_base          5745 drivers/tty/synclink.c 	outw( 0x000c,info->io_base + SDPIN );
io_base          5748 drivers/tty/synclink.c 	outw( 0,info->io_base );
io_base          5749 drivers/tty/synclink.c 	outw( 0,info->io_base + CCAR );
io_base          5804 drivers/tty/synclink.c 	outw( 0, info->io_base ); 			/* clear Master Bus Enable (DCAR) */
io_base          5970 drivers/tty/synclink.c 		outw(0x0300, info->io_base + CCAR);
io_base          6032 drivers/tty/synclink.c 	outw(0,info->io_base + DATAREG);
io_base          7276 drivers/tty/synclink.c 			__FILE__,__LINE__,info->device_name, (unsigned short)(info->io_base) );
io_base          7934 drivers/tty/synclink.c 	dev->base_addr = info->io_base;
io_base          7994 drivers/tty/synclink.c 	info->io_base = pci_resource_start(dev, 2);
io_base            40 drivers/watchdog/ni903x_wdt.c 	u16 io_base;
io_base            58 drivers/watchdog/ni903x_wdt.c 	u8 control = inb(wdt->io_base + NIWD_CONTROL);
io_base            60 drivers/watchdog/ni903x_wdt.c 	outb(control | NIWD_CONTROL_RESET, wdt->io_base + NIWD_CONTROL);
io_base            61 drivers/watchdog/ni903x_wdt.c 	outb(control | NIWD_CONTROL_PET, wdt->io_base + NIWD_CONTROL);
io_base            70 drivers/watchdog/ni903x_wdt.c 	outb(((0x00FF0000 & counter) >> 16), wdt->io_base + NIWD_SEED2);
io_base            71 drivers/watchdog/ni903x_wdt.c 	outb(((0x0000FF00 & counter) >> 8), wdt->io_base + NIWD_SEED1);
io_base            72 drivers/watchdog/ni903x_wdt.c 	outb((0x000000FF & counter), wdt->io_base + NIWD_SEED0);
io_base            85 drivers/watchdog/ni903x_wdt.c 	control = inb(wdt->io_base + NIWD_CONTROL);
io_base            87 drivers/watchdog/ni903x_wdt.c 	outb(control, wdt->io_base + NIWD_CONTROL);
io_base            89 drivers/watchdog/ni903x_wdt.c 	counter2 = inb(wdt->io_base + NIWD_COUNTER2);
io_base            90 drivers/watchdog/ni903x_wdt.c 	counter1 = inb(wdt->io_base + NIWD_COUNTER1);
io_base            91 drivers/watchdog/ni903x_wdt.c 	counter0 = inb(wdt->io_base + NIWD_COUNTER0);
io_base           103 drivers/watchdog/ni903x_wdt.c 	control = inb(wdt->io_base + NIWD_CONTROL);
io_base           104 drivers/watchdog/ni903x_wdt.c 	outb(control | NIWD_CONTROL_PET, wdt->io_base + NIWD_CONTROL);
io_base           114 drivers/watchdog/ni903x_wdt.c 	     wdt->io_base + NIWD_CONTROL);
io_base           126 drivers/watchdog/ni903x_wdt.c 	outb(NIWD_CONTROL_RESET, wdt->io_base + NIWD_CONTROL);
io_base           138 drivers/watchdog/ni903x_wdt.c 		if (wdt->io_base != 0) {
io_base           143 drivers/watchdog/ni903x_wdt.c 		wdt->io_base = res->data.io.minimum;
io_base           151 drivers/watchdog/ni903x_wdt.c 		if (!devm_request_region(wdt->dev, wdt->io_base, io_size,
io_base           197 drivers/watchdog/ni903x_wdt.c 	if (ACPI_FAILURE(status) || wdt->io_base == 0) {
io_base           219 drivers/watchdog/ni903x_wdt.c 	     wdt->io_base + NIWD_CONTROL);
io_base           222 drivers/watchdog/ni903x_wdt.c 		wdt->io_base, timeout, nowayout);
io_base            46 drivers/watchdog/nic7018_wdt.c 	u16 io_base;
io_base            96 drivers/watchdog/nic7018_wdt.c 	     wdt->io_base + WDT_PRESET_PRESCALE);
io_base           111 drivers/watchdog/nic7018_wdt.c 	control = inb(wdt->io_base + WDT_RELOAD_CTRL);
io_base           112 drivers/watchdog/nic7018_wdt.c 	outb(control | WDT_RELOAD_PORT_EN, wdt->io_base + WDT_RELOAD_CTRL);
io_base           114 drivers/watchdog/nic7018_wdt.c 	outb(1, wdt->io_base + WDT_RELOAD_PORT);
io_base           116 drivers/watchdog/nic7018_wdt.c 	control = inb(wdt->io_base + WDT_CTRL);
io_base           117 drivers/watchdog/nic7018_wdt.c 	outb(control | WDT_CTRL_RESET_EN, wdt->io_base + WDT_CTRL);
io_base           126 drivers/watchdog/nic7018_wdt.c 	outb(0, wdt->io_base + WDT_CTRL);
io_base           127 drivers/watchdog/nic7018_wdt.c 	outb(0, wdt->io_base + WDT_RELOAD_CTRL);
io_base           128 drivers/watchdog/nic7018_wdt.c 	outb(0xF0, wdt->io_base + WDT_PRESET_PRESCALE);
io_base           137 drivers/watchdog/nic7018_wdt.c 	outb(1, wdt->io_base + WDT_RELOAD_PORT);
io_base           147 drivers/watchdog/nic7018_wdt.c 	count = inb(wdt->io_base + WDT_COUNT) & 0xF;
io_base           194 drivers/watchdog/nic7018_wdt.c 	wdt->io_base = io_rc->start;
io_base           208 drivers/watchdog/nic7018_wdt.c 	outb(UNLOCK, wdt->io_base + WDT_REG_LOCK);
io_base           212 drivers/watchdog/nic7018_wdt.c 		outb(LOCK, wdt->io_base + WDT_REG_LOCK);
io_base           217 drivers/watchdog/nic7018_wdt.c 		wdt->io_base, timeout, nowayout);
io_base           228 drivers/watchdog/nic7018_wdt.c 	outb(LOCK, wdt->io_base + WDT_REG_LOCK);
io_base            29 drivers/watchdog/tqmx86_wdt.c 	void __iomem *io_base;
io_base            39 drivers/watchdog/tqmx86_wdt.c 	iowrite8(0x81, priv->io_base + TQMX86_WDCS);
io_base            52 drivers/watchdog/tqmx86_wdt.c 	iowrite8(val, priv->io_base + TQMX86_WDCFG);
io_base            86 drivers/watchdog/tqmx86_wdt.c 	priv->io_base = devm_ioport_map(dev, res->start, resource_size(res));
io_base            87 drivers/watchdog/tqmx86_wdt.c 	if (!priv->io_base)
io_base           101 include/clocksource/timer-ti-dm.h 	void __iomem	*io_base;
io_base           280 include/clocksource/timer-ti-dm.h 	tidr = readl_relaxed(timer->io_base);
io_base           283 include/clocksource/timer-ti-dm.h 		timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET;
io_base           284 include/clocksource/timer-ti-dm.h 		timer->irq_ena = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
io_base           285 include/clocksource/timer-ti-dm.h 		timer->irq_dis = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
io_base           286 include/clocksource/timer-ti-dm.h 		timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET;
io_base           287 include/clocksource/timer-ti-dm.h 		timer->func_base = timer->io_base;
io_base           290 include/clocksource/timer-ti-dm.h 		timer->irq_stat = timer->io_base + OMAP_TIMER_V2_IRQSTATUS;
io_base           291 include/clocksource/timer-ti-dm.h 		timer->irq_ena = timer->io_base + OMAP_TIMER_V2_IRQENABLE_SET;
io_base           292 include/clocksource/timer-ti-dm.h 		timer->irq_dis = timer->io_base + OMAP_TIMER_V2_IRQENABLE_CLR;
io_base           293 include/clocksource/timer-ti-dm.h 		timer->pend = timer->io_base +
io_base           296 include/clocksource/timer-ti-dm.h 		timer->func_base = timer->io_base + OMAP_TIMER_V2_FUNC_OFFSET;
io_base            87 include/linux/mfd/kempld.h 	void __iomem		*io_base;
io_base           318 sound/drivers/serial-u16550.c 	unsigned long io_base = uart->base;
io_base           323 sound/drivers/serial-u16550.c 	if (io_base == 0 || io_base == SNDRV_AUTO_PORT) {
io_base           327 sound/drivers/serial-u16550.c 	uart->res_base = request_region(io_base, 8, "Serial MIDI");
io_base           329 sound/drivers/serial-u16550.c 		snd_printk(KERN_ERR "u16550: can't grab port 0x%lx\n", io_base);
io_base           336 sound/drivers/serial-u16550.c 	outb(UART_LCR_WLEN8, io_base + UART_LCR); /* Line Control Register */
io_base           337 sound/drivers/serial-u16550.c 	c = inb(io_base + UART_IER);
io_base           342 sound/drivers/serial-u16550.c 	outb(0xaa, io_base + UART_SCR);
io_base           344 sound/drivers/serial-u16550.c 	c = inb(io_base + UART_SCR);
io_base           349 sound/drivers/serial-u16550.c 	outb(0x55, io_base + UART_SCR);
io_base           351 sound/drivers/serial-u16550.c 	c = inb(io_base + UART_SCR);
io_base           133 sound/isa/sscape.c 	unsigned io_base;
io_base           188 sound/isa/sscape.c static inline void sscape_write_unsafe(unsigned io_base, enum GA_REG reg,
io_base           191 sound/isa/sscape.c 	outb(reg, ODIE_ADDR_IO(io_base));
io_base           192 sound/isa/sscape.c 	outb(val, ODIE_DATA_IO(io_base));
io_base           205 sound/isa/sscape.c 	sscape_write_unsafe(s->io_base, reg, val);
io_base           213 sound/isa/sscape.c static inline unsigned char sscape_read_unsafe(unsigned io_base,
io_base           216 sound/isa/sscape.c 	outb(reg, ODIE_ADDR_IO(io_base));
io_base           217 sound/isa/sscape.c 	return inb(ODIE_DATA_IO(io_base));
io_base           223 sound/isa/sscape.c static inline void set_host_mode_unsafe(unsigned io_base)
io_base           225 sound/isa/sscape.c 	outb(0x0, HOST_CTRL_IO(io_base));
io_base           231 sound/isa/sscape.c static inline void set_midi_mode_unsafe(unsigned io_base)
io_base           233 sound/isa/sscape.c 	outb(0x3, HOST_CTRL_IO(io_base));
io_base           240 sound/isa/sscape.c static inline int host_read_unsafe(unsigned io_base)
io_base           243 sound/isa/sscape.c 	if ((inb(HOST_CTRL_IO(io_base)) & RX_READY) != 0)
io_base           244 sound/isa/sscape.c 		data = inb(HOST_DATA_IO(io_base));
io_base           254 sound/isa/sscape.c static int host_read_ctrl_unsafe(unsigned io_base, unsigned timeout)
io_base           258 sound/isa/sscape.c 	while (((data = host_read_unsafe(io_base)) < 0) && (timeout != 0)) {
io_base           270 sound/isa/sscape.c static inline int host_write_unsafe(unsigned io_base, unsigned char data)
io_base           272 sound/isa/sscape.c 	if ((inb(HOST_CTRL_IO(io_base)) & TX_READY) != 0) {
io_base           273 sound/isa/sscape.c 		outb(data, HOST_DATA_IO(io_base));
io_base           285 sound/isa/sscape.c static int host_write_ctrl_unsafe(unsigned io_base, unsigned char data,
io_base           290 sound/isa/sscape.c 	while (!(err = host_write_unsafe(io_base, data)) && (timeout != 0)) {
io_base           323 sound/isa/sscape.c static void activate_ad1845_unsafe(unsigned io_base)
io_base           325 sound/isa/sscape.c 	unsigned char val = sscape_read_unsafe(io_base, GA_HMCTL_REG);
io_base           326 sound/isa/sscape.c 	sscape_write_unsafe(io_base, GA_HMCTL_REG, (val & 0xcf) | 0x10);
io_base           327 sound/isa/sscape.c 	sscape_write_unsafe(io_base, GA_CDCFG_REG, 0x80);
io_base           345 sound/isa/sscape.c static void sscape_start_dma_unsafe(unsigned io_base, enum GA_REG reg)
io_base           347 sound/isa/sscape.c 	sscape_write_unsafe(io_base, reg,
io_base           348 sound/isa/sscape.c 			    sscape_read_unsafe(io_base, reg) | 0x01);
io_base           349 sound/isa/sscape.c 	sscape_write_unsafe(io_base, reg,
io_base           350 sound/isa/sscape.c 			    sscape_read_unsafe(io_base, reg) & 0xfe);
io_base           357 sound/isa/sscape.c static int sscape_wait_dma_unsafe(unsigned io_base, enum GA_REG reg,
io_base           360 sound/isa/sscape.c 	while (!(sscape_read_unsafe(io_base, reg) & 0x01) && (timeout != 0)) {
io_base           365 sound/isa/sscape.c 	return sscape_read_unsafe(io_base, reg) & 0x01;
io_base           384 sound/isa/sscape.c 		x = host_read_unsafe(s->io_base);
io_base           411 sound/isa/sscape.c 		x = host_read_unsafe(s->io_base);
io_base           441 sound/isa/sscape.c 	val = sscape_read_unsafe(s->io_base, GA_HMCTL_REG);
io_base           442 sound/isa/sscape.c 	sscape_write_unsafe(s->io_base, GA_HMCTL_REG, val & 0x3f);
io_base           448 sound/isa/sscape.c 	sscape_write_unsafe(s->io_base, GA_DMAA_REG, val);
io_base           449 sound/isa/sscape.c 	sscape_write_unsafe(s->io_base, GA_DMAB_REG, 0x20);
io_base           454 sound/isa/sscape.c 	val = sscape_read_unsafe(s->io_base, GA_HMCTL_REG);
io_base           455 sound/isa/sscape.c 	sscape_write_unsafe(s->io_base, GA_HMCTL_REG, val | 0x80);
io_base           470 sound/isa/sscape.c 		sscape_start_dma_unsafe(s->io_base, GA_DMAA_REG);
io_base           471 sound/isa/sscape.c 		if (!sscape_wait_dma_unsafe(s->io_base, GA_DMAA_REG, 5000)) {
io_base           484 sound/isa/sscape.c 	set_host_mode_unsafe(s->io_base);
io_base           485 sound/isa/sscape.c 	outb(0x0, s->io_base);
io_base           490 sound/isa/sscape.c 	val = sscape_read_unsafe(s->io_base, GA_HMCTL_REG);
io_base           491 sound/isa/sscape.c 	sscape_write_unsafe(s->io_base, GA_HMCTL_REG, val | 0x40);
io_base           544 sound/isa/sscape.c 		data = host_read_ctrl_unsafe(sscape->io_base, 100);
io_base           547 sound/isa/sscape.c 		sscape_write_unsafe(sscape->io_base, GA_SMCFGA_REG, 0x2f);
io_base           633 sound/isa/sscape.c 	set_host_mode_unsafe(s->io_base);
io_base           645 sound/isa/sscape.c 	change = host_write_ctrl_unsafe(s->io_base, CMD_SET_MIDI_VOL, 100)
io_base           646 sound/isa/sscape.c 		 && host_write_ctrl_unsafe(s->io_base, new_val, 100)
io_base           647 sound/isa/sscape.c 		 && host_write_ctrl_unsafe(s->io_base, CMD_XXX_MIDI_VOL, 100)
io_base           648 sound/isa/sscape.c 		 && host_write_ctrl_unsafe(s->io_base, new_val, 100);
io_base           655 sound/isa/sscape.c 	set_midi_mode_unsafe(s->io_base);
io_base           710 sound/isa/sscape.c 	if ((inb(HOST_CTRL_IO(s->io_base)) & 0x78) != 0)
io_base           713 sound/isa/sscape.c 	d = inb(ODIE_ADDR_IO(s->io_base)) & 0xf0;
io_base           724 sound/isa/sscape.c 	outb(0xfa, ODIE_ADDR_IO(s->io_base));
io_base           725 sound/isa/sscape.c 	if ((inb(ODIE_ADDR_IO(s->io_base)) & 0x9f) != 0x0a)
io_base           728 sound/isa/sscape.c 	outb(0xfe, ODIE_ADDR_IO(s->io_base));
io_base           729 sound/isa/sscape.c 	if ((inb(ODIE_ADDR_IO(s->io_base)) & 0x9f) != 0x0e)
io_base           732 sound/isa/sscape.c 	outb(0xfe, ODIE_ADDR_IO(s->io_base));
io_base           733 sound/isa/sscape.c 	d = inb(ODIE_DATA_IO(s->io_base));
io_base           738 sound/isa/sscape.c 		activate_ad1845_unsafe(s->io_base);
io_base           743 sound/isa/sscape.c 	d  = sscape_read_unsafe(s->io_base, GA_HMCTL_REG);
io_base           744 sound/isa/sscape.c 	sscape_write_unsafe(s->io_base, GA_HMCTL_REG, d | 0xc0);
io_base           761 sound/isa/sscape.c 	d  = sscape_read_unsafe(s->io_base, GA_HMCTL_REG) & 0x3f;
io_base           762 sound/isa/sscape.c 	sscape_write_unsafe(s->io_base, GA_HMCTL_REG, d);
io_base           767 sound/isa/sscape.c 	d = sscape_read_unsafe(s->io_base, GA_HMCTL_REG);
io_base           768 sound/isa/sscape.c 	sscape_write_unsafe(s->io_base, GA_HMCTL_REG, d | 0xc0);
io_base           973 sound/isa/sscape.c 	sscape->io_base = port[dev];
io_base           977 sound/isa/sscape.c 			sscape->io_base);
io_base          1001 sound/isa/sscape.c 			 name, sscape->io_base, irq[dev], dma[dev]);
io_base          1026 sound/isa/sscape.c 	sscape_write_unsafe(sscape->io_base, GA_SMCFGA_REG, 0x2e);
io_base          1027 sound/isa/sscape.c 	sscape_write_unsafe(sscape->io_base, GA_SMCFGB_REG, 0x00);
io_base          1032 sound/isa/sscape.c 	sscape_write_unsafe(sscape->io_base, GA_DMACFG_REG, 0x50);
io_base          1034 sound/isa/sscape.c 	sscape_write_unsafe(sscape->io_base, GA_DMAA_REG, dma_cfg);
io_base          1035 sound/isa/sscape.c 	sscape_write_unsafe(sscape->io_base, GA_DMAB_REG, 0x20);
io_base          1038 sound/isa/sscape.c 	val = sscape_read_unsafe(sscape->io_base, GA_HMCTL_REG) & 0xF7;
io_base          1041 sound/isa/sscape.c 	sscape_write_unsafe(sscape->io_base, GA_HMCTL_REG, val | 0x10);
io_base          1042 sound/isa/sscape.c 	sscape_write_unsafe(sscape->io_base, GA_INTCFG_REG, 0xf0 | mpu_irq_cfg);
io_base          1043 sound/isa/sscape.c 	sscape_write_unsafe(sscape->io_base,
io_base          1049 sound/isa/sscape.c 	sscape_write_unsafe(sscape->io_base, GA_INTENA_REG, 0x80);
io_base          1093 sound/isa/sscape.c 			host_write_ctrl_unsafe(sscape->io_base,
io_base          1095 sound/isa/sscape.c 			host_write_ctrl_unsafe(sscape->io_base,
io_base          1097 sound/isa/sscape.c 			host_write_ctrl_unsafe(sscape->io_base,
io_base          1099 sound/isa/sscape.c 			host_write_ctrl_unsafe(sscape->io_base,
io_base          1101 sound/isa/sscape.c 			host_write_ctrl_unsafe(sscape->io_base,
io_base          1103 sound/isa/sscape.c 			host_write_ctrl_unsafe(sscape->io_base,
io_base          1105 sound/isa/sscape.c 			host_write_ctrl_unsafe(sscape->io_base, CMD_ACK, 100);
io_base          1107 sound/isa/sscape.c 			set_midi_mode_unsafe(sscape->io_base);
io_base           251 sound/pci/azt3328.c 	unsigned long io_base; /* keep first! (avoid offset calc) */
io_base           343 sound/pci/azt3328.c 	outb(value, codec->io_base + reg);
io_base           349 sound/pci/azt3328.c 	return inb(codec->io_base + reg);
io_base           358 sound/pci/azt3328.c 	outw(value, codec->io_base + reg);
io_base           364 sound/pci/azt3328.c 	return inw(codec->io_base + reg);
io_base           373 sound/pci/azt3328.c 	outl(value, codec->io_base + reg);
io_base           381 sound/pci/azt3328.c 	unsigned long addr = codec->io_base + reg;
io_base           394 sound/pci/azt3328.c 	return inl(codec->io_base + reg);
io_base          2427 sound/pci/azt3328.c 	codec_setup->io_base = chip->ctrl_io + AZF_IO_OFFS_CODEC_PLAYBACK;
io_base          2433 sound/pci/azt3328.c 	codec_setup->io_base = chip->ctrl_io + AZF_IO_OFFS_CODEC_CAPTURE;
io_base          2439 sound/pci/azt3328.c 	codec_setup->io_base = chip->ctrl_io + AZF_IO_OFFS_CODEC_I2S_OUT;
io_base           186 sound/pci/ctxfi/cthardware.h 	unsigned long io_base;
io_base          1795 sound/pci/ctxfi/cthw20k1.c 	unsigned int io_base;
io_base          1807 sound/pci/ctxfi/cthw20k1.c 	io_base = pci_resource_start(pci, 0);
io_base          1808 sound/pci/ctxfi/cthw20k1.c 	mem_base = ioremap(io_base, pci_resource_len(pci, 0));
io_base          1911 sound/pci/ctxfi/cthw20k1.c 	if (!hw->io_base) {
io_base          1917 sound/pci/ctxfi/cthw20k1.c 			hw->io_base = pci_resource_start(pci, 5);
io_base          1919 sound/pci/ctxfi/cthw20k1.c 			hw->io_base = pci_resource_start(pci, 0);
io_base          1948 sound/pci/ctxfi/cthw20k1.c 	hw->io_base = 0;
io_base          1980 sound/pci/ctxfi/cthw20k1.c 	if (hw->io_base)
io_base          1983 sound/pci/ctxfi/cthw20k1.c 	hw->io_base = 0;
io_base          2105 sound/pci/ctxfi/cthw20k1.c 	outl(reg, hw->io_base + 0x0);
io_base          2106 sound/pci/ctxfi/cthw20k1.c 	value = inl(hw->io_base + 0x4);
io_base          2119 sound/pci/ctxfi/cthw20k1.c 	outl(reg, hw->io_base + 0x0);
io_base          2120 sound/pci/ctxfi/cthw20k1.c 	outl(data, hw->io_base + 0x4);
io_base          2133 sound/pci/ctxfi/cthw20k1.c 	outl(reg, hw->io_base + 0x10);
io_base          2134 sound/pci/ctxfi/cthw20k1.c 	value = inl(hw->io_base + 0x14);
io_base          2147 sound/pci/ctxfi/cthw20k1.c 	outl(reg, hw->io_base + 0x10);
io_base          2148 sound/pci/ctxfi/cthw20k1.c 	outl(data, hw->io_base + 0x14);
io_base          2278 sound/pci/ctxfi/cthw20k1.c 	if (hw->io_base)
io_base          2036 sound/pci/ctxfi/cthw20k2.c 	if (!hw->io_base) {
io_base          2041 sound/pci/ctxfi/cthw20k2.c 		hw->io_base = pci_resource_start(hw->pci, 2);
io_base          2042 sound/pci/ctxfi/cthw20k2.c 		hw->mem_base = ioremap(hw->io_base,
io_base          2075 sound/pci/ctxfi/cthw20k2.c 	hw->io_base = 0;
io_base          2105 sound/pci/ctxfi/cthw20k2.c 	if (hw->io_base)
io_base          2108 sound/pci/ctxfi/cthw20k2.c 	hw->io_base = 0;
io_base          2344 sound/pci/ctxfi/cthw20k2.c 	if (hw->io_base)
io_base           555 sound/soc/atmel/atmel-classd.c 	void __iomem *io_base;
io_base           592 sound/soc/atmel/atmel-classd.c 	io_base = devm_ioremap_resource(dev, res);
io_base           593 sound/soc/atmel/atmel-classd.c 	if (IS_ERR(io_base))
io_base           594 sound/soc/atmel/atmel-classd.c 		return PTR_ERR(io_base);
io_base           599 sound/soc/atmel/atmel-classd.c 	dd->regmap = devm_regmap_init_mmio(dev, io_base,
io_base           597 sound/soc/atmel/atmel-pdmic.c 	void __iomem *io_base;
io_base           642 sound/soc/atmel/atmel-pdmic.c 	io_base = devm_ioremap_resource(dev, res);
io_base           643 sound/soc/atmel/atmel-pdmic.c 	if (IS_ERR(io_base))
io_base           644 sound/soc/atmel/atmel-pdmic.c 		return PTR_ERR(io_base);
io_base           648 sound/soc/atmel/atmel-pdmic.c 	dd->regmap = devm_regmap_init_mmio(dev, io_base,
io_base            29 sound/soc/dwc/dwc-i2s.c static inline void i2s_write_reg(void __iomem *io_base, int reg, u32 val)
io_base            31 sound/soc/dwc/dwc-i2s.c 	writel(val, io_base + reg);
io_base            34 sound/soc/dwc/dwc-i2s.c static inline u32 i2s_read_reg(void __iomem *io_base, int reg)
io_base            36 sound/soc/dwc/dwc-i2s.c 	return readl(io_base + reg);
io_base            38 sound/soc/spear/spdif_in.c 	void *io_base;
io_base            52 sound/soc/spear/spdif_in.c 	writel(ctrl, host->io_base + SPDIF_IN_CTRL);
io_base            53 sound/soc/spear/spdif_in.c 	writel(0xF, host->io_base + SPDIF_IN_IRQ_MASK);
io_base            74 sound/soc/spear/spdif_in.c 	writel(0x0, host->io_base + SPDIF_IN_IRQ_MASK);
io_base            79 sound/soc/spear/spdif_in.c 	u32 ctrl = readl(host->io_base + SPDIF_IN_CTRL);
io_base            91 sound/soc/spear/spdif_in.c 	writel(ctrl, host->io_base + SPDIF_IN_CTRL);
io_base           128 sound/soc/spear/spdif_in.c 		ctrl = readl(host->io_base + SPDIF_IN_CTRL);
io_base           130 sound/soc/spear/spdif_in.c 		writel(ctrl, host->io_base + SPDIF_IN_CTRL);
io_base           131 sound/soc/spear/spdif_in.c 		writel(0xF, host->io_base + SPDIF_IN_IRQ_MASK);
io_base           137 sound/soc/spear/spdif_in.c 		ctrl = readl(host->io_base + SPDIF_IN_CTRL);
io_base           139 sound/soc/spear/spdif_in.c 		writel(ctrl, host->io_base + SPDIF_IN_CTRL);
io_base           140 sound/soc/spear/spdif_in.c 		writel(0x0, host->io_base + SPDIF_IN_IRQ_MASK);
io_base           182 sound/soc/spear/spdif_in.c 	u32 irq_status = readl(host->io_base + SPDIF_IN_IRQ);
io_base           196 sound/soc/spear/spdif_in.c 	writel(0, host->io_base + SPDIF_IN_IRQ);
io_base           206 sound/soc/spear/spdif_in.c 	void __iomem *io_base;
io_base           209 sound/soc/spear/spdif_in.c 	io_base = devm_platform_ioremap_resource(pdev, 0);
io_base           210 sound/soc/spear/spdif_in.c 	if (IS_ERR(io_base))
io_base           211 sound/soc/spear/spdif_in.c 		return PTR_ERR(io_base);
io_base           221 sound/soc/spear/spdif_in.c 	host->io_base = io_base;
io_base            39 sound/soc/spear/spdif_out.c 	void __iomem *io_base;
io_base            46 sound/soc/spear/spdif_out.c 	writel(SPDIF_OUT_RESET, host->io_base + SPDIF_OUT_SOFT_RST);
io_base            48 sound/soc/spear/spdif_out.c 	writel(readl(host->io_base + SPDIF_OUT_SOFT_RST) & ~SPDIF_OUT_RESET,
io_base            49 sound/soc/spear/spdif_out.c 			host->io_base + SPDIF_OUT_SOFT_RST);
io_base            54 sound/soc/spear/spdif_out.c 			host->io_base + SPDIF_OUT_CFG);
io_base            56 sound/soc/spear/spdif_out.c 	writel(0x7F, host->io_base + SPDIF_OUT_INT_STA_CLR);
io_base            57 sound/soc/spear/spdif_out.c 	writel(0x7F, host->io_base + SPDIF_OUT_INT_EN_CLR);
io_base            99 sound/soc/spear/spdif_out.c 	ctrl = readl(host->io_base + SPDIF_OUT_CTRL);
io_base           102 sound/soc/spear/spdif_out.c 	writel(ctrl, host->io_base + SPDIF_OUT_CTRL);
io_base           165 sound/soc/spear/spdif_out.c 			ctrl = readl(host->io_base + SPDIF_OUT_CTRL);
io_base           172 sound/soc/spear/spdif_out.c 			writel(ctrl, host->io_base + SPDIF_OUT_CTRL);
io_base           178 sound/soc/spear/spdif_out.c 		ctrl = readl(host->io_base + SPDIF_OUT_CTRL);
io_base           181 sound/soc/spear/spdif_out.c 		writel(ctrl, host->io_base + SPDIF_OUT_CTRL);
io_base           197 sound/soc/spear/spdif_out.c 	val = readl(host->io_base + SPDIF_OUT_CTRL);
io_base           209 sound/soc/spear/spdif_out.c 	writel(val, host->io_base + SPDIF_OUT_CTRL);
io_base           289 sound/soc/spear/spdif_out.c 	host->io_base = devm_ioremap_resource(&pdev->dev, res);
io_base           290 sound/soc/spear/spdif_out.c 	if (IS_ERR(host->io_base))
io_base           291 sound/soc/spear/spdif_out.c 		return PTR_ERR(host->io_base);
io_base           651 sound/soc/ti/davinci-i2s.c 	void __iomem *io_base;
io_base           666 sound/soc/ti/davinci-i2s.c 	io_base = devm_ioremap_resource(&pdev->dev, mem);
io_base           667 sound/soc/ti/davinci-i2s.c 	if (IS_ERR(io_base))
io_base           668 sound/soc/ti/davinci-i2s.c 		return PTR_ERR(io_base);
io_base           675 sound/soc/ti/davinci-i2s.c 	dev->base = io_base;
io_base            35 sound/soc/ti/omap-dmic.c 	void __iomem *io_base;
io_base            53 sound/soc/ti/omap-dmic.c 	writel_relaxed(val, dmic->io_base + reg);
io_base            58 sound/soc/ti/omap-dmic.c 	return readl_relaxed(dmic->io_base + reg);
io_base           490 sound/soc/ti/omap-dmic.c 	dmic->io_base = devm_ioremap_resource(&pdev->dev, res);
io_base           491 sound/soc/ti/omap-dmic.c 	if (IS_ERR(dmic->io_base))
io_base           492 sound/soc/ti/omap-dmic.c 		return PTR_ERR(dmic->io_base);
io_base           247 sound/soc/ti/omap-mcbsp-priv.h 	void __iomem *io_base;
io_base           284 sound/soc/ti/omap-mcbsp-priv.h 	void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
io_base           298 sound/soc/ti/omap-mcbsp-priv.h 	void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
io_base           630 sound/soc/ti/omap-mcbsp.c 	mcbsp->io_base = devm_ioremap_resource(&pdev->dev, res);
io_base           631 sound/soc/ti/omap-mcbsp.c 	if (IS_ERR(mcbsp->io_base))
io_base           632 sound/soc/ti/omap-mcbsp.c 		return PTR_ERR(mcbsp->io_base);
io_base            41 sound/soc/ti/omap-mcpdm.c 	void __iomem *io_base;
io_base            69 sound/soc/ti/omap-mcpdm.c 	writel_relaxed(val, mcpdm->io_base + reg);
io_base            74 sound/soc/ti/omap-mcpdm.c 	return readl_relaxed(mcpdm->io_base + reg);
io_base           566 sound/soc/ti/omap-mcpdm.c 	mcpdm->io_base = devm_ioremap_resource(&pdev->dev, res);
io_base           567 sound/soc/ti/omap-mcpdm.c 	if (IS_ERR(mcpdm->io_base))
io_base           568 sound/soc/ti/omap-mcpdm.c 		return PTR_ERR(mcpdm->io_base);