inv 720 arch/x86/events/amd/core.c PMU_FORMAT_ATTR(inv, "config:23" ); inv 1744 arch/x86/events/core.c bool inv = (config & ARCH_PERFMON_EVENTSEL_INV); inv 1765 arch/x86/events/core.c if (inv) inv 3137 arch/x86/events/intel/core.c u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16); inv 3165 arch/x86/events/intel/core.c u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16); inv 3189 arch/x86/events/intel/core.c u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16); inv 3593 arch/x86/events/intel/core.c PMU_FORMAT_ATTR(inv, "config:23" ); inv 4638 arch/x86/events/intel/core.c X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); inv 4641 arch/x86/events/intel/core.c X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); inv 4795 arch/x86/events/intel/core.c X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); inv 4798 arch/x86/events/intel/core.c X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); inv 4835 arch/x86/events/intel/core.c X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); inv 4838 arch/x86/events/intel/core.c X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1); inv 4876 arch/x86/events/intel/core.c X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); inv 278 arch/x86/events/intel/knc.c PMU_FORMAT_ATTR(inv, "config:23" ); inv 188 arch/x86/events/intel/p6.c PMU_FORMAT_ATTR(inv, "config:23" ); inv 194 arch/x86/events/intel/uncore_nhmex.c DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23"); inv 116 arch/x86/events/intel/uncore_snb.c DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23"); inv 396 arch/x86/events/intel/uncore_snbep.c DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23"); inv 544 arch/x86/events/perf_event.h inv:1, inv 631 drivers/auxdisplay/panel.c int d_bit, c_bit, inv; inv 643 drivers/auxdisplay/panel.c inv = (pin < 0); inv 644 drivers/auxdisplay/panel.c if (inv) inv 653 drivers/auxdisplay/panel.c inv = !inv; inv 660 drivers/auxdisplay/panel.c inv = !inv; inv 667 drivers/auxdisplay/panel.c inv = !inv; inv 675 drivers/auxdisplay/panel.c c_val[!inv] = c_bit; inv 678 drivers/auxdisplay/panel.c d_val[!inv] = d_bit; inv 414 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t inv) inv 430 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c amdgpu_ring_write(ring, inv); /* poll interval */ inv 820 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t inv) inv 836 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c amdgpu_ring_write(ring, inv); /* poll interval */ inv 718 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c uint32_t inv) inv 736 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */ inv 123 drivers/hwmon/pc87360.c #define PWM_FROM_REG(val, inv) ((inv) ? 255 - (val) : (val)) inv 124 drivers/hwmon/pc87360.c static inline u8 PWM_TO_REG(int val, int inv) inv 126 drivers/hwmon/pc87360.c if (inv) inv 886 drivers/infiniband/hw/cxgb4/qp.c wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey); inv 887 drivers/infiniband/hw/cxgb4/qp.c wqe->inv.r2 = 0; inv 888 drivers/infiniband/hw/cxgb4/qp.c *len16 = DIV_ROUND_UP(sizeof(wqe->inv), 16); inv 107 drivers/infiniband/hw/cxgb4/t4.h struct fw_ri_inv_lstag_wr inv; inv 335 drivers/infiniband/hw/hfi1/uc.c inv: inv 368 drivers/infiniband/hw/hfi1/uc.c goto inv; inv 376 drivers/infiniband/hw/hfi1/uc.c goto inv; inv 386 drivers/infiniband/hw/hfi1/uc.c goto inv; inv 273 drivers/infiniband/hw/qib/qib_uc.c inv: inv 305 drivers/infiniband/hw/qib/qib_uc.c goto inv; inv 313 drivers/infiniband/hw/qib/qib_uc.c goto inv; inv 323 drivers/infiniband/hw/qib/qib_uc.c goto inv; inv 202 drivers/irqchip/irq-gic-v4.c int its_prop_update_vlpi(int irq, u8 config, bool inv) inv 205 drivers/irqchip/irq-gic-v4.c .cmd_type = inv ? PROP_UPDATE_AND_INV_VLPI : PROP_UPDATE_VLPI, inv 1558 drivers/media/dvb-frontends/cx24117.c u8 reg, st, inv; inv 1582 drivers/media/dvb-frontends/cx24117.c inv = (((state->demod == 0) ? ~st : st) >> 6) & 1; inv 1583 drivers/media/dvb-frontends/cx24117.c if (inv == 0) inv 332 drivers/media/dvb-frontends/lgs8gl5.c u8 inv = lgs8gl5_read_reg(state, REG_INVERSION); inv 334 drivers/media/dvb-frontends/lgs8gl5.c p->inversion = (inv & REG_INVERSION_ON) ? INVERSION_ON : INVERSION_OFF; inv 450 drivers/media/dvb-frontends/tda10023.c int sync,inv; inv 455 drivers/media/dvb-frontends/tda10023.c inv = tda10023_readreg(state, 0x04); inv 465 drivers/media/dvb-frontends/tda10023.c p->inversion = (inv&0x20?0:1); inv 1261 drivers/misc/fastrpc.c struct fastrpc_invoke inv; inv 1265 drivers/misc/fastrpc.c if (copy_from_user(&inv, argp, sizeof(inv))) inv 1269 drivers/misc/fastrpc.c nscalars = REMOTE_SCALARS_LENGTH(inv.sc); inv 1275 drivers/misc/fastrpc.c if (copy_from_user(args, (void __user *)(uintptr_t)inv.args, inv 1282 drivers/misc/fastrpc.c err = fastrpc_internal_invoke(fl, false, inv.handle, inv.sc, args); inv 256 drivers/mtd/nand/raw/nand_hynix.c #define NAND_HYNIX_1XNM_RR_SET_OFFS(x, setsize, inv) \ inv 257 drivers/mtd/nand/raw/nand_hynix.c (16 + ((((x) * 2) + ((inv) ? 1 : 0)) * (setsize))) inv 260 drivers/mtd/nand/raw/nand_hynix.c int mode, int reg, bool inv, u8 *val) inv 268 drivers/mtd/nand/raw/nand_hynix.c int set_offs = NAND_HYNIX_1XNM_RR_SET_OFFS(i, set_size, inv); inv 277 drivers/mtd/nand/raw/nand_hynix.c if (inv) inv 2520 drivers/net/ethernet/mellanox/mlx5/core/en_main.c int inv = 0; inv 2524 drivers/net/ethernet/mellanox/mlx5/core/en_main.c inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i; inv 2526 drivers/net/ethernet/mellanox/mlx5/core/en_main.c return inv; inv 1524 drivers/net/ethernet/packetengines/hamachi.c u32 inv = *(u32 *) &buf_addr[data_size - 16]; inv 1528 drivers/net/ethernet/packetengines/hamachi.c if (inv & 4) { inv 1529 drivers/net/ethernet/packetengines/hamachi.c inv &= ~4; inv 1534 drivers/net/ethernet/packetengines/hamachi.c switch (inv) { inv 1211 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c bool en, bool ipv6, bool sa, bool inv, inv 1233 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c if (inv) inv 1237 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c if (inv) inv 1244 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c if (inv) inv 1248 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c if (inv) inv 1274 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c bool en, bool udp, bool sa, bool inv, inv 1299 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c if (inv) inv 1303 drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c if (inv) inv 368 drivers/net/ethernet/stmicro/stmmac/hwif.h bool en, bool ipv6, bool sa, bool inv, inv 371 drivers/net/ethernet/stmicro/stmmac/hwif.h bool en, bool udp, bool sa, bool inv, inv 417 drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c bool inv = entry->action & STMMAC_FLOW_ACTION_DROP; inv 430 drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c false, true, inv, hw_match); inv 438 drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c false, false, inv, hw_match); inv 452 drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c bool inv = entry->action & STMMAC_FLOW_ACTION_DROP; inv 478 drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c is_udp, true, inv, hw_match); inv 486 drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c is_udp, false, inv, hw_match); inv 96 drivers/power/supply/generic-adc-battery.c bool inv = pdata->gpio_inverted; inv 100 drivers/power/supply/generic-adc-battery.c return ret ^ inv; inv 496 drivers/video/fbdev/mmp/hw/mmp_ctrl.h #define CFG_VSYNC_INV(inv) ((inv)<<27) inv 271 drivers/video/fbdev/pxa168fb.h #define CFG_VSYNC_INV(inv) ((inv) << 27) inv 99 include/linux/irqchip/arm-gic-v4.h int its_prop_update_vlpi(int irq, u8 config, bool inv); inv 226 lib/842/842_compress.c bool inv = false; inv 243 lib/842/842_compress.c inv = true; inv 249 lib/842/842_compress.c inv = true; inv 255 lib/842/842_compress.c inv = true; inv 261 lib/842/842_compress.c inv = true; inv 265 lib/842/842_compress.c inv = true; inv 271 lib/842/842_compress.c inv = true; inv 274 lib/842/842_compress.c inv = (b != 8) || !(t[i] & OP_ACTION_NOOP); inv 277 lib/842/842_compress.c inv = true; inv 284 lib/842/842_compress.c if (inv) { inv 367 net/can/af_can.c canid_t inv = *can_id & CAN_INV_FILTER; /* save flag before masking */ inv 388 net/can/af_can.c if (inv) inv 138 net/netfilter/nft_compat.c union nft_entry *entry, u16 proto, bool inv) inv 145 net/netfilter/nft_compat.c entry->e4.ip.invflags = inv ? IPT_INV_PROTO : 0; inv 152 net/netfilter/nft_compat.c entry->e6.ipv6.invflags = inv ? IP6T_INV_PROTO : 0; inv 156 net/netfilter/nft_compat.c entry->ebt.invflags = inv ? EBT_IPROTO : 0; inv 192 net/netfilter/nft_compat.c static int nft_parse_compat(const struct nlattr *attr, u16 *proto, bool *inv) inv 210 net/netfilter/nft_compat.c *inv = true; inv 225 net/netfilter/nft_compat.c bool inv = false; inv 232 net/netfilter/nft_compat.c ret = nft_parse_compat(ctx->nla[NFTA_RULE_COMPAT], &proto, &inv); inv 237 net/netfilter/nft_compat.c nft_target_set_tgchk_param(&par, ctx, target, info, &e, proto, inv); inv 239 net/netfilter/nft_compat.c ret = xt_check_target(&par, size, proto, inv); inv 382 net/netfilter/nft_compat.c union nft_entry *entry, u16 proto, bool inv) inv 389 net/netfilter/nft_compat.c entry->e4.ip.invflags = inv ? IPT_INV_PROTO : 0; inv 396 net/netfilter/nft_compat.c entry->e6.ipv6.invflags = inv ? IP6T_INV_PROTO : 0; inv 400 net/netfilter/nft_compat.c entry->ebt.invflags = inv ? EBT_IPROTO : 0; inv 440 net/netfilter/nft_compat.c bool inv = false; inv 447 net/netfilter/nft_compat.c ret = nft_parse_compat(ctx->nla[NFTA_RULE_COMPAT], &proto, &inv); inv 452 net/netfilter/nft_compat.c nft_match_set_mtchk_param(&par, ctx, match, info, &e, proto, inv); inv 454 net/netfilter/nft_compat.c return xt_check_match(&par, size, proto, inv); inv 31 net/netfilter/xt_set.c struct ip_set_adt_opt *opt, int inv) inv 34 net/netfilter/xt_set.c inv = !inv; inv 35 net/netfilter/xt_set.c return inv; inv 204 sound/i2c/other/ak4113.c unsigned char inv = (kcontrol->private_value >> 31) & 1; inv 207 sound/i2c/other/ak4113.c ((reg_read(chip, reg) & (1 << bit)) ? 1 : 0) ^ inv; inv 199 sound/i2c/other/ak4114.c unsigned char inv = (kcontrol->private_value >> 31) & 1; inv 201 sound/i2c/other/ak4114.c ucontrol->value.integer.value[0] = ((reg_read(chip, reg) & (1 << bit)) ? 1 : 0) ^ inv; inv 173 sound/i2c/other/ak4117.c unsigned char inv = (kcontrol->private_value >> 31) & 1; inv 175 sound/i2c/other/ak4117.c ucontrol->value.integer.value[0] = ((reg_read(chip, reg) & (1 << bit)) ? 1 : 0) ^ inv; inv 279 sound/pci/ice1712/maya44.c #define COMPOSE_GPIO_VAL(shift, inv) ((shift) | ((inv) << 8)) inv 938 sound/soc/codecs/cs42l73.c unsigned int inv, format; inv 958 sound/soc/codecs/cs42l73.c inv = (fmt & SND_SOC_DAIFMT_INV_MASK); inv 987 sound/soc/codecs/cs42l73.c if (inv == SND_SOC_DAIFMT_IB_IF) inv 989 sound/soc/codecs/cs42l73.c if (inv == SND_SOC_DAIFMT_IB_NF) inv 993 sound/soc/codecs/cs42l73.c if (inv == SND_SOC_DAIFMT_IB_IF) inv 389 sound/soc/sh/rcar/core.c int id = 0, inv; inv 431 sound/soc/sh/rcar/core.c inv = 0; inv 434 sound/soc/sh/rcar/core.c inv = 1; inv 436 sound/soc/sh/rcar/core.c return dalign_values[id][inv];