intf_cfg           59 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	struct dpu_hw_intf_cfg intf_cfg = { 0 };
intf_cfg           68 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	intf_cfg.intf = phys_enc->intf_idx;
intf_cfg           69 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_CMD;
intf_cfg           70 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	intf_cfg.stream_sel = cmd_enc->stream_sel;
intf_cfg           71 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
intf_cfg           72 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c 	ctl->ops.setup_intf_cfg(ctl, &intf_cfg);
intf_cfg          240 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 	struct dpu_hw_intf_cfg intf_cfg = { 0 };
intf_cfg          274 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 	intf_cfg.intf = phys_enc->hw_intf->idx;
intf_cfg          275 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 	intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_VID;
intf_cfg          276 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 	intf_cfg.stream_sel = 0; /* Don't care value for video mode */
intf_cfg          277 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 	intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
intf_cfg          282 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 	phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg);
intf_cfg          429 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 	u32 intf_cfg = 0;
intf_cfg          431 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 	intf_cfg |= (cfg->intf & 0xF) << 4;
intf_cfg          434 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 		intf_cfg |= BIT(19);
intf_cfg          435 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 		intf_cfg |= (cfg->mode_3d - 0x1) << 20;
intf_cfg          440 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 		intf_cfg &= ~BIT(17);
intf_cfg          441 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 		intf_cfg &= ~(0x3 << 15);
intf_cfg          444 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 		intf_cfg |= BIT(17);
intf_cfg          445 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 		intf_cfg |= ((cfg->stream_sel & 0x3) << 15);
intf_cfg          452 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c 	DPU_REG_WRITE(c, CTL_TOP, intf_cfg);
intf_cfg           94 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 	u32 intf_cfg;
intf_cfg           97 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 	intf_cfg = DPU_REG_READ(c, INTF_CONFIG);
intf_cfg          134 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 		intf_cfg |= BIT(29);	/* ACTIVE_H_ENABLE */
intf_cfg          140 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 		intf_cfg |= BIT(30); /* ACTIVE_V_ENABLE */
intf_cfg          184 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 	DPU_REG_WRITE(c, INTF_CONFIG, intf_cfg);