interrupt_status_offsets   90 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c } interrupt_status_offsets[] = { {
interrupt_status_offsets 3214 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
interrupt_status_offsets 3219 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		if (disp_int & interrupt_status_offsets[crtc].vblank)
interrupt_status_offsets 3231 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 		if (disp_int & interrupt_status_offsets[crtc].vline)
interrupt_status_offsets 3260 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	disp_int = RREG32(interrupt_status_offsets[hpd].reg);
interrupt_status_offsets 3261 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	mask = interrupt_status_offsets[hpd].hpd;
interrupt_status_offsets   92 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c } interrupt_status_offsets[] = { {
interrupt_status_offsets 3340 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
interrupt_status_offsets 3346 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		if (disp_int & interrupt_status_offsets[crtc].vblank)
interrupt_status_offsets 3358 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 		if (disp_int & interrupt_status_offsets[crtc].vline)
interrupt_status_offsets 3387 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	disp_int = RREG32(interrupt_status_offsets[hpd].reg);
interrupt_status_offsets 3388 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	mask = interrupt_status_offsets[hpd].hpd;
interrupt_status_offsets   93 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c } interrupt_status_offsets[6] = { {
interrupt_status_offsets 2933 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
interrupt_status_offsets 2939 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		if (disp_int & interrupt_status_offsets[crtc].vblank)
interrupt_status_offsets 2950 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 		if (disp_int & interrupt_status_offsets[crtc].vline)
interrupt_status_offsets 3054 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	disp_int = RREG32(interrupt_status_offsets[hpd].reg);
interrupt_status_offsets 3055 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c 	mask = interrupt_status_offsets[hpd].hpd;
interrupt_status_offsets   90 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c } interrupt_status_offsets[6] = { {
interrupt_status_offsets 3025 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 	uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
interrupt_status_offsets 3031 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		if (disp_int & interrupt_status_offsets[crtc].vblank)
interrupt_status_offsets 3042 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 		if (disp_int & interrupt_status_offsets[crtc].vline)
interrupt_status_offsets 3146 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 	disp_int = RREG32(interrupt_status_offsets[hpd].reg);
interrupt_status_offsets 3147 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c 	mask = interrupt_status_offsets[hpd].hpd;