interlock          34 drivers/gpu/drm/nouveau/dispnv50/base507c.c base507c_update(struct nv50_wndw *wndw, u32 *interlock)
interlock          39 drivers/gpu/drm/nouveau/dispnv50/base507c.c 		evo_data(push, interlock[NV50_DISP_INTERLOCK_CORE]);
interlock          19 drivers/gpu/drm/nouveau/dispnv50/core.h 	void (*update)(struct nv50_core *, u32 *interlock, bool ntfy);
interlock          30 drivers/gpu/drm/nouveau/dispnv50/core507d.c core507d_update(struct nv50_core *core, u32 *interlock, bool ntfy)
interlock          39 drivers/gpu/drm/nouveau/dispnv50/core507d.c 		evo_data(push, interlock[NV50_DISP_INTERLOCK_BASE] |
interlock          40 drivers/gpu/drm/nouveau/dispnv50/core507d.c 			       interlock[NV50_DISP_INTERLOCK_OVLY]);
interlock          28 drivers/gpu/drm/nouveau/dispnv50/corec37d.c corec37d_update(struct nv50_core *core, u32 *interlock, bool ntfy)
interlock          38 drivers/gpu/drm/nouveau/dispnv50/corec37d.c 		evo_data(push, interlock[NV50_DISP_INTERLOCK_CURS]);
interlock          39 drivers/gpu/drm/nouveau/dispnv50/corec37d.c 		evo_data(push, interlock[NV50_DISP_INTERLOCK_WNDW]);
interlock          32 drivers/gpu/drm/nouveau/dispnv50/curs507a.c curs507a_update(struct nv50_wndw *wndw, u32 *interlock)
interlock          26 drivers/gpu/drm/nouveau/dispnv50/cursc37a.c cursc37a_update(struct nv50_wndw *wndw, u32 *interlock)
interlock        1775 drivers/gpu/drm/nouveau/dispnv50/disp.c nv50_disp_atomic_commit_core(struct drm_atomic_state *state, u32 *interlock)
interlock        1783 drivers/gpu/drm/nouveau/dispnv50/disp.c 	NV_ATOMIC(drm, "commit core %08x\n", interlock[NV50_DISP_INTERLOCK_BASE]);
interlock        1794 drivers/gpu/drm/nouveau/dispnv50/disp.c 	core->func->update(core, interlock, true);
interlock        1809 drivers/gpu/drm/nouveau/dispnv50/disp.c nv50_disp_atomic_commit_wndw(struct drm_atomic_state *state, u32 *interlock)
interlock        1817 drivers/gpu/drm/nouveau/dispnv50/disp.c 		if (interlock[wndw->interlock.type] & wndw->interlock.data) {
interlock        1819 drivers/gpu/drm/nouveau/dispnv50/disp.c 				wndw->func->update(wndw, interlock);
interlock        1836 drivers/gpu/drm/nouveau/dispnv50/disp.c 	u32 interlock[NV50_DISP_INTERLOCK__SIZE] = {};
interlock        1862 drivers/gpu/drm/nouveau/dispnv50/disp.c 			interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
interlock        1876 drivers/gpu/drm/nouveau/dispnv50/disp.c 		nv50_wndw_flush_clr(wndw, interlock, atom->flush_disable, asyw);
interlock        1892 drivers/gpu/drm/nouveau/dispnv50/disp.c 			interlock[NV50_DISP_INTERLOCK_CORE] |= 1;
interlock        1894 drivers/gpu/drm/nouveau/dispnv50/disp.c 				nv50_disp_atomic_commit_wndw(state, interlock);
interlock        1895 drivers/gpu/drm/nouveau/dispnv50/disp.c 				nv50_disp_atomic_commit_core(state, interlock);
interlock        1896 drivers/gpu/drm/nouveau/dispnv50/disp.c 				memset(interlock, 0x00, sizeof(interlock));
interlock        1902 drivers/gpu/drm/nouveau/dispnv50/disp.c 	if (interlock[NV50_DISP_INTERLOCK_CORE]) {
interlock        1904 drivers/gpu/drm/nouveau/dispnv50/disp.c 			nv50_disp_atomic_commit_wndw(state, interlock);
interlock        1905 drivers/gpu/drm/nouveau/dispnv50/disp.c 			nv50_disp_atomic_commit_core(state, interlock);
interlock        1906 drivers/gpu/drm/nouveau/dispnv50/disp.c 			memset(interlock, 0x00, sizeof(interlock));
interlock        1923 drivers/gpu/drm/nouveau/dispnv50/disp.c 			interlock[NV50_DISP_INTERLOCK_CORE] = 1;
interlock        1940 drivers/gpu/drm/nouveau/dispnv50/disp.c 			interlock[NV50_DISP_INTERLOCK_CORE] = 1;
interlock        1964 drivers/gpu/drm/nouveau/dispnv50/disp.c 		nv50_wndw_flush_set(wndw, interlock, asyw);
interlock        1968 drivers/gpu/drm/nouveau/dispnv50/disp.c 	nv50_disp_atomic_commit_wndw(state, interlock);
interlock        1970 drivers/gpu/drm/nouveau/dispnv50/disp.c 	if (interlock[NV50_DISP_INTERLOCK_CORE]) {
interlock        1971 drivers/gpu/drm/nouveau/dispnv50/disp.c 		if (interlock[NV50_DISP_INTERLOCK_BASE] ||
interlock        1972 drivers/gpu/drm/nouveau/dispnv50/disp.c 		    interlock[NV50_DISP_INTERLOCK_OVLY] ||
interlock        1973 drivers/gpu/drm/nouveau/dispnv50/disp.c 		    interlock[NV50_DISP_INTERLOCK_WNDW] ||
interlock        1975 drivers/gpu/drm/nouveau/dispnv50/disp.c 			nv50_disp_atomic_commit_core(state, interlock);
interlock        1977 drivers/gpu/drm/nouveau/dispnv50/disp.c 			disp->core->func->update(disp->core, interlock, false);
interlock          33 drivers/gpu/drm/nouveau/dispnv50/ovly507e.c ovly507e_update(struct nv50_wndw *wndw, u32 *interlock)
interlock          38 drivers/gpu/drm/nouveau/dispnv50/ovly507e.c 		evo_data(push, interlock[NV50_DISP_INTERLOCK_CORE]);
interlock          29 drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c wimmc37b_update(struct nv50_wndw *wndw, u32 *interlock)
interlock          34 drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c 		if (interlock[NV50_DISP_INTERLOCK_WNDW] & wndw->interlock.data)
interlock          78 drivers/gpu/drm/nouveau/dispnv50/wimmc37b.c 	wndw->interlock.wimm = wndw->interlock.data;
interlock         114 drivers/gpu/drm/nouveau/dispnv50/wndw.c nv50_wndw_flush_clr(struct nv50_wndw *wndw, u32 *interlock, bool flush,
interlock         126 drivers/gpu/drm/nouveau/dispnv50/wndw.c 	interlock[wndw->interlock.type] |= wndw->interlock.data;
interlock         130 drivers/gpu/drm/nouveau/dispnv50/wndw.c nv50_wndw_flush_set(struct nv50_wndw *wndw, u32 *interlock,
interlock         133 drivers/gpu/drm/nouveau/dispnv50/wndw.c 	if (interlock[NV50_DISP_INTERLOCK_CORE]) {
interlock         156 drivers/gpu/drm/nouveau/dispnv50/wndw.c 			interlock[wndw->interlock.type] |= wndw->interlock.data;
interlock         157 drivers/gpu/drm/nouveau/dispnv50/wndw.c 		interlock[NV50_DISP_INTERLOCK_WIMM] |= wndw->interlock.wimm;
interlock         160 drivers/gpu/drm/nouveau/dispnv50/wndw.c 		wndw->immd->update(wndw, interlock);
interlock         162 drivers/gpu/drm/nouveau/dispnv50/wndw.c 		interlock[wndw->interlock.type] |= wndw->interlock.data;
interlock         645 drivers/gpu/drm/nouveau/dispnv50/wndw.c 	wndw->interlock.type = interlock_type;
interlock         646 drivers/gpu/drm/nouveau/dispnv50/wndw.c 	wndw->interlock.data = interlock_data;
interlock          19 drivers/gpu/drm/nouveau/dispnv50/wndw.h 	struct nv50_disp_interlock interlock;
interlock          45 drivers/gpu/drm/nouveau/dispnv50/wndw.h void nv50_wndw_flush_set(struct nv50_wndw *, u32 *interlock,
interlock          47 drivers/gpu/drm/nouveau/dispnv50/wndw.h void nv50_wndw_flush_clr(struct nv50_wndw *, u32 *interlock, bool flush,
interlock          81 drivers/gpu/drm/nouveau/dispnv50/wndw.h 	void (*update)(struct nv50_wndw *, u32 *interlock);
interlock          95 drivers/gpu/drm/nouveau/dispnv50/wndw.h 	void (*update)(struct nv50_wndw *, u32 *interlock);
interlock         199 drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c wndwc37e_update(struct nv50_wndw *wndw, u32 *interlock)
interlock         204 drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c 		evo_data(push, interlock[NV50_DISP_INTERLOCK_CURS] << 1 |
interlock         205 drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c 			       interlock[NV50_DISP_INTERLOCK_CORE]);
interlock         206 drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c 		evo_data(push, interlock[NV50_DISP_INTERLOCK_WNDW]);
interlock         208 drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c 		if (interlock[NV50_DISP_INTERLOCK_WIMM] & wndw->interlock.data)
interlock        3222 drivers/infiniband/hw/hfi1/tid_rdma.c 				goto interlock;
interlock        3235 drivers/infiniband/hw/hfi1/tid_rdma.c 				goto interlock;
interlock        3240 drivers/infiniband/hw/hfi1/tid_rdma.c 				goto interlock;
interlock        3249 drivers/infiniband/hw/hfi1/tid_rdma.c interlock: