BL_PWM_PERIOD_CNTL   94 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 	pwm_period_cntl = REG_READ(BL_PWM_PERIOD_CNTL);
BL_PWM_PERIOD_CNTL   95 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 	REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, &bl_period);
BL_PWM_PERIOD_CNTL   96 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 	REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, &bl_int_count);
BL_PWM_PERIOD_CNTL  151 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 	REG_GET_2(BL_PWM_PERIOD_CNTL,
BL_PWM_PERIOD_CNTL  347 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 	abm->stored_backlight_registers.BL_PWM_PERIOD_CNTL =
BL_PWM_PERIOD_CNTL  348 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 		REG_READ(BL_PWM_PERIOD_CNTL);
BL_PWM_PERIOD_CNTL  371 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 			REG_WRITE(BL_PWM_PERIOD_CNTL,
BL_PWM_PERIOD_CNTL  372 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 				abm->stored_backlight_registers.BL_PWM_PERIOD_CNTL);
BL_PWM_PERIOD_CNTL  382 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 			REG_WRITE(BL_PWM_PERIOD_CNTL, 0x000C0FA0);
BL_PWM_PERIOD_CNTL  389 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 		abm->stored_backlight_registers.BL_PWM_PERIOD_CNTL =
BL_PWM_PERIOD_CNTL  390 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 				REG_READ(BL_PWM_PERIOD_CNTL);
BL_PWM_PERIOD_CNTL  462 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 	base->stored_backlight_registers.BL_PWM_PERIOD_CNTL = 0;
BL_PWM_PERIOD_CNTL   33 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h 	SR(BL_PWM_PERIOD_CNTL), \
BL_PWM_PERIOD_CNTL   90 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h 	ABM_SF(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, mask_sh), \
BL_PWM_PERIOD_CNTL   91 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h 	ABM_SF(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, mask_sh), \
BL_PWM_PERIOD_CNTL  208 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h 	uint32_t BL_PWM_PERIOD_CNTL;
BL_PWM_PERIOD_CNTL   33 drivers/gpu/drm/amd/display/dc/inc/hw/abm.h 	unsigned int BL_PWM_PERIOD_CNTL;