BL_PWM_GRP1_REG_LOCK  183 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 	REG_UPDATE_2(BL_PWM_GRP1_REG_LOCK,
BL_PWM_GRP1_REG_LOCK  185 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 			BL_PWM_GRP1_REG_LOCK, 1);
BL_PWM_GRP1_REG_LOCK  191 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 	REG_UPDATE(BL_PWM_GRP1_REG_LOCK,
BL_PWM_GRP1_REG_LOCK  192 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 			BL_PWM_GRP1_REG_LOCK, 0);
BL_PWM_GRP1_REG_LOCK  195 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 	REG_WAIT(BL_PWM_GRP1_REG_LOCK,
BL_PWM_GRP1_REG_LOCK  408 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 	REG_UPDATE(BL_PWM_GRP1_REG_LOCK,
BL_PWM_GRP1_REG_LOCK  409 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 			BL_PWM_GRP1_REG_LOCK, 0);
BL_PWM_GRP1_REG_LOCK   36 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h 	SR(BL_PWM_GRP1_REG_LOCK), \
BL_PWM_GRP1_REG_LOCK   95 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h 	ABM_SF(BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN, mask_sh), \
BL_PWM_GRP1_REG_LOCK   96 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h 	ABM_SF(BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_REG_LOCK, mask_sh), \
BL_PWM_GRP1_REG_LOCK   97 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h 	ABM_SF(BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_REG_UPDATE_PENDING, mask_sh), \
BL_PWM_GRP1_REG_LOCK  196 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h 	type BL_PWM_GRP1_REG_LOCK; \
BL_PWM_GRP1_REG_LOCK  226 drivers/gpu/drm/amd/display/dc/dce/dce_abm.h 	uint32_t BL_PWM_GRP1_REG_LOCK;