inst_offset 776 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c inst_offset = reg_offsets[pipe_ctx->stream_res.tg->inst].fmt; inst_offset 159 drivers/gpu/drm/amd/display/dc/dm_services.h #define dm_write_reg_soc15(ctx, reg, inst_offset, value) \ inst_offset 160 drivers/gpu/drm/amd/display/dc/dm_services.h dm_write_reg_func(ctx, reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX] + inst_offset, value, __func__) inst_offset 162 drivers/gpu/drm/amd/display/dc/dm_services.h #define dm_read_reg_soc15(ctx, reg, inst_offset) \ inst_offset 163 drivers/gpu/drm/amd/display/dc/dm_services.h dm_read_reg_func(ctx, reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX] + inst_offset, __func__) inst_offset 165 drivers/gpu/drm/amd/display/dc/dm_services.h #define generic_reg_update_soc15(ctx, inst_offset, reg_name, n, ...)\ inst_offset 166 drivers/gpu/drm/amd/display/dc/dm_services.h generic_reg_update_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + mm##reg_name + inst_offset, \ inst_offset 169 drivers/gpu/drm/amd/display/dc/dm_services.h #define generic_reg_set_soc15(ctx, inst_offset, reg_name, n, ...)\ inst_offset 170 drivers/gpu/drm/amd/display/dc/dm_services.h generic_reg_set_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + mm##reg_name + inst_offset, 0, \