insert_above_mpcc 181 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c struct mpcc *insert_above_mpcc, insert_above_mpcc 192 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c if (insert_above_mpcc) { insert_above_mpcc 196 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c while (temp_mpcc && temp_mpcc->mpcc_bot != insert_above_mpcc) insert_above_mpcc 207 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c if (insert_above_mpcc) { insert_above_mpcc 208 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c new_mpcc->mpcc_bot = insert_above_mpcc; insert_above_mpcc 209 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, insert_above_mpcc->mpcc_id); insert_above_mpcc 220 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c if (tree->opp_list == insert_above_mpcc) { insert_above_mpcc 228 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c while (temp_mpcc && temp_mpcc->mpcc_bot != insert_above_mpcc) insert_above_mpcc 230 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c if (temp_mpcc && temp_mpcc->mpcc_bot == insert_above_mpcc) { insert_above_mpcc 233 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c if (!insert_above_mpcc) insert_above_mpcc 140 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.h struct mpcc *insert_above_mpcc, insert_above_mpcc 174 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h struct mpcc *insert_above_mpcc,