input_rate        109 arch/c6x/include/asm/clock.h 	u32 input_rate;
input_rate        224 arch/c6x/platforms/pll.c 		rate = pll->input_rate;
input_rate        276 arch/c6x/platforms/pll.c 	rate = pll->input_rate = clk->parent->rate;
input_rate        516 drivers/clk/tegra/clk-pll.c 	for (sel = pll->params->freq_table; sel->input_rate != 0; sel++)
input_rate        517 drivers/clk/tegra/clk-pll.c 		if (sel->input_rate == parent_rate &&
input_rate        521 drivers/clk/tegra/clk-pll.c 	if (sel->input_rate == 0)
input_rate        532 drivers/clk/tegra/clk-pll.c 	cfg->input_rate = sel->input_rate;
input_rate        936 drivers/clk/tegra/clk-pll.c 	unsigned long input_rate;
input_rate        943 drivers/clk/tegra/clk-pll.c 	input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
input_rate        945 drivers/clk/tegra/clk-pll.c 	if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
input_rate       1077 drivers/clk/tegra/clk-pll.c 	unsigned long flags = 0, input_rate;
input_rate       1087 drivers/clk/tegra/clk-pll.c 	input_rate = clk_hw_get_rate(osc);
input_rate       1099 drivers/clk/tegra/clk-pll.c 		if (input_rate == utmi_parameters[i].osc_frequency) {
input_rate       1107 drivers/clk/tegra/clk-pll.c 		       input_rate);
input_rate       1189 drivers/clk/tegra/clk-pll.c 	cfg->input_rate = parent_rate;
input_rate       1208 drivers/clk/tegra/clk-pll.c u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate)
input_rate       1212 drivers/clk/tegra/clk-pll.c 	return (u16)_pll_fixed_mdiv(pll->params, input_rate);
input_rate       1407 drivers/clk/tegra/clk-pll.c 					unsigned long input_rate, u32 n)
input_rate       1411 drivers/clk/tegra/clk-pll.c 	switch (input_rate) {
input_rate       1427 drivers/clk/tegra/clk-pll.c 			__func__, input_rate);
input_rate       1570 drivers/clk/tegra/clk-pll.c 	unsigned long input_rate;
input_rate       1575 drivers/clk/tegra/clk-pll.c 	input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
input_rate       1577 drivers/clk/tegra/clk-pll.c 	if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
input_rate       1702 drivers/clk/tegra/clk-pll.c 	unsigned long flags = 0, input_rate;
input_rate       1715 drivers/clk/tegra/clk-pll.c 	input_rate = clk_hw_get_rate(__clk_get_hw(osc));
input_rate       1727 drivers/clk/tegra/clk-pll.c 		if (input_rate == utmi_parameters[i].osc_frequency) {
input_rate       1735 drivers/clk/tegra/clk-pll.c 		       input_rate);
input_rate       2407 drivers/clk/tegra/clk-pll.c 	unsigned long input_rate;
input_rate       2412 drivers/clk/tegra/clk-pll.c 	input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
input_rate       2414 drivers/clk/tegra/clk-pll.c 	if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
input_rate       1034 drivers/clk/tegra/clk-tegra210.c 	unsigned long input_rate;
input_rate       1038 drivers/clk/tegra/clk-tegra210.c 		input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
input_rate       1040 drivers/clk/tegra/clk-tegra210.c 		input_rate = 38400000;
input_rate       1042 drivers/clk/tegra/clk-tegra210.c 	input_rate /= tegra_pll_get_fixed_mdiv(hw, input_rate);
input_rate       1044 drivers/clk/tegra/clk-tegra210.c 	switch (input_rate) {
input_rate       1061 drivers/clk/tegra/clk-tegra210.c 			__func__, input_rate);
input_rate       1387 drivers/clk/tegra/clk-tegra210.c 		 cfg->input_rate / cfg->m * cfg->n /
input_rate       1403 drivers/clk/tegra/clk-tegra210.c 			       unsigned long rate, unsigned long input_rate)
input_rate       1424 drivers/clk/tegra/clk-tegra210.c 	cfg->m = tegra_pll_get_fixed_mdiv(hw, input_rate);
input_rate       1433 drivers/clk/tegra/clk-tegra210.c 	cf = input_rate / cfg->m;
input_rate       1437 drivers/clk/tegra/clk-tegra210.c 	cfg->output_rate = input_rate;
input_rate       1455 drivers/clk/tegra/clk-tegra210.c 	cfg->input_rate = input_rate;
input_rate       2829 drivers/clk/tegra/clk-tegra210.c 	for (fentry = pll_u_freq_table; fentry->input_rate; fentry++) {
input_rate       2830 drivers/clk/tegra/clk-tegra210.c 		if (fentry->input_rate == pll_ref_freq)
input_rate       2834 drivers/clk/tegra/clk-tegra210.c 	if (!fentry->input_rate) {
input_rate        106 drivers/clk/tegra/clk.h 	unsigned long	input_rate;
input_rate        828 drivers/clk/tegra/clk.h u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate);
input_rate        193 sound/pci/ctxfi/ctatc.c atc_get_pitch(unsigned int input_rate, unsigned int output_rate)
input_rate        199 sound/pci/ctxfi/ctatc.c 	pitch = (input_rate / output_rate) << 24;
input_rate        200 sound/pci/ctxfi/ctatc.c 	input_rate %= output_rate;
input_rate        201 sound/pci/ctxfi/ctatc.c 	input_rate /= 100;
input_rate        203 sound/pci/ctxfi/ctatc.c 	for (b = 31; ((b >= 0) && !(input_rate >> b)); )
input_rate        207 sound/pci/ctxfi/ctatc.c 		input_rate <<= (31 - b);
input_rate        208 sound/pci/ctxfi/ctatc.c 		input_rate /= output_rate;
input_rate        211 sound/pci/ctxfi/ctatc.c 			input_rate <<= b;
input_rate        213 sound/pci/ctxfi/ctatc.c 			input_rate >>= -b;
input_rate        215 sound/pci/ctxfi/ctatc.c 		pitch |= input_rate;
input_rate        314 sound/soc/stm/stm32_sai_sub.c 				 unsigned long input_rate,
input_rate        320 sound/soc/stm/stm32_sai_sub.c 	div = DIV_ROUND_CLOSEST(input_rate, output_rate);
input_rate        327 sound/soc/stm/stm32_sai_sub.c 	if (input_rate % div)
input_rate        330 sound/soc/stm/stm32_sai_sub.c 			output_rate, input_rate / div);