initial_state 269 arch/arm/mach-imx/mach-mx31ads.c .initial_state = PM_SUSPEND_MEM, initial_state 288 arch/arm/mach-imx/mach-mx31ads.c .initial_state = PM_SUSPEND_MEM, initial_state 305 arch/arm/mach-imx/mach-mx31ads.c .initial_state = PM_SUSPEND_MEM, initial_state 329 arch/arm/mach-imx/mach-mx31ads.c .initial_state = PM_SUSPEND_MEM, initial_state 424 arch/arm/mach-s3c64xx/mach-smdk6410.c .initial_state = PM_SUSPEND_MEM, initial_state 47 arch/mips/pmcs-msp71xx/msp_hwbutton.c int initial_state; /* The "normal" state of the switch */ initial_state 96 arch/mips/pmcs-msp71xx/msp_hwbutton.c .initial_state = HWBUTTON_HI, initial_state 106 arch/mips/pmcs-msp71xx/msp_hwbutton.c .initial_state = HWBUTTON_HI, initial_state 146 arch/mips/pmcs-msp71xx/msp_hwbutton.c if (hirq->initial_state == HWBUTTON_HI) initial_state 32 crypto/salsa20_generic.c u32 initial_state[16]; initial_state 106 crypto/salsa20_generic.c memcpy(state, ctx->initial_state, sizeof(ctx->initial_state)); initial_state 123 crypto/salsa20_generic.c ctx->initial_state[1] = get_unaligned_le32(key + 0); initial_state 124 crypto/salsa20_generic.c ctx->initial_state[2] = get_unaligned_le32(key + 4); initial_state 125 crypto/salsa20_generic.c ctx->initial_state[3] = get_unaligned_le32(key + 8); initial_state 126 crypto/salsa20_generic.c ctx->initial_state[4] = get_unaligned_le32(key + 12); initial_state 133 crypto/salsa20_generic.c ctx->initial_state[11] = get_unaligned_le32(key + 0); initial_state 134 crypto/salsa20_generic.c ctx->initial_state[12] = get_unaligned_le32(key + 4); initial_state 135 crypto/salsa20_generic.c ctx->initial_state[13] = get_unaligned_le32(key + 8); initial_state 136 crypto/salsa20_generic.c ctx->initial_state[14] = get_unaligned_le32(key + 12); initial_state 137 crypto/salsa20_generic.c ctx->initial_state[0] = get_unaligned_le32(constants + 0); initial_state 138 crypto/salsa20_generic.c ctx->initial_state[5] = get_unaligned_le32(constants + 4); initial_state 139 crypto/salsa20_generic.c ctx->initial_state[10] = get_unaligned_le32(constants + 8); initial_state 140 crypto/salsa20_generic.c ctx->initial_state[15] = get_unaligned_le32(constants + 12); initial_state 143 crypto/salsa20_generic.c ctx->initial_state[6] = 0; initial_state 144 crypto/salsa20_generic.c ctx->initial_state[7] = 0; initial_state 147 crypto/salsa20_generic.c ctx->initial_state[8] = 0; initial_state 148 crypto/salsa20_generic.c ctx->initial_state[9] = 0; initial_state 4834 drivers/gpu/drm/amd/amdgpu/si_dpm.c struct si_ps *initial_state = si_get_ps(amdgpu_initial_state); initial_state 4861 drivers/gpu/drm/amd/amdgpu/si_dpm.c cpu_to_be32(initial_state->performance_levels[0].mclk); initial_state 4877 drivers/gpu/drm/amd/amdgpu/si_dpm.c cpu_to_be32(initial_state->performance_levels[0].sclk); initial_state 4885 drivers/gpu/drm/amd/amdgpu/si_dpm.c initial_state->performance_levels[0].vddc, initial_state 4903 drivers/gpu/drm/amd/amdgpu/si_dpm.c initial_state->performance_levels[0].vddci, initial_state 4909 drivers/gpu/drm/amd/amdgpu/si_dpm.c initial_state->performance_levels[0].vddc, initial_state 4910 drivers/gpu/drm/amd/amdgpu/si_dpm.c initial_state->performance_levels[0].sclk, initial_state 4911 drivers/gpu/drm/amd/amdgpu/si_dpm.c initial_state->performance_levels[0].mclk, initial_state 4924 drivers/gpu/drm/amd/amdgpu/si_dpm.c initial_state->performance_levels[0].mclk); initial_state 4926 drivers/gpu/drm/amd/amdgpu/si_dpm.c if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) initial_state 1239 drivers/gpu/drm/radeon/cypress_dpm.c struct rv7xx_ps *initial_state = rv770_get_ps(radeon_initial_state); initial_state 1263 drivers/gpu/drm/radeon/cypress_dpm.c cpu_to_be32(initial_state->low.mclk); initial_state 1277 drivers/gpu/drm/radeon/cypress_dpm.c cpu_to_be32(initial_state->low.sclk); initial_state 1285 drivers/gpu/drm/radeon/cypress_dpm.c initial_state->low.vddc, initial_state 1291 drivers/gpu/drm/radeon/cypress_dpm.c initial_state->low.vddci, initial_state 1307 drivers/gpu/drm/radeon/cypress_dpm.c if (initial_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) initial_state 1315 drivers/gpu/drm/radeon/cypress_dpm.c initial_state->low.mclk); initial_state 1317 drivers/gpu/drm/radeon/cypress_dpm.c if (initial_state->low.mclk > pi->mclk_edc_enable_threshold) initial_state 1685 drivers/gpu/drm/radeon/ni_dpm.c struct ni_ps *initial_state = ni_get_ps(radeon_initial_state); initial_state 1709 drivers/gpu/drm/radeon/ni_dpm.c cpu_to_be32(initial_state->performance_levels[0].mclk); initial_state 1724 drivers/gpu/drm/radeon/ni_dpm.c cpu_to_be32(initial_state->performance_levels[0].sclk); initial_state 1731 drivers/gpu/drm/radeon/ni_dpm.c initial_state->performance_levels[0].vddc, initial_state 1748 drivers/gpu/drm/radeon/ni_dpm.c initial_state->performance_levels[0].vddci, initial_state 1766 drivers/gpu/drm/radeon/ni_dpm.c initial_state->performance_levels[0].mclk); initial_state 1768 drivers/gpu/drm/radeon/ni_dpm.c if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) initial_state 322 drivers/gpu/drm/radeon/rv730_dpm.c struct rv7xx_ps *initial_state = rv770_get_ps(radeon_state); initial_state 342 drivers/gpu/drm/radeon/rv730_dpm.c cpu_to_be32(initial_state->low.mclk); initial_state 356 drivers/gpu/drm/radeon/rv730_dpm.c cpu_to_be32(initial_state->low.sclk); initial_state 361 drivers/gpu/drm/radeon/rv730_dpm.c rv770_get_seq_value(rdev, &initial_state->low); initial_state 364 drivers/gpu/drm/radeon/rv730_dpm.c initial_state->low.vddc, initial_state 379 drivers/gpu/drm/radeon/rv730_dpm.c if (initial_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) initial_state 1026 drivers/gpu/drm/radeon/rv770_dpm.c struct rv7xx_ps *initial_state = rv770_get_ps(radeon_state); initial_state 1049 drivers/gpu/drm/radeon/rv770_dpm.c cpu_to_be32(initial_state->low.mclk); initial_state 1063 drivers/gpu/drm/radeon/rv770_dpm.c cpu_to_be32(initial_state->low.sclk); initial_state 1068 drivers/gpu/drm/radeon/rv770_dpm.c rv770_get_seq_value(rdev, &initial_state->low); initial_state 1071 drivers/gpu/drm/radeon/rv770_dpm.c initial_state->low.vddc, initial_state 1085 drivers/gpu/drm/radeon/rv770_dpm.c if (initial_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) initial_state 1092 drivers/gpu/drm/radeon/rv770_dpm.c if (initial_state->low.mclk <= pi->mclk_strobe_mode_threshold) initial_state 1094 drivers/gpu/drm/radeon/rv770_dpm.c rv740_get_mclk_frequency_ratio(initial_state->low.mclk) | 0x10; initial_state 1098 drivers/gpu/drm/radeon/rv770_dpm.c if (initial_state->low.mclk >= pi->mclk_edc_enable_threshold) initial_state 4370 drivers/gpu/drm/radeon/si_dpm.c struct ni_ps *initial_state = ni_get_ps(radeon_initial_state); initial_state 4397 drivers/gpu/drm/radeon/si_dpm.c cpu_to_be32(initial_state->performance_levels[0].mclk); initial_state 4413 drivers/gpu/drm/radeon/si_dpm.c cpu_to_be32(initial_state->performance_levels[0].sclk); initial_state 4421 drivers/gpu/drm/radeon/si_dpm.c initial_state->performance_levels[0].vddc, initial_state 4439 drivers/gpu/drm/radeon/si_dpm.c initial_state->performance_levels[0].vddci, initial_state 4445 drivers/gpu/drm/radeon/si_dpm.c initial_state->performance_levels[0].vddc, initial_state 4446 drivers/gpu/drm/radeon/si_dpm.c initial_state->performance_levels[0].sclk, initial_state 4447 drivers/gpu/drm/radeon/si_dpm.c initial_state->performance_levels[0].mclk, initial_state 4462 drivers/gpu/drm/radeon/si_dpm.c initial_state->performance_levels[0].mclk); initial_state 4464 drivers/gpu/drm/radeon/si_dpm.c if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) initial_state 113 drivers/i2c/muxes/i2c-mux-gpio.c unsigned initial_state; initial_state 157 drivers/i2c/muxes/i2c-mux-gpio.c initial_state = mux->data.idle; initial_state 160 drivers/i2c/muxes/i2c-mux-gpio.c initial_state = mux->data.values[0]; initial_state 168 drivers/i2c/muxes/i2c-mux-gpio.c if (initial_state & BIT(i)) initial_state 625 drivers/nvdimm/btt.c bool idx_set = false, initial_state = true; initial_state 689 drivers/nvdimm/btt.c initial_state = false; initial_state 693 drivers/nvdimm/btt.c if (!initial_state && !idx_set) initial_state 700 drivers/nvdimm/btt.c if (initial_state) initial_state 1316 drivers/regulator/core.c if (rdev->constraints->initial_state) { initial_state 1317 drivers/regulator/core.c ret = suspend_set_state(rdev, rdev->constraints->initial_state); initial_state 253 drivers/regulator/of_regulator.c constraints->initial_state = PM_SUSPEND_MEM; initial_state 150 drivers/scsi/isci/host.c const struct sci_base_state *state_table, u32 initial_state) initial_state 154 drivers/scsi/isci/host.c sm->initial_state_id = initial_state; initial_state 155 drivers/scsi/isci/host.c sm->previous_state_id = initial_state; initial_state 156 drivers/scsi/isci/host.c sm->current_state_id = initial_state; initial_state 159 drivers/scsi/isci/host.c handler = sm->state_table[initial_state].enter_state; initial_state 535 drivers/scsi/isci/isci.h u32 initial_state); initial_state 99 drivers/video/fbdev/nvidia/nv_type.h RIVA_HW_STATE initial_state; initial_state 1000 drivers/video/fbdev/nvidia/nvidia.c nvidia_save_vga(par, &par->initial_state); initial_state 1018 drivers/video/fbdev/nvidia/nvidia.c nvidia_write_regs(par, &par->initial_state); initial_state 1050 drivers/video/fbdev/riva/fbdev.c riva_save_state(par, &par->initial_state); initial_state 1070 drivers/video/fbdev/riva/fbdev.c par->riva.LoadStateExt(&par->riva, &par->initial_state.ext); initial_state 1071 drivers/video/fbdev/riva/fbdev.c riva_load_state(par, &par->initial_state); initial_state 51 drivers/video/fbdev/riva/rivafb.h struct riva_regs initial_state; /* initial startup video mode */ initial_state 174 include/linux/regulator/machine.h suspend_state_t initial_state; /* suspend state to set at init */ initial_state 510 kernel/livepatch/transition.c int initial_state = !state; initial_state 532 kernel/livepatch/transition.c task->patch_state = initial_state; initial_state 542 kernel/livepatch/transition.c task->patch_state = initial_state; initial_state 902 sound/firewire/amdtp-stream.c } *entry, initial_state[] = { initial_state 927 sound/firewire/amdtp-stream.c entry = &initial_state[s->sfc];