initial_offset    280 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	DC_LOG_DSC("\tinitial_offset %d", pps->initial_offset);
initial_offset    486 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	reg_vals->pps.initial_offset              = 6144;
initial_offset    603 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 		INITIAL_OFFSET, reg_vals->pps.initial_offset,
initial_offset     56 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c 	to->initial_offset           = from->initial_offset;
initial_offset     81 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c 	dsc_cfg->initial_offset         = rc->initial_fullness_offset;
initial_offset    176 drivers/gpu/drm/drm_dsc.c 	pps_payload->initial_offset =
initial_offset    177 drivers/gpu/drm/drm_dsc.c 		cpu_to_be16(dsc_cfg->initial_offset);
initial_offset    350 drivers/gpu/drm/drm_dsc.c 						    vdsc_cfg->initial_offset +
initial_offset    384 drivers/gpu/drm/drm_dsc.c 	rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset +
initial_offset     44 drivers/gpu/drm/i915/display/intel_vdsc.c 	u16 initial_offset;
initial_offset    413 drivers/gpu/drm/i915/display/intel_vdsc.c 	vdsc_cfg->initial_offset =
initial_offset    414 drivers/gpu/drm/i915/display/intel_vdsc.c 		rc_params[row_index][column_index].initial_offset;
initial_offset    454 drivers/gpu/drm/i915/display/intel_vdsc.c 		(vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
initial_offset    670 drivers/gpu/drm/i915/display/intel_vdsc.c 		DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset);
initial_offset   11377 drivers/gpu/drm/i915/i915_reg.h #define  DSC_INITIAL_OFFSET(initial_offset)		((initial_offset) << 16)
initial_offset     34 drivers/nvdimm/btt.c 	return offset + nd_btt->initial_offset;
initial_offset   1696 drivers/nvdimm/btt.c 	rawsize = nvdimm_namespace_capacity(ndns) - nd_btt->initial_offset;
initial_offset   1700 drivers/nvdimm/btt.c 				ARENA_MIN_SIZE + nd_btt->initial_offset);
initial_offset    276 drivers/nvdimm/btt_devs.c 		nd_btt->initial_offset = 0;
initial_offset    291 drivers/nvdimm/btt_devs.c 		nd_btt->initial_offset = SZ_4K;
initial_offset    189 drivers/nvdimm/nd.h 	int initial_offset;
initial_offset    172 include/drm/drm_dsc.h 	u16 initial_offset;
initial_offset    444 include/drm/drm_dsc.h 	__be16 initial_offset;