inc_base          728 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c 	uint32_t inc_base;
inc_base          957 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c 		inc_base = (src_bpc - dst_bpc);
inc_base          967 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c 				inc_base,
inc_base          996 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c 				inc_base,
inc_base         1025 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c 				inc_base,
inc_base         1030 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c 				inc_base + 2,
inc_base          859 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 	uint32_t inc_base;
inc_base         1030 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 		inc_base = (src_bpc - dst_bpc);
inc_base         1036 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 					CRTC_TEST_PATTERN_INC0, inc_base,
inc_base         1046 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 					CRTC_TEST_PATTERN_INC0, inc_base,
inc_base         1056 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 					CRTC_TEST_PATTERN_INC0, inc_base,
inc_base         1057 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 					CRTC_TEST_PATTERN_INC1, inc_base + 2,
inc_base          924 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 	uint32_t inc_base;
inc_base         1093 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 		inc_base = (src_bpc - dst_bpc);
inc_base         1099 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 					OTG_TEST_PATTERN_INC0, inc_base,
inc_base         1109 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 					OTG_TEST_PATTERN_INC0, inc_base,
inc_base         1119 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 					OTG_TEST_PATTERN_INC0, inc_base,
inc_base         1120 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 					OTG_TEST_PATTERN_INC1, inc_base + 2,
inc_base           68 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c 	uint32_t inc_base;
inc_base          198 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c 		inc_base = (src_bpc - dst_bpc);
inc_base          205 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c 				DPG_INC0, inc_base,
inc_base          216 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c 				DPG_INC0, inc_base,
inc_base          227 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c 				DPG_INC0, inc_base,
inc_base          228 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c 				DPG_INC1, inc_base + 2);