imr_val            84 arch/arm/mach-imx/3ds_debugboard.c 	u32 imr_val;
imr_val            91 arch/arm/mach-imx/3ds_debugboard.c 	imr_val = imx_readw(brd_io + INTR_MASK_REG);
imr_val            92 arch/arm/mach-imx/3ds_debugboard.c 	int_valid = imx_readw(brd_io + INTR_STATUS_REG) & ~imr_val;
imr_val           150 arch/arm/mach-imx/mach-mx31ads.c 	u32 imr_val;
imr_val           154 arch/arm/mach-imx/mach-mx31ads.c 	imr_val = imx_readw(PBC_INTMASK_SET_REG);
imr_val           155 arch/arm/mach-imx/mach-mx31ads.c 	int_valid = imx_readw(PBC_INTSTATUS_REG) & imr_val;
imr_val           241 drivers/gpu/drm/i915/i915_irq.c 		   i915_reg_t imr, u32 imr_val,
imr_val           248 drivers/gpu/drm/i915/i915_irq.c 	intel_uncore_write(uncore, imr, imr_val);
imr_val           253 drivers/gpu/drm/i915/i915_irq.c 		   u32 imr_val, u32 ier_val)
imr_val           258 drivers/gpu/drm/i915/i915_irq.c 	intel_uncore_write16(uncore, GEN2_IMR, imr_val);
imr_val           140 drivers/gpu/drm/i915/i915_irq.h 		   u32 imr_val, u32 ier_val);
imr_val           142 drivers/gpu/drm/i915/i915_irq.h 		   i915_reg_t imr, u32 imr_val,
imr_val           159 drivers/gpu/drm/i915/i915_irq.h #define GEN8_IRQ_INIT_NDX(uncore, type, which, imr_val, ier_val) \
imr_val           163 drivers/gpu/drm/i915/i915_irq.h 		      GEN8_##type##_IMR(which_), imr_val, \
imr_val           168 drivers/gpu/drm/i915/i915_irq.h #define GEN3_IRQ_INIT(uncore, type, imr_val, ier_val) \
imr_val           170 drivers/gpu/drm/i915/i915_irq.h 		      type##IMR, imr_val, \
imr_val           174 drivers/gpu/drm/i915/i915_irq.h #define GEN2_IRQ_INIT(uncore, imr_val, ier_val) \
imr_val           175 drivers/gpu/drm/i915/i915_irq.h 	gen2_irq_init((uncore), imr_val, ier_val)
imr_val           474 drivers/iio/adc/twl4030-madc.c 	u8 isr_val, imr_val;
imr_val           485 drivers/iio/adc/twl4030-madc.c 	ret = twl_i2c_read_u8(TWL4030_MODULE_MADC, &imr_val, madc->imr);
imr_val           491 drivers/iio/adc/twl4030-madc.c 	isr_val &= ~imr_val;