ih_cntl 62 drivers/gpu/drm/amd/amdgpu/cik_ih.c u32 ih_cntl = RREG32(mmIH_CNTL); ih_cntl 65 drivers/gpu/drm/amd/amdgpu/cik_ih.c ih_cntl |= IH_CNTL__ENABLE_INTR_MASK; ih_cntl 67 drivers/gpu/drm/amd/amdgpu/cik_ih.c WREG32(mmIH_CNTL, ih_cntl); ih_cntl 82 drivers/gpu/drm/amd/amdgpu/cik_ih.c u32 ih_cntl = RREG32(mmIH_CNTL); ih_cntl 85 drivers/gpu/drm/amd/amdgpu/cik_ih.c ih_cntl &= ~IH_CNTL__ENABLE_INTR_MASK; ih_cntl 87 drivers/gpu/drm/amd/amdgpu/cik_ih.c WREG32(mmIH_CNTL, ih_cntl); ih_cntl 110 drivers/gpu/drm/amd/amdgpu/cik_ih.c u32 interrupt_cntl, ih_cntl, ih_rb_cntl; ih_cntl 146 drivers/gpu/drm/amd/amdgpu/cik_ih.c ih_cntl = (0x10 << IH_CNTL__MC_WRREQ_CREDIT__SHIFT) | ih_cntl 151 drivers/gpu/drm/amd/amdgpu/cik_ih.c ih_cntl |= IH_CNTL__RPTR_REARM_MASK; ih_cntl 152 drivers/gpu/drm/amd/amdgpu/cik_ih.c WREG32(mmIH_CNTL, ih_cntl); ih_cntl 62 drivers/gpu/drm/amd/amdgpu/cz_ih.c u32 ih_cntl = RREG32(mmIH_CNTL); ih_cntl 65 drivers/gpu/drm/amd/amdgpu/cz_ih.c ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1); ih_cntl 67 drivers/gpu/drm/amd/amdgpu/cz_ih.c WREG32(mmIH_CNTL, ih_cntl); ih_cntl 82 drivers/gpu/drm/amd/amdgpu/cz_ih.c u32 ih_cntl = RREG32(mmIH_CNTL); ih_cntl 85 drivers/gpu/drm/amd/amdgpu/cz_ih.c ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0); ih_cntl 87 drivers/gpu/drm/amd/amdgpu/cz_ih.c WREG32(mmIH_CNTL, ih_cntl); ih_cntl 109 drivers/gpu/drm/amd/amdgpu/cz_ih.c u32 interrupt_cntl, ih_cntl, ih_rb_cntl; ih_cntl 148 drivers/gpu/drm/amd/amdgpu/cz_ih.c ih_cntl = RREG32(mmIH_CNTL); ih_cntl 149 drivers/gpu/drm/amd/amdgpu/cz_ih.c ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, MC_VMID, 0); ih_cntl 152 drivers/gpu/drm/amd/amdgpu/cz_ih.c ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, RPTR_REARM, 1); ih_cntl 153 drivers/gpu/drm/amd/amdgpu/cz_ih.c WREG32(mmIH_CNTL, ih_cntl); ih_cntl 62 drivers/gpu/drm/amd/amdgpu/iceland_ih.c u32 ih_cntl = RREG32(mmIH_CNTL); ih_cntl 65 drivers/gpu/drm/amd/amdgpu/iceland_ih.c ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1); ih_cntl 67 drivers/gpu/drm/amd/amdgpu/iceland_ih.c WREG32(mmIH_CNTL, ih_cntl); ih_cntl 82 drivers/gpu/drm/amd/amdgpu/iceland_ih.c u32 ih_cntl = RREG32(mmIH_CNTL); ih_cntl 85 drivers/gpu/drm/amd/amdgpu/iceland_ih.c ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0); ih_cntl 87 drivers/gpu/drm/amd/amdgpu/iceland_ih.c WREG32(mmIH_CNTL, ih_cntl); ih_cntl 110 drivers/gpu/drm/amd/amdgpu/iceland_ih.c u32 interrupt_cntl, ih_cntl, ih_rb_cntl; ih_cntl 148 drivers/gpu/drm/amd/amdgpu/iceland_ih.c ih_cntl = RREG32(mmIH_CNTL); ih_cntl 149 drivers/gpu/drm/amd/amdgpu/iceland_ih.c ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, MC_VMID, 0); ih_cntl 152 drivers/gpu/drm/amd/amdgpu/iceland_ih.c ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, RPTR_REARM, 1); ih_cntl 153 drivers/gpu/drm/amd/amdgpu/iceland_ih.c WREG32(mmIH_CNTL, ih_cntl); ih_cntl 35 drivers/gpu/drm/amd/amdgpu/si_ih.c u32 ih_cntl = RREG32(IH_CNTL); ih_cntl 38 drivers/gpu/drm/amd/amdgpu/si_ih.c ih_cntl |= ENABLE_INTR; ih_cntl 40 drivers/gpu/drm/amd/amdgpu/si_ih.c WREG32(IH_CNTL, ih_cntl); ih_cntl 48 drivers/gpu/drm/amd/amdgpu/si_ih.c u32 ih_cntl = RREG32(IH_CNTL); ih_cntl 51 drivers/gpu/drm/amd/amdgpu/si_ih.c ih_cntl &= ~ENABLE_INTR; ih_cntl 53 drivers/gpu/drm/amd/amdgpu/si_ih.c WREG32(IH_CNTL, ih_cntl); ih_cntl 64 drivers/gpu/drm/amd/amdgpu/si_ih.c u32 interrupt_cntl, ih_cntl, ih_rb_cntl; ih_cntl 88 drivers/gpu/drm/amd/amdgpu/si_ih.c ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0); ih_cntl 90 drivers/gpu/drm/amd/amdgpu/si_ih.c ih_cntl |= RPTR_REARM; ih_cntl 91 drivers/gpu/drm/amd/amdgpu/si_ih.c WREG32(IH_CNTL, ih_cntl); ih_cntl 6829 drivers/gpu/drm/radeon/cik.c u32 ih_cntl = RREG32(IH_CNTL); ih_cntl 6832 drivers/gpu/drm/radeon/cik.c ih_cntl |= ENABLE_INTR; ih_cntl 6834 drivers/gpu/drm/radeon/cik.c WREG32(IH_CNTL, ih_cntl); ih_cntl 6849 drivers/gpu/drm/radeon/cik.c u32 ih_cntl = RREG32(IH_CNTL); ih_cntl 6852 drivers/gpu/drm/radeon/cik.c ih_cntl &= ~ENABLE_INTR; ih_cntl 6854 drivers/gpu/drm/radeon/cik.c WREG32(IH_CNTL, ih_cntl); ih_cntl 6954 drivers/gpu/drm/radeon/cik.c u32 interrupt_cntl, ih_cntl, ih_rb_cntl; ih_cntl 7004 drivers/gpu/drm/radeon/cik.c ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0); ih_cntl 7007 drivers/gpu/drm/radeon/cik.c ih_cntl |= RPTR_REARM; ih_cntl 7008 drivers/gpu/drm/radeon/cik.c WREG32(IH_CNTL, ih_cntl); ih_cntl 3595 drivers/gpu/drm/radeon/r600.c u32 ih_cntl = RREG32(IH_CNTL); ih_cntl 3598 drivers/gpu/drm/radeon/r600.c ih_cntl |= ENABLE_INTR; ih_cntl 3600 drivers/gpu/drm/radeon/r600.c WREG32(IH_CNTL, ih_cntl); ih_cntl 3608 drivers/gpu/drm/radeon/r600.c u32 ih_cntl = RREG32(IH_CNTL); ih_cntl 3611 drivers/gpu/drm/radeon/r600.c ih_cntl &= ~ENABLE_INTR; ih_cntl 3613 drivers/gpu/drm/radeon/r600.c WREG32(IH_CNTL, ih_cntl); ih_cntl 3678 drivers/gpu/drm/radeon/r600.c u32 interrupt_cntl, ih_cntl, ih_rb_cntl; ih_cntl 3731 drivers/gpu/drm/radeon/r600.c ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10); ih_cntl 3734 drivers/gpu/drm/radeon/r600.c ih_cntl |= RPTR_REARM; ih_cntl 3735 drivers/gpu/drm/radeon/r600.c WREG32(IH_CNTL, ih_cntl); ih_cntl 5922 drivers/gpu/drm/radeon/si.c u32 ih_cntl = RREG32(IH_CNTL); ih_cntl 5925 drivers/gpu/drm/radeon/si.c ih_cntl |= ENABLE_INTR; ih_cntl 5927 drivers/gpu/drm/radeon/si.c WREG32(IH_CNTL, ih_cntl); ih_cntl 5935 drivers/gpu/drm/radeon/si.c u32 ih_cntl = RREG32(IH_CNTL); ih_cntl 5938 drivers/gpu/drm/radeon/si.c ih_cntl &= ~ENABLE_INTR; ih_cntl 5940 drivers/gpu/drm/radeon/si.c WREG32(IH_CNTL, ih_cntl); ih_cntl 5982 drivers/gpu/drm/radeon/si.c u32 interrupt_cntl, ih_cntl, ih_rb_cntl; ih_cntl 6032 drivers/gpu/drm/radeon/si.c ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0); ih_cntl 6035 drivers/gpu/drm/radeon/si.c ih_cntl |= RPTR_REARM; ih_cntl 6036 drivers/gpu/drm/radeon/si.c WREG32(IH_CNTL, ih_cntl);