ih1               171 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c 	amdgpu_ih_process(adev, &adev->irq.ih1);
ih1                91 drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h 	struct amdgpu_ih_ring		ih, ih1, ih2;
ih1                63 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	if (adev->irq.ih1.ring_size) {
ih1                76 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		adev->irq.ih1.enabled = true;
ih1               124 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	if (adev->irq.ih1.ring_size) {
ih1               140 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		adev->irq.ih1.enabled = false;
ih1               141 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		adev->irq.ih1.rptr = 0;
ih1               274 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	ih = &adev->irq.ih1;
ih1               387 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	else if (ih == &adev->irq.ih1)
ih1               412 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	else if (ih == &adev->irq.ih1)
ih1               485 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	else if (ih == &adev->irq.ih1)
ih1               521 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	} else if (ih == &adev->irq.ih1) {
ih1               545 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 		*adev->irq.ih1.wptr_cpu = wptr;
ih1               593 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true);
ih1               597 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	adev->irq.ih1.use_doorbell = true;
ih1               598 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1;
ih1               618 drivers/gpu/drm/amd/amdgpu/vega10_ih.c 	amdgpu_ih_ring_fini(adev, &adev->irq.ih1);