idx_value        1782 drivers/gpu/drm/radeon/evergreen_cs.c 	u32 idx_value;
idx_value        1787 drivers/gpu/drm/radeon/evergreen_cs.c 	idx_value = radeon_get_ib_value(p, idx);
idx_value        1820 drivers/gpu/drm/radeon/evergreen_cs.c 			 (idx_value & 0xfffffff0) +
idx_value        1866 drivers/gpu/drm/radeon/evergreen_cs.c 			 idx_value +
idx_value        1901 drivers/gpu/drm/radeon/evergreen_cs.c 			 idx_value +
idx_value        2012 drivers/gpu/drm/radeon/evergreen_cs.c 		if (idx_value != 1) {
idx_value        2045 drivers/gpu/drm/radeon/evergreen_cs.c 		if (idx_value + size > track->indirect_draw_buffer_size) {
idx_value        2047 drivers/gpu/drm/radeon/evergreen_cs.c 				idx_value, size, track->indirect_draw_buffer_size);
idx_value        2079 drivers/gpu/drm/radeon/evergreen_cs.c 		ib[idx+0] = idx_value + (u32)(reloc->gpu_offset & 0xffffffff);
idx_value        2092 drivers/gpu/drm/radeon/evergreen_cs.c 		if (idx_value & 0x10) {
idx_value        2107 drivers/gpu/drm/radeon/evergreen_cs.c 		} else if (idx_value & 0x100) {
idx_value        2301 drivers/gpu/drm/radeon/evergreen_cs.c 		start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
idx_value        2318 drivers/gpu/drm/radeon/evergreen_cs.c 		start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_START;
idx_value        2339 drivers/gpu/drm/radeon/evergreen_cs.c 		start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_START;
idx_value        2442 drivers/gpu/drm/radeon/evergreen_cs.c 		start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_START;
idx_value        2452 drivers/gpu/drm/radeon/evergreen_cs.c 		start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_START;
idx_value        2462 drivers/gpu/drm/radeon/evergreen_cs.c 		start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_START;
idx_value        2476 drivers/gpu/drm/radeon/evergreen_cs.c 		start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_START;
idx_value        2491 drivers/gpu/drm/radeon/evergreen_cs.c 		if (idx_value & 0x1) {
idx_value        2510 drivers/gpu/drm/radeon/evergreen_cs.c 		if (((idx_value >> 1) & 0x3) == 2) {
idx_value        2563 drivers/gpu/drm/radeon/evergreen_cs.c 		if (idx_value & 0x1) {
idx_value        2590 drivers/gpu/drm/radeon/evergreen_cs.c 		if (idx_value & 0x2) {
idx_value        2632 drivers/gpu/drm/radeon/evergreen_cs.c 		areg = idx_value >> 16;
idx_value        2639 drivers/gpu/drm/radeon/evergreen_cs.c 		source_sel = G_PACKET3_SET_APPEND_CNT_SRC_SELECT(idx_value);
idx_value        3352 drivers/gpu/drm/radeon/evergreen_cs.c 	u32 idx_value = ib[idx];
idx_value        3360 drivers/gpu/drm/radeon/evergreen_cs.c 		if (idx_value != 1) {
idx_value        3408 drivers/gpu/drm/radeon/evergreen_cs.c 		if (idx_value & 0x100) {
idx_value        3415 drivers/gpu/drm/radeon/evergreen_cs.c 		if (idx_value & 0x2) {
idx_value        3422 drivers/gpu/drm/radeon/evergreen_cs.c 		start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
idx_value        3454 drivers/gpu/drm/radeon/evergreen_cs.c 				start_reg = idx_value << 2;
idx_value        3507 drivers/gpu/drm/radeon/evergreen_cs.c 		areg = idx_value >> 16;
idx_value        1310 drivers/gpu/drm/radeon/r100.c 	u32 idx_value;
idx_value        1330 drivers/gpu/drm/radeon/r100.c 		idx_value = radeon_get_ib_value(p, idx);
idx_value        1333 drivers/gpu/drm/radeon/r100.c 		track->arrays[i + 0].esize = idx_value >> 8;
idx_value        1345 drivers/gpu/drm/radeon/r100.c 		track->arrays[i + 1].esize = idx_value >> 24;
idx_value        1356 drivers/gpu/drm/radeon/r100.c 		idx_value = radeon_get_ib_value(p, idx);
idx_value        1359 drivers/gpu/drm/radeon/r100.c 		track->arrays[i + 0].esize = idx_value >> 8;
idx_value        1562 drivers/gpu/drm/radeon/r100.c 	u32 idx_value;
idx_value        1567 drivers/gpu/drm/radeon/r100.c 	idx_value = radeon_get_ib_value(p, idx);
idx_value        1596 drivers/gpu/drm/radeon/r100.c 		track->zb.offset = idx_value;
idx_value        1598 drivers/gpu/drm/radeon/r100.c 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);
idx_value        1609 drivers/gpu/drm/radeon/r100.c 		track->cb[0].offset = idx_value;
idx_value        1611 drivers/gpu/drm/radeon/r100.c 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);
idx_value        1630 drivers/gpu/drm/radeon/r100.c 			tmp = idx_value & ~(0x7 << 2);
idx_value        1634 drivers/gpu/drm/radeon/r100.c 			ib[idx] = idx_value + ((u32)reloc->gpu_offset);
idx_value        1651 drivers/gpu/drm/radeon/r100.c 		track->textures[0].cube_info[i].offset = idx_value;
idx_value        1652 drivers/gpu/drm/radeon/r100.c 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);
idx_value        1669 drivers/gpu/drm/radeon/r100.c 		track->textures[1].cube_info[i].offset = idx_value;
idx_value        1670 drivers/gpu/drm/radeon/r100.c 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);
idx_value        1687 drivers/gpu/drm/radeon/r100.c 		track->textures[2].cube_info[i].offset = idx_value;
idx_value        1688 drivers/gpu/drm/radeon/r100.c 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);
idx_value        1693 drivers/gpu/drm/radeon/r100.c 		track->maxy = ((idx_value >> 16) & 0x7FF);
idx_value        1711 drivers/gpu/drm/radeon/r100.c 			tmp = idx_value & ~(0x7 << 16);
idx_value        1715 drivers/gpu/drm/radeon/r100.c 			ib[idx] = idx_value;
idx_value        1717 drivers/gpu/drm/radeon/r100.c 		track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
idx_value        1721 drivers/gpu/drm/radeon/r100.c 		track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
idx_value        1725 drivers/gpu/drm/radeon/r100.c 		switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
idx_value        1743 drivers/gpu/drm/radeon/r100.c 				  ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
idx_value        1746 drivers/gpu/drm/radeon/r100.c 		track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
idx_value        1751 drivers/gpu/drm/radeon/r100.c 		switch (idx_value & 0xf) {
idx_value        1776 drivers/gpu/drm/radeon/r100.c 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);
idx_value        1780 drivers/gpu/drm/radeon/r100.c 			uint32_t temp = idx_value >> 4;
idx_value        1787 drivers/gpu/drm/radeon/r100.c 		track->vap_vf_cntl = idx_value;
idx_value        1790 drivers/gpu/drm/radeon/r100.c 		track->vtx_size = r100_get_vtx_size(idx_value);
idx_value        1796 drivers/gpu/drm/radeon/r100.c 		track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
idx_value        1797 drivers/gpu/drm/radeon/r100.c 		track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
idx_value        1804 drivers/gpu/drm/radeon/r100.c 		track->textures[i].pitch = idx_value + 32;
idx_value        1811 drivers/gpu/drm/radeon/r100.c 		track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
idx_value        1813 drivers/gpu/drm/radeon/r100.c 		tmp = (idx_value >> 23) & 0x7;
idx_value        1816 drivers/gpu/drm/radeon/r100.c 		tmp = (idx_value >> 27) & 0x7;
idx_value        1825 drivers/gpu/drm/radeon/r100.c 		if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
idx_value        1829 drivers/gpu/drm/radeon/r100.c 			track->textures[i].width = 1 << ((idx_value & RADEON_TXFORMAT_WIDTH_MASK) >> RADEON_TXFORMAT_WIDTH_SHIFT);
idx_value        1830 drivers/gpu/drm/radeon/r100.c 			track->textures[i].height = 1 << ((idx_value & RADEON_TXFORMAT_HEIGHT_MASK) >> RADEON_TXFORMAT_HEIGHT_SHIFT);
idx_value        1832 drivers/gpu/drm/radeon/r100.c 		if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
idx_value        1834 drivers/gpu/drm/radeon/r100.c 		switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
idx_value        1870 drivers/gpu/drm/radeon/r100.c 		track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
idx_value        1871 drivers/gpu/drm/radeon/r100.c 		track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
idx_value        1877 drivers/gpu/drm/radeon/r100.c 		tmp = idx_value;
idx_value         157 drivers/gpu/drm/radeon/r200.c 	u32 idx_value;
idx_value         161 drivers/gpu/drm/radeon/r200.c 	idx_value = radeon_get_ib_value(p, idx);
idx_value         189 drivers/gpu/drm/radeon/r200.c 		track->zb.offset = idx_value;
idx_value         191 drivers/gpu/drm/radeon/r200.c 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);
idx_value         202 drivers/gpu/drm/radeon/r200.c 		track->cb[0].offset = idx_value;
idx_value         204 drivers/gpu/drm/radeon/r200.c 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);
idx_value         226 drivers/gpu/drm/radeon/r200.c 			tmp = idx_value & ~(0x7 << 2);
idx_value         230 drivers/gpu/drm/radeon/r200.c 			ib[idx] = idx_value + ((u32)reloc->gpu_offset);
idx_value         273 drivers/gpu/drm/radeon/r200.c 		track->textures[i].cube_info[face - 1].offset = idx_value;
idx_value         274 drivers/gpu/drm/radeon/r200.c 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);
idx_value         279 drivers/gpu/drm/radeon/r200.c 		track->maxy = ((idx_value >> 16) & 0x7FF);
idx_value         298 drivers/gpu/drm/radeon/r200.c 			tmp = idx_value & ~(0x7 << 16);
idx_value         302 drivers/gpu/drm/radeon/r200.c 			ib[idx] = idx_value;
idx_value         304 drivers/gpu/drm/radeon/r200.c 		track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
idx_value         308 drivers/gpu/drm/radeon/r200.c 		track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
idx_value         312 drivers/gpu/drm/radeon/r200.c 		switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
idx_value         330 drivers/gpu/drm/radeon/r200.c 				  ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
idx_value         333 drivers/gpu/drm/radeon/r200.c 		if (idx_value & RADEON_DEPTHXY_OFFSET_ENABLE) {
idx_value         338 drivers/gpu/drm/radeon/r200.c 		track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
idx_value         343 drivers/gpu/drm/radeon/r200.c 		switch (idx_value & 0xf) {
idx_value         368 drivers/gpu/drm/radeon/r200.c 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);
idx_value         372 drivers/gpu/drm/radeon/r200.c 			uint32_t temp = idx_value >> 4;
idx_value         379 drivers/gpu/drm/radeon/r200.c 		track->vap_vf_cntl = idx_value;
idx_value         383 drivers/gpu/drm/radeon/r200.c 		track->max_indx = idx_value & 0x00FFFFFFUL;
idx_value         386 drivers/gpu/drm/radeon/r200.c 		track->vtx_size = r200_get_vtx_size_0(idx_value);
idx_value         389 drivers/gpu/drm/radeon/r200.c 		track->vtx_size += r200_get_vtx_size_1(idx_value);
idx_value         398 drivers/gpu/drm/radeon/r200.c 		track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
idx_value         399 drivers/gpu/drm/radeon/r200.c 		track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
idx_value         409 drivers/gpu/drm/radeon/r200.c 		track->textures[i].pitch = idx_value + 32;
idx_value         419 drivers/gpu/drm/radeon/r200.c 		track->textures[i].num_levels = ((idx_value & R200_MAX_MIP_LEVEL_MASK)
idx_value         421 drivers/gpu/drm/radeon/r200.c 		tmp = (idx_value >> 23) & 0x7;
idx_value         424 drivers/gpu/drm/radeon/r200.c 		tmp = (idx_value >> 27) & 0x7;
idx_value         444 drivers/gpu/drm/radeon/r200.c 		track->textures[i].txdepth = idx_value & 0x7;
idx_value         445 drivers/gpu/drm/radeon/r200.c 		tmp = (idx_value >> 16) & 0x3;
idx_value         475 drivers/gpu/drm/radeon/r200.c 		if (idx_value & R200_TXFORMAT_NON_POWER2) {
idx_value         479 drivers/gpu/drm/radeon/r200.c 			track->textures[i].width = 1 << ((idx_value & RADEON_TXFORMAT_WIDTH_MASK) >> RADEON_TXFORMAT_WIDTH_SHIFT);
idx_value         480 drivers/gpu/drm/radeon/r200.c 			track->textures[i].height = 1 << ((idx_value & RADEON_TXFORMAT_HEIGHT_MASK) >> RADEON_TXFORMAT_HEIGHT_SHIFT);
idx_value         482 drivers/gpu/drm/radeon/r200.c 		if (idx_value & R200_TXFORMAT_LOOKUP_DISABLE)
idx_value         484 drivers/gpu/drm/radeon/r200.c 		switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
idx_value         521 drivers/gpu/drm/radeon/r200.c 		track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
idx_value         522 drivers/gpu/drm/radeon/r200.c 		track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
idx_value         531 drivers/gpu/drm/radeon/r200.c 		tmp = idx_value;
idx_value         641 drivers/gpu/drm/radeon/r300.c 	u32 idx_value;
idx_value         645 drivers/gpu/drm/radeon/r300.c 	idx_value = radeon_get_ib_value(p, idx);
idx_value         677 drivers/gpu/drm/radeon/r300.c 		track->cb[i].offset = idx_value;
idx_value         679 drivers/gpu/drm/radeon/r300.c 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);
idx_value         690 drivers/gpu/drm/radeon/r300.c 		track->zb.offset = idx_value;
idx_value         692 drivers/gpu/drm/radeon/r300.c 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);
idx_value         720 drivers/gpu/drm/radeon/r300.c 			ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */
idx_value         721 drivers/gpu/drm/radeon/r300.c 				  ((idx_value & ~31) + (u32)reloc->gpu_offset);
idx_value         730 drivers/gpu/drm/radeon/r300.c 			tmp = idx_value + ((u32)reloc->gpu_offset);
idx_value         740 drivers/gpu/drm/radeon/r300.c 		track->vap_vf_cntl = idx_value;
idx_value         744 drivers/gpu/drm/radeon/r300.c 		track->vtx_size = idx_value & 0x7F;
idx_value         748 drivers/gpu/drm/radeon/r300.c 		track->max_indx = idx_value & 0x00FFFFFFUL;
idx_value         754 drivers/gpu/drm/radeon/r300.c 		track->vap_alt_nverts = idx_value & 0xFFFFFF;
idx_value         758 drivers/gpu/drm/radeon/r300.c 		track->maxy = ((idx_value >> 13) & 0x1FFF) + 1;
idx_value         767 drivers/gpu/drm/radeon/r300.c 		if ((idx_value & (1 << 10)) && /* CMASK_ENABLE */
idx_value         772 drivers/gpu/drm/radeon/r300.c 		track->num_cb = ((idx_value >> 5) & 0x3) + 1;
idx_value         799 drivers/gpu/drm/radeon/r300.c 			tmp = idx_value & ~(0x7 << 16);
idx_value         804 drivers/gpu/drm/radeon/r300.c 		track->cb[i].pitch = idx_value & 0x3FFE;
idx_value         805 drivers/gpu/drm/radeon/r300.c 		switch (((idx_value >> 21) & 0xF)) {
idx_value         820 drivers/gpu/drm/radeon/r300.c 					  ((idx_value >> 21) & 0xF));
idx_value         835 drivers/gpu/drm/radeon/r300.c 				  ((idx_value >> 21) & 0xF));
idx_value         842 drivers/gpu/drm/radeon/r300.c 		if (idx_value & 2) {
idx_value         851 drivers/gpu/drm/radeon/r300.c 		switch ((idx_value & 0xF)) {
idx_value         861 drivers/gpu/drm/radeon/r300.c 				  (idx_value & 0xF));
idx_value         884 drivers/gpu/drm/radeon/r300.c 			tmp = idx_value & ~(0x7 << 16);
idx_value         888 drivers/gpu/drm/radeon/r300.c 		track->zb.pitch = idx_value & 0x3FFC;
idx_value         896 drivers/gpu/drm/radeon/r300.c 			enabled = !!(idx_value & (1 << i));
idx_value         919 drivers/gpu/drm/radeon/r300.c 		tmp = (idx_value >> 25) & 0x3;
idx_value         921 drivers/gpu/drm/radeon/r300.c 		switch ((idx_value & 0x1F)) {
idx_value         970 drivers/gpu/drm/radeon/r300.c 					  (idx_value & 0x1F));
idx_value         982 drivers/gpu/drm/radeon/r300.c 				  (idx_value & 0x1F));
idx_value        1005 drivers/gpu/drm/radeon/r300.c 		tmp = idx_value & 0x7;
idx_value        1009 drivers/gpu/drm/radeon/r300.c 		tmp = (idx_value >> 3) & 0x7;
idx_value        1033 drivers/gpu/drm/radeon/r300.c 		tmp = idx_value & 0x3FFF;
idx_value        1036 drivers/gpu/drm/radeon/r300.c 			tmp = ((idx_value >> 15) & 1) << 11;
idx_value        1038 drivers/gpu/drm/radeon/r300.c 			tmp = ((idx_value >> 16) & 1) << 11;
idx_value        1042 drivers/gpu/drm/radeon/r300.c 			if (idx_value & (1 << 14)) {
idx_value        1047 drivers/gpu/drm/radeon/r300.c 		} else if (idx_value & (1 << 14)) {
idx_value        1071 drivers/gpu/drm/radeon/r300.c 		tmp = idx_value & 0x7FF;
idx_value        1073 drivers/gpu/drm/radeon/r300.c 		tmp = (idx_value >> 11) & 0x7FF;
idx_value        1075 drivers/gpu/drm/radeon/r300.c 		tmp = (idx_value >> 26) & 0xF;
idx_value        1077 drivers/gpu/drm/radeon/r300.c 		tmp = idx_value & (1 << 31);
idx_value        1079 drivers/gpu/drm/radeon/r300.c 		tmp = (idx_value >> 22) & 0xF;
idx_value        1091 drivers/gpu/drm/radeon/r300.c 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);
idx_value        1095 drivers/gpu/drm/radeon/r300.c 		track->color_channel_mask = idx_value;
idx_value        1103 drivers/gpu/drm/radeon/r300.c 			if (idx_value & 0x1)
idx_value        1104 drivers/gpu/drm/radeon/r300.c 				ib[idx] = idx_value & ~1;
idx_value        1109 drivers/gpu/drm/radeon/r300.c 		track->zb_cb_clear = !!(idx_value & (1 << 5));
idx_value        1113 drivers/gpu/drm/radeon/r300.c 			if (idx_value & (R300_HIZ_ENABLE |
idx_value        1122 drivers/gpu/drm/radeon/r300.c 		track->blend_read_enable = !!(idx_value & (1 << 2));
idx_value        1134 drivers/gpu/drm/radeon/r300.c 		track->aa.offset = idx_value;
idx_value        1136 drivers/gpu/drm/radeon/r300.c 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);
idx_value        1139 drivers/gpu/drm/radeon/r300.c 		track->aa.pitch = idx_value & 0x3FFE;
idx_value        1143 drivers/gpu/drm/radeon/r300.c 		track->aaresolve = idx_value & 0x1;
idx_value        1150 drivers/gpu/drm/radeon/r300.c 		if (idx_value && (p->rdev->hyperz_filp != p->filp))
idx_value        1154 drivers/gpu/drm/radeon/r300.c 		if (idx_value && (p->rdev->hyperz_filp != p->filp))
idx_value        1172 drivers/gpu/drm/radeon/r300.c 	       reg, idx, idx_value);
idx_value        1636 drivers/gpu/drm/radeon/r600_cs.c 	u32 idx_value;
idx_value        1641 drivers/gpu/drm/radeon/r600_cs.c 	idx_value = radeon_get_ib_value(p, idx);
idx_value        1674 drivers/gpu/drm/radeon/r600_cs.c 			 (idx_value & 0xfffffff0) +
idx_value        1715 drivers/gpu/drm/radeon/r600_cs.c 			 idx_value +
idx_value        1757 drivers/gpu/drm/radeon/r600_cs.c 		if (idx_value & 0x10) {
idx_value        1772 drivers/gpu/drm/radeon/r600_cs.c 		} else if (idx_value & 0x100) {
idx_value        1909 drivers/gpu/drm/radeon/r600_cs.c 		start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET;
idx_value        1925 drivers/gpu/drm/radeon/r600_cs.c 		start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET;
idx_value        1945 drivers/gpu/drm/radeon/r600_cs.c 		start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET;
idx_value        2025 drivers/gpu/drm/radeon/r600_cs.c 			start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET;
idx_value        2036 drivers/gpu/drm/radeon/r600_cs.c 		start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_OFFSET;
idx_value        2046 drivers/gpu/drm/radeon/r600_cs.c 		start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_OFFSET;
idx_value        2056 drivers/gpu/drm/radeon/r600_cs.c 		start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_OFFSET;
idx_value        2070 drivers/gpu/drm/radeon/r600_cs.c 		start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_OFFSET;
idx_value        2089 drivers/gpu/drm/radeon/r600_cs.c 		if (idx_value > 3) {
idx_value        2102 drivers/gpu/drm/radeon/r600_cs.c 			if (reloc->robj != track->vgt_strmout_bo[idx_value]) {
idx_value        2108 drivers/gpu/drm/radeon/r600_cs.c 			if (offset != track->vgt_strmout_bo_offset[idx_value]) {
idx_value        2110 drivers/gpu/drm/radeon/r600_cs.c 					  offset, track->vgt_strmout_bo_offset[idx_value]);
idx_value        2138 drivers/gpu/drm/radeon/r600_cs.c 		if (idx_value & 0x1) {
idx_value        2157 drivers/gpu/drm/radeon/r600_cs.c 		if (((idx_value >> 1) & 0x3) == 2) {
idx_value        2210 drivers/gpu/drm/radeon/r600_cs.c 		if (idx_value & 0x1) {
idx_value        2234 drivers/gpu/drm/radeon/r600_cs.c 		if (idx_value & 0x2) {
idx_value        2384 drivers/gpu/drm/radeon/r600_cs.c 	u32 idx, idx_value;
idx_value        2439 drivers/gpu/drm/radeon/r600_cs.c 				idx_value = radeon_get_ib_value(p, idx + 2);
idx_value        2441 drivers/gpu/drm/radeon/r600_cs.c 				if (idx_value & (1 << 31)) {
idx_value        4484 drivers/gpu/drm/radeon/si.c 	u32 idx_value = ib[idx];
idx_value        4488 drivers/gpu/drm/radeon/si.c 			start_reg = idx_value << 2;
idx_value        4535 drivers/gpu/drm/radeon/si.c 	u32 idx_value = ib[idx];
idx_value        4586 drivers/gpu/drm/radeon/si.c 		if ((idx_value & 0xf00) == 0) {
idx_value        4593 drivers/gpu/drm/radeon/si.c 		if ((idx_value & 0xf00) == 0) {
idx_value        4595 drivers/gpu/drm/radeon/si.c 			if (idx_value & 0x10000) {
idx_value        4608 drivers/gpu/drm/radeon/si.c 		if (idx_value & 0x100) {
idx_value        4615 drivers/gpu/drm/radeon/si.c 		if (idx_value & 0x2) {
idx_value        4622 drivers/gpu/drm/radeon/si.c 		start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
idx_value        4653 drivers/gpu/drm/radeon/si.c 	u32 idx_value = ib[idx];
idx_value        4689 drivers/gpu/drm/radeon/si.c 		if ((idx_value & 0xf00) == 0) {
idx_value        4696 drivers/gpu/drm/radeon/si.c 		if ((idx_value & 0xf00) == 0) {
idx_value        4698 drivers/gpu/drm/radeon/si.c 			if (idx_value & 0x10000) {
idx_value        4711 drivers/gpu/drm/radeon/si.c 		if (idx_value & 0x100) {
idx_value        4718 drivers/gpu/drm/radeon/si.c 		if (idx_value & 0x2) {