idf 48 drivers/clk/st/clkgen-pll.c struct clkgen_field idf; idf 70 drivers/clk/st/clkgen-pll.c .idf = CLKGEN_FIELD(0x2a4, C32_IDF_MASK, 0x0), idf 83 drivers/clk/st/clkgen-pll.c .idf = CLKGEN_FIELD(0x2cc, C32_IDF_MASK, 0x0), idf 96 drivers/clk/st/clkgen-pll.c .idf = CLKGEN_FIELD(0x1a8, C32_IDF_MASK, 25), idf 113 drivers/clk/st/clkgen-pll.c .idf = CLKGEN_FIELD(0x1a8, C28_IDF_MASK, 25), idf 149 drivers/clk/st/clkgen-pll.c u32 idf; idf 161 drivers/clk/st/clkgen-pll.c unsigned long idf; idf 287 drivers/clk/st/clkgen-pll.c pll->idf = i; idf 306 drivers/clk/st/clkgen-pll.c if (!pll->idf) idf 307 drivers/clk/st/clkgen-pll.c pll->idf = 1; idf 309 drivers/clk/st/clkgen-pll.c *rate = ((2 * (input / 1000) * pll->ndiv) / pll->idf) * 1000; idf 318 drivers/clk/st/clkgen-pll.c unsigned long ndiv, idf; idf 325 drivers/clk/st/clkgen-pll.c idf = CLKGEN_READ(pll, idf); idf 327 drivers/clk/st/clkgen-pll.c if (idf) idf 329 drivers/clk/st/clkgen-pll.c rate = ((2 * (parent_rate/1000) * ndiv) / idf) * 1000; idf 352 drivers/clk/st/clkgen-pll.c (unsigned int)params.idf); idf 374 drivers/clk/st/clkgen-pll.c (unsigned int)params.idf); idf 380 drivers/clk/st/clkgen-pll.c pll->idf = params.idf; idf 389 drivers/clk/st/clkgen-pll.c CLKGEN_WRITE(pll, idf, pll->idf); idf 446 drivers/clk/st/clkgen-pll.c pll->idf = i; idf 462 drivers/clk/st/clkgen-pll.c if (!pll->idf) idf 463 drivers/clk/st/clkgen-pll.c pll->idf = 1; idf 465 drivers/clk/st/clkgen-pll.c *rate = (input / pll->idf) * 2 * pll->ndiv; idf 481 drivers/clk/st/clkgen-pll.c params.idf = CLKGEN_READ(pll, idf); idf 506 drivers/clk/st/clkgen-pll.c (unsigned int)params.idf); idf 533 drivers/clk/st/clkgen-pll.c (unsigned int)params.idf); idf 539 drivers/clk/st/clkgen-pll.c pll->idf = params.idf; idf 547 drivers/clk/st/clkgen-pll.c CLKGEN_WRITE(pll, idf, pll->idf); idf 280 drivers/gpu/drm/i915/display/dvo_ch7xxx.c u8 tvco, tpcp, tpd, tlpf, idf; idf 302 drivers/gpu/drm/i915/display/dvo_ch7xxx.c ch7xxx_readb(dvo, CH7xxx_IDF, &idf); idf 304 drivers/gpu/drm/i915/display/dvo_ch7xxx.c idf &= ~(CH7xxx_IDF_HSP | CH7xxx_IDF_VSP); idf 306 drivers/gpu/drm/i915/display/dvo_ch7xxx.c idf |= CH7xxx_IDF_HSP; idf 309 drivers/gpu/drm/i915/display/dvo_ch7xxx.c idf |= CH7xxx_IDF_VSP; idf 311 drivers/gpu/drm/i915/display/dvo_ch7xxx.c ch7xxx_writeb(dvo, CH7xxx_IDF, idf); idf 47 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c uint32_t idf; idf 79 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c u32 val, tmdsck, idf, odf, pllctrl = 0; idf 88 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c idf = plldividers[i].idf; idf 110 drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c pllctrl |= idf << PLL_CFG_IDF_SHIFT; idf 130 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c static int dsi_pll_get_clkout_khz(int clkin_khz, int idf, int ndiv, int odf) idf 132 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c int divisor = idf * odf; idf 143 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c int *idf, int *ndiv, int *odf) idf 183 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c *idf = i; idf 246 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c unsigned int idf, ndiv, odf, pll_in_khz, pll_out_khz; idf 275 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c idf = 0; idf 279 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c &idf, &ndiv, &odf); idf 284 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c pll_out_khz = dsi_pll_get_clkout_khz(pll_in_khz, idf, ndiv, odf); idf 288 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c (ndiv << 2) | (idf << 11) | ((ffs(odf) - 1) << 16)); idf 803 drivers/media/dvb-frontends/stv0910.c u32 idf = 1; idf 807 drivers/media/dvb-frontends/stv0910.c u32 ndiv = (fphi * odf * idf) / quartz; idf 854 drivers/media/dvb-frontends/stv0910.c write_reg(state, RSTV0910_NCOARSE, (cp << 3) | idf); idf 858 drivers/media/dvb-frontends/stv0910.c fvco = (quartz * 2 * ndiv) / idf;