INPUT_GAMMA_CONTROL 2117 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
INPUT_GAMMA_CONTROL 2118 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 	tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, OVL_INPUT_GAMMA_MODE, 0);
INPUT_GAMMA_CONTROL 2154 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c 	tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
INPUT_GAMMA_CONTROL  166 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c 		REG_UPDATE(INPUT_GAMMA_CONTROL,
INPUT_GAMMA_CONTROL  216 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c 	REG_UPDATE(INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
INPUT_GAMMA_CONTROL   48 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h 	SRI(INPUT_GAMMA_CONTROL, DCP, id), \
INPUT_GAMMA_CONTROL   94 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h 	IPP_SF(INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, mask_sh), \
INPUT_GAMMA_CONTROL  212 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.h 	uint32_t INPUT_GAMMA_CONTROL;