icache 300 arch/arc/include/asm/arcregs.h struct cpuinfo_arc_cache icache, dcache, slc; icache 54 arch/arc/mm/cache.c PR_CACHE(&cpuinfo_arc700[c].icache, CONFIG_ARC_HAS_ICACHE, "I-Cache"); icache 154 arch/arc/mm/cache.c p_ic = &cpuinfo_arc700[cpu].icache; icache 1221 arch/arc/mm/cache.c struct cpuinfo_arc_cache *ic = &cpuinfo_arc700[cpu].icache; icache 235 arch/mips/include/asm/cpu-features.h #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) icache 241 arch/mips/include/asm/cpu-features.h #define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC) icache 260 arch/mips/include/asm/cpu-features.h #define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE) icache 488 arch/mips/include/asm/cpu-features.h #define cpu_icache_line_size() cpu_data[0].icache.linesz icache 75 arch/mips/include/asm/cpu-info.h struct cache_desc icache; /* Primary I-cache */ icache 1742 arch/mips/include/asm/octeon/cvmx-mio-defs.h uint64_t icache:24; icache 1744 arch/mips/include/asm/octeon/cvmx-mio-defs.h uint64_t icache:24; icache 1765 arch/mips/include/asm/octeon/cvmx-mio-defs.h uint64_t icache:24; icache 1767 arch/mips/include/asm/octeon/cvmx-mio-defs.h uint64_t icache:24; icache 1787 arch/mips/include/asm/octeon/cvmx-mio-defs.h uint64_t icache:24; icache 1789 arch/mips/include/asm/octeon/cvmx-mio-defs.h uint64_t icache:24; icache 1807 arch/mips/include/asm/octeon/cvmx-mio-defs.h uint64_t icache:24; icache 1809 arch/mips/include/asm/octeon/cvmx-mio-defs.h uint64_t icache:24; icache 572 arch/mips/include/asm/r4kcache.h __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, ) icache 575 arch/mips/include/asm/r4kcache.h __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, ) icache 576 arch/mips/include/asm/r4kcache.h __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I_Loongson2, 32, loongson2_) icache 579 arch/mips/include/asm/r4kcache.h __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, ) icache 582 arch/mips/include/asm/r4kcache.h __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, ) icache 606 arch/mips/include/asm/r4kcache.h __BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16) icache 609 arch/mips/include/asm/r4kcache.h __BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32) icache 612 arch/mips/include/asm/r4kcache.h __BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64) icache 634 arch/mips/include/asm/r4kcache.h __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, ) icache 665 arch/mips/include/asm/r4kcache.h __BUILD_PROT_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I) icache 669 arch/mips/include/asm/r4kcache.h __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson2, \ icache 672 arch/mips/include/asm/r4kcache.h __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, , ) icache 36 arch/mips/kernel/cacheinfo.c leaves += (c->icache.waysize) ? 2 : 1; icache 78 arch/mips/kernel/cacheinfo.c if (c->icache.waysize) { icache 83 arch/mips/kernel/cacheinfo.c populate_cache(icache, this_leaf, 1, CACHE_TYPE_INST); icache 468 arch/mips/kernel/pm-cps.c cps_gen_cache_routine(&p, &l, &r, &cpu_data[cpu].icache, icache 640 arch/mips/kernel/traps.c current_cpu_data.icache.linesz); icache 2534 arch/mips/kvm/emulate.c current_cpu_data.icache.linesz); icache 180 arch/mips/mm/c-octeon.c c->icache.linesz = 2 << ((config1 >> 19) & 7); icache 181 arch/mips/mm/c-octeon.c c->icache.sets = 64 << ((config1 >> 22) & 7); icache 182 arch/mips/mm/c-octeon.c c->icache.ways = 1 + ((config1 >> 16) & 7); icache 183 arch/mips/mm/c-octeon.c c->icache.flags |= MIPS_CACHE_VTAG; icache 185 arch/mips/mm/c-octeon.c c->icache.sets * c->icache.ways * c->icache.linesz; icache 186 arch/mips/mm/c-octeon.c c->icache.waybit = ffs(icache_size / c->icache.ways) - 1; icache 200 arch/mips/mm/c-octeon.c c->icache.linesz = 2 << ((config1 >> 19) & 7); icache 201 arch/mips/mm/c-octeon.c c->icache.sets = 8; icache 202 arch/mips/mm/c-octeon.c c->icache.ways = 37; icache 203 arch/mips/mm/c-octeon.c c->icache.flags |= MIPS_CACHE_VTAG; icache 204 arch/mips/mm/c-octeon.c icache_size = c->icache.sets * c->icache.ways * c->icache.linesz; icache 214 arch/mips/mm/c-octeon.c c->icache.linesz = 128; icache 215 arch/mips/mm/c-octeon.c c->icache.sets = 16; icache 216 arch/mips/mm/c-octeon.c c->icache.ways = 39; icache 217 arch/mips/mm/c-octeon.c c->icache.flags |= MIPS_CACHE_VTAG; icache 218 arch/mips/mm/c-octeon.c icache_size = c->icache.sets * c->icache.ways * c->icache.linesz; icache 233 arch/mips/mm/c-octeon.c c->icache.waysize = icache_size / c->icache.ways; icache 236 arch/mips/mm/c-octeon.c c->icache.sets = icache_size / (c->icache.linesz * c->icache.ways); icache 245 arch/mips/mm/c-octeon.c c->icache.ways, c->icache.sets, c->icache.linesz); icache 264 arch/mips/mm/c-r4k.c unsigned long end = start + current_cpu_data.icache.waysize; icache 265 arch/mips/mm/c-r4k.c unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; icache 266 arch/mips/mm/c-r4k.c unsigned long ws_end = current_cpu_data.icache.ways << icache 267 arch/mips/mm/c-r4k.c current_cpu_data.icache.waybit; icache 293 arch/mips/mm/c-r4k.c unsigned long indexmask = current_cpu_data.icache.waysize - 1; icache 296 arch/mips/mm/c-r4k.c unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit; icache 297 arch/mips/mm/c-r4k.c unsigned long ws_end = current_cpu_data.icache.ways << icache 298 arch/mips/mm/c-r4k.c current_cpu_data.icache.waybit; icache 1089 arch/mips/mm/c-r4k.c c->icache.linesz = 16 << ((config & CONF_IB) >> 5); icache 1090 arch/mips/mm/c-r4k.c c->icache.ways = 2; icache 1091 arch/mips/mm/c-r4k.c c->icache.waybit = __ffs(icache_size/2); icache 1103 arch/mips/mm/c-r4k.c c->icache.linesz = 16 << ((config & CONF_IB) >> 5); icache 1104 arch/mips/mm/c-r4k.c c->icache.ways = 2; icache 1105 arch/mips/mm/c-r4k.c c->icache.waybit= 0; icache 1117 arch/mips/mm/c-r4k.c c->icache.linesz = 16 << ((config & CONF_IB) >> 5); icache 1118 arch/mips/mm/c-r4k.c c->icache.ways = 4; icache 1119 arch/mips/mm/c-r4k.c c->icache.waybit= 0; icache 1137 arch/mips/mm/c-r4k.c c->icache.linesz = 16 << ((config & CONF_IB) >> 5); icache 1138 arch/mips/mm/c-r4k.c c->icache.ways = 1; icache 1139 arch/mips/mm/c-r4k.c c->icache.waybit = 0; /* doesn't matter */ icache 1154 arch/mips/mm/c-r4k.c c->icache.linesz = 64; icache 1155 arch/mips/mm/c-r4k.c c->icache.ways = 2; icache 1156 arch/mips/mm/c-r4k.c c->icache.waybit = 0; icache 1181 arch/mips/mm/c-r4k.c c->icache.linesz = 16 << ((config & CONF_IB) >> 5); icache 1182 arch/mips/mm/c-r4k.c c->icache.ways = 2; icache 1183 arch/mips/mm/c-r4k.c c->icache.waybit = __ffs(icache_size/2); icache 1198 arch/mips/mm/c-r4k.c c->icache.linesz = 16 << ((config & CONF_IB) >> 5); icache 1199 arch/mips/mm/c-r4k.c c->icache.ways = 1; icache 1200 arch/mips/mm/c-r4k.c c->icache.waybit = 0; /* doesn't matter */ icache 1214 arch/mips/mm/c-r4k.c c->icache.linesz = 16 << ((config & CONF_IB) >> 5); icache 1215 arch/mips/mm/c-r4k.c c->icache.ways = 4; icache 1216 arch/mips/mm/c-r4k.c c->icache.waybit = __ffs(icache_size / c->icache.ways); icache 1229 arch/mips/mm/c-r4k.c c->icache.linesz = 16 << ((config & CONF_IB) >> 5); icache 1231 arch/mips/mm/c-r4k.c c->icache.ways = 4; icache 1233 arch/mips/mm/c-r4k.c c->icache.ways = 2; icache 1234 arch/mips/mm/c-r4k.c c->icache.waybit = 0; icache 1249 arch/mips/mm/c-r4k.c c->icache.linesz = 2 << lsize; icache 1251 arch/mips/mm/c-r4k.c c->icache.linesz = 0; icache 1252 arch/mips/mm/c-r4k.c c->icache.sets = 64 << ((config1 >> 22) & 7); icache 1253 arch/mips/mm/c-r4k.c c->icache.ways = 1 + ((config1 >> 16) & 7); icache 1254 arch/mips/mm/c-r4k.c icache_size = c->icache.sets * icache 1255 arch/mips/mm/c-r4k.c c->icache.ways * icache 1256 arch/mips/mm/c-r4k.c c->icache.linesz; icache 1257 arch/mips/mm/c-r4k.c c->icache.waybit = 0; icache 1276 arch/mips/mm/c-r4k.c c->icache.linesz = 128; icache 1277 arch/mips/mm/c-r4k.c c->icache.sets = 16; icache 1278 arch/mips/mm/c-r4k.c c->icache.ways = 8; icache 1279 arch/mips/mm/c-r4k.c c->icache.flags |= MIPS_CACHE_VTAG; icache 1280 arch/mips/mm/c-r4k.c icache_size = c->icache.sets * c->icache.ways * c->icache.linesz; icache 1305 arch/mips/mm/c-r4k.c c->icache.linesz = lsize ? 2 << lsize : 0; icache 1307 arch/mips/mm/c-r4k.c c->icache.sets = 32 << (((config1 >> 22) + 1) & 7); icache 1308 arch/mips/mm/c-r4k.c c->icache.ways = 1 + ((config1 >> 16) & 7); icache 1310 arch/mips/mm/c-r4k.c icache_size = c->icache.sets * icache 1311 arch/mips/mm/c-r4k.c c->icache.ways * icache 1312 arch/mips/mm/c-r4k.c c->icache.linesz; icache 1313 arch/mips/mm/c-r4k.c c->icache.waybit = __ffs(icache_size/c->icache.ways); icache 1316 arch/mips/mm/c-r4k.c c->icache.flags |= MIPS_CACHE_VTAG; icache 1353 arch/mips/mm/c-r4k.c !(config & CONF_SC) && c->icache.linesz != 16 && icache 1358 arch/mips/mm/c-r4k.c c->icache.waysize = icache_size / c->icache.ways; icache 1361 arch/mips/mm/c-r4k.c c->icache.sets = c->icache.linesz ? icache 1362 arch/mips/mm/c-r4k.c icache_size / (c->icache.linesz * c->icache.ways) : 0; icache 1406 arch/mips/mm/c-r4k.c (c->icache.waysize > PAGE_SIZE)) icache 1407 arch/mips/mm/c-r4k.c c->icache.flags |= MIPS_CACHE_ALIASES; icache 1432 arch/mips/mm/c-r4k.c c->icache.flags |= MIPS_IC_SNOOPS_REMOTE; icache 1440 arch/mips/mm/c-r4k.c c->icache.flags |= MIPS_CACHE_VTAG; icache 1446 arch/mips/mm/c-r4k.c c->icache.flags |= MIPS_CACHE_IC_F_DC; icache 1450 arch/mips/mm/c-r4k.c c->icache.flags |= MIPS_CACHE_IC_F_DC; icache 1460 arch/mips/mm/c-r4k.c c->icache.ways = 1; icache 1465 arch/mips/mm/c-r4k.c c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT", icache 1466 arch/mips/mm/c-r4k.c way_string[c->icache.ways], c->icache.linesz); icache 304 arch/mips/mm/c-tx39.c current_cpu_data.icache.linesz = 16; icache 307 arch/mips/mm/c-tx39.c current_cpu_data.icache.ways = 1; icache 313 arch/mips/mm/c-tx39.c current_cpu_data.icache.ways = 2; icache 320 arch/mips/mm/c-tx39.c current_cpu_data.icache.ways = 1; icache 397 arch/mips/mm/c-tx39.c current_cpu_data.icache.waysize = icache_size / current_cpu_data.icache.ways; icache 400 arch/mips/mm/c-tx39.c current_cpu_data.icache.sets = icache 401 arch/mips/mm/c-tx39.c current_cpu_data.icache.waysize / current_cpu_data.icache.linesz; icache 408 arch/mips/mm/c-tx39.c current_cpu_data.icache.waybit = 0; icache 412 arch/mips/mm/c-tx39.c icache_size >> 10, current_cpu_data.icache.linesz); icache 363 arch/powerpc/kernel/cacheinfo.c struct cache *dcache, *icache; icache 369 arch/powerpc/kernel/cacheinfo.c icache = new_cache(CACHE_TYPE_INSTRUCTION, level, node); icache 371 arch/powerpc/kernel/cacheinfo.c if (!dcache || !icache) icache 374 arch/powerpc/kernel/cacheinfo.c dcache->next_local = icache; icache 379 arch/powerpc/kernel/cacheinfo.c release_cache(icache); icache 511 arch/powerpc/kernel/setup_64.c bool icache, icache 526 arch/powerpc/kernel/setup_64.c const char **propnames = icache ? ipropnames : dpropnames; icache 138 arch/powerpc/perf/power8-pmu.c CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS); icache 139 arch/powerpc/perf/power8-pmu.c CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1); icache 140 arch/powerpc/perf/power8-pmu.c CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_WRITE); icache 167 arch/powerpc/perf/power9-pmu.c CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS); icache 168 arch/powerpc/perf/power9-pmu.c CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1); icache 169 arch/powerpc/perf/power9-pmu.c CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_WRITE); icache 82 arch/sh/include/asm/processor.h struct cache_info icache; /* Primary I-cache */ icache 209 arch/sh/kernel/cpu/init.c l1i_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.icache); icache 306 arch/sh/kernel/cpu/init.c current_cpu_data.icache.entry_mask = current_cpu_data.icache.way_incr - icache 307 arch/sh/kernel/cpu/init.c current_cpu_data.icache.linesz; icache 309 arch/sh/kernel/cpu/init.c current_cpu_data.icache.way_size = current_cpu_data.icache.sets * icache 310 arch/sh/kernel/cpu/init.c current_cpu_data.icache.linesz; icache 112 arch/sh/kernel/cpu/proc.c if (c->icache.flags & SH_CACHE_COMBINED) { icache 114 arch/sh/kernel/cpu/proc.c show_cacheinfo(m, "cache", c->icache); icache 117 arch/sh/kernel/cpu/proc.c show_cacheinfo(m, "icache", c->icache); icache 69 arch/sh/kernel/cpu/sh2/probe.c boot_cpu_data.icache = boot_cpu_data.dcache; icache 56 arch/sh/kernel/cpu/sh2a/probe.c boot_cpu_data.icache = boot_cpu_data.dcache; icache 105 arch/sh/kernel/cpu/sh3/probe.c boot_cpu_data.icache = boot_cpu_data.dcache; icache 35 arch/sh/kernel/cpu/sh4/probe.c boot_cpu_data.icache.way_incr = (1 << 13); icache 36 arch/sh/kernel/cpu/sh4/probe.c boot_cpu_data.icache.entry_shift = 5; icache 37 arch/sh/kernel/cpu/sh4/probe.c boot_cpu_data.icache.sets = 256; icache 38 arch/sh/kernel/cpu/sh4/probe.c boot_cpu_data.icache.ways = 1; icache 39 arch/sh/kernel/cpu/sh4/probe.c boot_cpu_data.icache.linesz = L1_CACHE_BYTES; icache 67 arch/sh/kernel/cpu/sh4/probe.c boot_cpu_data.icache.ways = 4; icache 171 arch/sh/kernel/cpu/sh4/probe.c boot_cpu_data.icache.ways = 2; icache 176 arch/sh/kernel/cpu/sh4/probe.c boot_cpu_data.icache.ways = 2; icache 192 arch/sh/kernel/cpu/sh4/probe.c boot_cpu_data.icache.ways = 2; icache 202 arch/sh/kernel/cpu/sh4/probe.c if (boot_cpu_data.icache.ways > 1) { icache 204 arch/sh/kernel/cpu/sh4/probe.c boot_cpu_data.icache.way_incr = (size >> 1); icache 205 arch/sh/kernel/cpu/sh4/probe.c boot_cpu_data.icache.sets = (size >> 6); icache 39 arch/sh/kernel/cpu/sh5/probe.c boot_cpu_data.icache.ways = 4; icache 40 arch/sh/kernel/cpu/sh5/probe.c boot_cpu_data.icache.sets = 256; icache 41 arch/sh/kernel/cpu/sh5/probe.c boot_cpu_data.icache.linesz = L1_CACHE_BYTES; icache 42 arch/sh/kernel/cpu/sh5/probe.c boot_cpu_data.icache.way_incr = (1 << 13); icache 43 arch/sh/kernel/cpu/sh5/probe.c boot_cpu_data.icache.entry_shift = 5; icache 44 arch/sh/kernel/cpu/sh5/probe.c boot_cpu_data.icache.way_size = boot_cpu_data.icache.sets * icache 45 arch/sh/kernel/cpu/sh5/probe.c boot_cpu_data.icache.linesz; icache 46 arch/sh/kernel/cpu/sh5/probe.c boot_cpu_data.icache.entry_mask = 0x1fe0; icache 47 arch/sh/kernel/cpu/sh5/probe.c boot_cpu_data.icache.flags = 0; icache 59 arch/sh/kernel/cpu/sh5/probe.c boot_cpu_data.dcache = boot_cpu_data.icache; icache 52 arch/sh/mm/cache-debugfs.c cache = ¤t_cpu_data.icache; icache 74 arch/sh/mm/cache-sh4.c cpu_data->icache.entry_mask); icache 77 arch/sh/mm/cache-sh4.c n = boot_cpu_data.icache.n_aliases; icache 78 arch/sh/mm/cache-sh4.c for (i = 0; i < cpu_data->icache.ways; i++) { icache 81 arch/sh/mm/cache-sh4.c icacheaddr += cpu_data->icache.way_incr; icache 27 arch/sh/mm/cache-shx3.c if (boot_cpu_data.dcache.n_aliases || boot_cpu_data.icache.n_aliases) { icache 30 arch/sh/mm/cache-shx3.c boot_cpu_data.icache.n_aliases = 0; icache 260 arch/sh/mm/cache.c boot_cpu_data.icache.ways, icache 261 arch/sh/mm/cache.c boot_cpu_data.icache.sets, icache 262 arch/sh/mm/cache.c boot_cpu_data.icache.way_incr); icache 264 arch/sh/mm/cache.c boot_cpu_data.icache.entry_mask, icache 265 arch/sh/mm/cache.c boot_cpu_data.icache.alias_mask, icache 266 arch/sh/mm/cache.c boot_cpu_data.icache.n_aliases); icache 299 arch/sh/mm/cache.c compute_alias(&boot_cpu_data.icache); icache 733 drivers/perf/qcom_l2_pmu.c L2CACHE_EVENT_ATTR(icache-ops, L2_EVENT_ICACHE_OPS), icache 270 drivers/soc/bcm/brcmstb/pm/pm-mips.c s2_params[3] = (u32)current_cpu_data.icache.linesz;