i1 9 arch/arm/kernel/insn.c unsigned long s, j1, j2, i1, i2, imm10, imm11; i1 20 arch/arm/kernel/insn.c i1 = (offset >> 23) & 0x1; i1 25 arch/arm/kernel/insn.c j1 = (!i1) ^ s; i1 1330 arch/arm/kvm/coproc.c const struct coproc_reg *i1, *i2, *end1, *end2; i1 1335 arch/arm/kvm/coproc.c i1 = get_target_table(vcpu->arch.target, &num); i1 1336 arch/arm/kvm/coproc.c end1 = i1 + num; i1 1340 arch/arm/kvm/coproc.c BUG_ON(i1 == end1 || i2 == end2); i1 1343 arch/arm/kvm/coproc.c while (i1 || i2) { i1 1344 arch/arm/kvm/coproc.c int cmp = cmp_reg(i1, i2); i1 1348 arch/arm/kvm/coproc.c if (i1->reg) { i1 1349 arch/arm/kvm/coproc.c if (!copy_reg_to_user(i1, &uind)) i1 1362 arch/arm/kvm/coproc.c if (cmp <= 0 && ++i1 == end1) i1 1363 arch/arm/kvm/coproc.c i1 = NULL; i1 98 arch/arm/kvm/coproc.h static inline int cmp_reg(const struct coproc_reg *i1, i1 101 arch/arm/kvm/coproc.h BUG_ON(i1 == i2); i1 102 arch/arm/kvm/coproc.h if (!i1) i1 106 arch/arm/kvm/coproc.h if (i1->CRn != i2->CRn) i1 107 arch/arm/kvm/coproc.h return i1->CRn - i2->CRn; i1 108 arch/arm/kvm/coproc.h if (i1->CRm != i2->CRm) i1 109 arch/arm/kvm/coproc.h return i1->CRm - i2->CRm; i1 110 arch/arm/kvm/coproc.h if (i1->Op1 != i2->Op1) i1 111 arch/arm/kvm/coproc.h return i1->Op1 - i2->Op1; i1 112 arch/arm/kvm/coproc.h if (i1->Op2 != i2->Op2) i1 113 arch/arm/kvm/coproc.h return i1->Op2 - i2->Op2; i1 114 arch/arm/kvm/coproc.h return i2->is_64bit - i1->is_64bit; i1 2675 arch/arm64/kvm/sys_regs.c const struct sys_reg_desc *i1, *i2, *end1, *end2; i1 2681 arch/arm64/kvm/sys_regs.c i1 = get_target_table(vcpu->arch.target, true, &num); i1 2682 arch/arm64/kvm/sys_regs.c end1 = i1 + num; i1 2686 arch/arm64/kvm/sys_regs.c BUG_ON(i1 == end1 || i2 == end2); i1 2689 arch/arm64/kvm/sys_regs.c while (i1 || i2) { i1 2690 arch/arm64/kvm/sys_regs.c int cmp = cmp_sys_reg(i1, i2); i1 2693 arch/arm64/kvm/sys_regs.c err = walk_one_sys_reg(vcpu, i1, &uind, &total); i1 2700 arch/arm64/kvm/sys_regs.c if (cmp <= 0 && ++i1 == end1) i1 2701 arch/arm64/kvm/sys_regs.c i1 = NULL; i1 119 arch/arm64/kvm/sys_regs.h static inline int cmp_sys_reg(const struct sys_reg_desc *i1, i1 122 arch/arm64/kvm/sys_regs.h BUG_ON(i1 == i2); i1 123 arch/arm64/kvm/sys_regs.h if (!i1) i1 127 arch/arm64/kvm/sys_regs.h if (i1->Op0 != i2->Op0) i1 128 arch/arm64/kvm/sys_regs.h return i1->Op0 - i2->Op0; i1 129 arch/arm64/kvm/sys_regs.h if (i1->Op1 != i2->Op1) i1 130 arch/arm64/kvm/sys_regs.h return i1->Op1 - i2->Op1; i1 131 arch/arm64/kvm/sys_regs.h if (i1->CRn != i2->CRn) i1 132 arch/arm64/kvm/sys_regs.h return i1->CRn - i2->CRn; i1 133 arch/arm64/kvm/sys_regs.h if (i1->CRm != i2->CRm) i1 134 arch/arm64/kvm/sys_regs.h return i1->CRm - i2->CRm; i1 135 arch/arm64/kvm/sys_regs.h return i1->Op2 - i2->Op2; i1 27 arch/ia64/include/asm/kprobes.h #define BRL_INST(i1, i2) ((long)((0xcL << 37) | /* brl */ \ i1 29 arch/ia64/include/asm/kprobes.h (((i1) & 1) << 36) | ((i2) << 13))) /* imm */ i1 1116 arch/parisc/math-emu/fpudispatch.c struct { u_int i1; u_int i2; } ints; i1 1143 arch/parisc/math-emu/fpudispatch.c &mtmp.ints.i1,&status)) i1 1146 arch/parisc/math-emu/fpudispatch.c &atmp.ints.i1,&atmp.ints.i1,&status)) i1 1151 arch/parisc/math-emu/fpudispatch.c if (dbl_fmpy(&fpregs[rm1],&fpregs[rm2],&mtmp.ints.i1, i1 1154 arch/parisc/math-emu/fpudispatch.c if (dbl_fadd(&fpregs[ta], &fpregs[ra], &atmp.ints.i1, i1 1166 arch/parisc/math-emu/fpudispatch.c if (dbl_fmpy(&fpregs[rm1],&fpregs[rm2],&mtmp.ints.i1, i1 1169 arch/parisc/math-emu/fpudispatch.c if (dbl_fadd(&fpregs[ta], &fpregs[ra], &atmp.ints.i1, i1 1179 arch/parisc/math-emu/fpudispatch.c fpregs[tm] = mtmp.ints.i1; i1 1181 arch/parisc/math-emu/fpudispatch.c fpregs[ta] = atmp.ints.i1; i1 1213 arch/parisc/math-emu/fpudispatch.c if (sgl_fmpy(&fpregs[rm1],&fpregs[rm2],&mtmp.ints.i1, i1 1216 arch/parisc/math-emu/fpudispatch.c if (sgl_to_sgl_fcnvfxt(&fpregs[ta],&atmp.ints.i1, i1 1217 arch/parisc/math-emu/fpudispatch.c &atmp.ints.i1,&status)) i1 1221 arch/parisc/math-emu/fpudispatch.c if (sgl_fmpy(&fpregs[rm1],&fpregs[rm2],&mtmp.ints.i1, i1 1224 arch/parisc/math-emu/fpudispatch.c if (sgl_fadd(&fpregs[ta], &fpregs[ra], &atmp.ints.i1, i1 1232 arch/parisc/math-emu/fpudispatch.c fpregs[tm] = mtmp.ints.i1; i1 1233 arch/parisc/math-emu/fpudispatch.c fpregs[ta] = atmp.ints.i1; i1 1255 arch/parisc/math-emu/fpudispatch.c struct { u_int i1; u_int i2; } ints; i1 1278 arch/parisc/math-emu/fpudispatch.c if (dbl_fmpy(&fpregs[rm1],&fpregs[rm2],&mtmp.ints.i1,&status)) i1 1280 arch/parisc/math-emu/fpudispatch.c if (dbl_fsub(&fpregs[ta], &fpregs[ra], &atmp.ints.i1,&status)) i1 1286 arch/parisc/math-emu/fpudispatch.c fpregs[tm] = mtmp.ints.i1; i1 1288 arch/parisc/math-emu/fpudispatch.c fpregs[ta] = atmp.ints.i1; i1 1314 arch/parisc/math-emu/fpudispatch.c if (sgl_fmpy(&fpregs[rm1],&fpregs[rm2],&mtmp.ints.i1,&status)) i1 1316 arch/parisc/math-emu/fpudispatch.c if (sgl_fsub(&fpregs[ta], &fpregs[ra], &atmp.ints.i1,&status)) i1 1322 arch/parisc/math-emu/fpudispatch.c fpregs[tm] = mtmp.ints.i1; i1 1323 arch/parisc/math-emu/fpudispatch.c fpregs[ta] = atmp.ints.i1; i1 2051 arch/powerpc/kvm/book3s_xive.c u32 i0, i1, idx; i1 2062 arch/powerpc/kvm/book3s_xive.c i1 = be32_to_cpup(q->qpage + idx); i1 2064 arch/powerpc/kvm/book3s_xive.c i0, i1); i1 226 arch/powerpc/sysdev/xive/common.c u32 i0, i1, idx; i1 233 arch/powerpc/sysdev/xive/common.c i1 = be32_to_cpup(q->qpage + idx); i1 235 arch/powerpc/sysdev/xive/common.c q->idx, q->toggle, i0, i1); i1 261 arch/sparc/include/asm/ttable.h stx %i1, [%sp + STACK_BIAS + 0x48]; \ i1 282 arch/sparc/include/asm/ttable.h stx %i1, [%sp + STACK_BIAS + 0x48]; \ i1 313 arch/sparc/include/asm/ttable.h stxa %i1, [%g1 + %g3] ASI; \ i1 340 arch/sparc/include/asm/ttable.h stxa %i1, [%sp + STACK_BIAS + 0x48] %asi; \ i1 374 arch/sparc/include/asm/ttable.h stx %i1, [%g3 + TI_REG_WINDOW + 0x48]; \ i1 409 arch/sparc/include/asm/ttable.h stwa %i1, [%g1 + %g3] ASI; \ i1 439 arch/sparc/include/asm/ttable.h stwa %i1, [%sp + 0x24] %asi; \ i1 473 arch/sparc/include/asm/ttable.h stw %i1, [%g3 + TI_REG_WINDOW + 0x24]; \ i1 517 arch/sparc/include/asm/ttable.h ldx [%sp + STACK_BIAS + 0x48], %i1; \ i1 541 arch/sparc/include/asm/ttable.h ldx [%sp + STACK_BIAS + 0x48], %i1; \ i1 573 arch/sparc/include/asm/ttable.h ldxa [%g1 + %g2] ASI, %i1; \ i1 598 arch/sparc/include/asm/ttable.h ldxa [%sp + STACK_BIAS + 0x48] %asi, %i1; \ i1 633 arch/sparc/include/asm/ttable.h lduwa [%g1 + %g2] ASI, %i1; \ i1 661 arch/sparc/include/asm/ttable.h lduwa [%sp + 0x24] %asi, %i1; \ i1 112 crypto/vmac.c #define MUL32(i1, i2) ((u64)(u32)(i1)*(u32)(i2)) i1 114 crypto/vmac.c #define PMUL64(rh, rl, i1, i2) /* Assumes m doesn't overflow */ \ i1 116 crypto/vmac.c u64 _i1 = (i1), _i2 = (i2); \ i1 123 crypto/vmac.c #define MUL64(rh, rl, i1, i2) \ i1 125 crypto/vmac.c u64 _i1 = (i1), _i2 = (i2); \ i1 191 drivers/block/umem.c int i, i1; i1 197 drivers/block/umem.c for (i1 = 0; i1 < 16; i1++) i1 54 drivers/connector/cn_queue.c int cn_cb_equal(struct cb_id *i1, struct cb_id *i2) i1 56 drivers/connector/cn_queue.c return ((i1->idx == i2->idx) && (i1->val == i2->val)); i1 353 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_STAGE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); } i1 355 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); } i1 375 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_STAGE_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_OVLP(i0) + __offset_STAGE(i1); } i1 377 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_STAGE_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_OVLP(i0) + __offset_STAGE(i1); } i1 379 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000c + __offset_OVLP(i0) + __offset_STAGE(i1); } i1 381 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000010 + __offset_OVLP(i0) + __offset_STAGE(i1); } i1 383 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000014 + __offset_OVLP(i0) + __offset_STAGE(i1); } i1 385 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000018 + __offset_OVLP(i0) + __offset_STAGE(i1); } i1 397 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_STAGE_CO3(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE_CO3(i1); } i1 399 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_STAGE_CO3_SEL(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE_CO3(i1); } i1 415 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_CSC_MV(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_OVLP(i0) + 0x4*i1; } i1 417 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_CSC_MV_VAL(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_OVLP(i0) + 0x4*i1; } i1 419 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_CSC_PRE_BV(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_OVLP(i0) + 0x4*i1; } i1 421 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_CSC_PRE_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_OVLP(i0) + 0x4*i1; } i1 423 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_CSC_POST_BV(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_OVLP(i0) + 0x4*i1; } i1 425 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_CSC_POST_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_OVLP(i0) + 0x4*i1; } i1 427 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_CSC_PRE_LV(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_OVLP(i0) + 0x4*i1; } i1 429 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_CSC_PRE_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_OVLP(i0) + 0x4*i1; } i1 431 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_CSC_POST_LV(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_OVLP(i0) + 0x4*i1; } i1 433 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_CSC_POST_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_OVLP(i0) + 0x4*i1; } i1 439 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_LUTN_LUT(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 + 0x4*i1; } i1 441 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_LUTN_LUT_VAL(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 + 0x4*i1; } i1 570 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CSC_MV(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1; } i1 572 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CSC_MV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1; } i1 574 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1; } i1 576 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1; } i1 578 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CSC_POST_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1; } i1 580 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CSC_POST_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1; } i1 582 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1; } i1 584 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1; } i1 586 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CSC_POST_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1; } i1 588 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CSC_POST_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1; } i1 821 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_CSC_MV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; } i1 823 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_CSC_MV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; } i1 825 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; } i1 827 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; } i1 829 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; } i1 831 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; } i1 833 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; } i1 835 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; } i1 837 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; } i1 839 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; } i1 321 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_IGC_LUT(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1; } i1 323 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_IGC_LUT_REG(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1; } i1 374 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_CTL_LAYER(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); } i1 376 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_CTL_LAYER_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); } i1 509 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_CTL_LAYER_EXT(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER_EXT(i1); } i1 511 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_CTL_LAYER_EXT_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER_EXT(i1); } i1 641 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x4*i1; } i1 643 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x4*i1; } i1 657 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x4*i1; } i1 659 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x4*i1; } i1 673 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_PIPE(i0) + 0x4*i1; } i1 675 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_PIPE(i0) + 0x4*i1; } i1 683 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_PIPE(i0) + 0x4*i1; } i1 685 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_PIPE(i0) + 0x4*i1; } i1 943 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000000 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); } i1 945 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_LR(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000000 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); } i1 971 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_TB(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000004 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); } i1 997 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000008 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); } i1 1118 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_BLEND(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_LM(i0) + __offset_BLEND(i1); } i1 1120 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_BLEND_OP_MODE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_LM(i0) + __offset_BLEND(i1); } i1 1142 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_BLEND_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_LM(i0) + __offset_BLEND(i1); } i1 1144 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_BLEND_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_LM(i0) + __offset_BLEND(i1); } i1 1146 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000c + __offset_LM(i0) + __offset_BLEND(i1); } i1 1148 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000010 + __offset_LM(i0) + __offset_BLEND(i1); } i1 1150 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000014 + __offset_LM(i0) + __offset_BLEND(i1); } i1 1152 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000018 + __offset_LM(i0) + __offset_BLEND(i1); } i1 1154 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000001c + __offset_LM(i0) + __offset_BLEND(i1); } i1 1156 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000020 + __offset_LM(i0) + __offset_BLEND(i1); } i1 1158 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000024 + __offset_LM(i0) + __offset_BLEND(i1); } i1 1160 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000028 + __offset_LM(i0) + __offset_BLEND(i1); } i1 1691 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP(uint32_t i0, uint32_t i1) { return 0x00000274 + __offset_WB(i0) + 0x4*i1; } i1 1693 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000274 + __offset_WB(i0) + 0x4*i1; } i1 1707 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP(uint32_t i0, uint32_t i1) { return 0x00000280 + __offset_WB(i0) + 0x4*i1; } i1 1709 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000280 + __offset_WB(i0) + 0x4*i1; } i1 1723 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS(uint32_t i0, uint32_t i1) { return 0x0000028c + __offset_WB(i0) + 0x4*i1; } i1 1725 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS_REG(uint32_t i0, uint32_t i1) { return 0x0000028c + __offset_WB(i0) + 0x4*i1; } i1 1733 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS(uint32_t i0, uint32_t i1) { return 0x00000298 + __offset_WB(i0) + 0x4*i1; } i1 1735 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS_REG(uint32_t i0, uint32_t i1) { return 0x00000298 + __offset_WB(i0) + 0x4*i1; } i1 388 drivers/isdn/mISDN/dsp_cmx.c int memb = 0, i, ii, i1, i2; i1 858 drivers/isdn/mISDN/dsp_cmx.c i1 = 0; i1 860 drivers/isdn/mISDN/dsp_cmx.c while (i1 < ii) { i1 861 drivers/isdn/mISDN/dsp_cmx.c if (freeslots[i1]) i1 863 drivers/isdn/mISDN/dsp_cmx.c i1++; i1 865 drivers/isdn/mISDN/dsp_cmx.c if (i1 == ii) { i1 875 drivers/isdn/mISDN/dsp_cmx.c i2 = i1 + 1; i1 893 drivers/isdn/mISDN/dsp_cmx.c member->dsp->pcm_slot_tx = i1; i1 896 drivers/isdn/mISDN/dsp_cmx.c nextm->dsp->pcm_slot_rx = i1; i1 312 drivers/isdn/mISDN/l1oip_codec.c int i1, i2, c, sample; i1 326 drivers/isdn/mISDN/l1oip_codec.c i1 = 0; i1 327 drivers/isdn/mISDN/l1oip_codec.c while (i1 < 256) { i1 329 drivers/isdn/mISDN/l1oip_codec.c c = ulaw_to_4bit[i1]; i1 331 drivers/isdn/mISDN/l1oip_codec.c c = alaw_to_4bit[i1]; i1 334 drivers/isdn/mISDN/l1oip_codec.c table_com[(i1 << 8) | i2] |= (c << 4); i1 335 drivers/isdn/mISDN/l1oip_codec.c table_com[(i2 << 8) | i1] |= c; i1 338 drivers/isdn/mISDN/l1oip_codec.c i1++; i1 342 drivers/isdn/mISDN/l1oip_codec.c i1 = 0; i1 343 drivers/isdn/mISDN/l1oip_codec.c while (i1 < 16) { i1 345 drivers/isdn/mISDN/l1oip_codec.c sample = _4bit_to_ulaw[i1]; i1 347 drivers/isdn/mISDN/l1oip_codec.c sample = _4bit_to_alaw[i1]; i1 350 drivers/isdn/mISDN/l1oip_codec.c table_dec[(i1 << 4) | i2] |= (sample << 8); i1 351 drivers/isdn/mISDN/l1oip_codec.c table_dec[(i2 << 4) | i1] |= sample; i1 354 drivers/isdn/mISDN/l1oip_codec.c i1++; i1 345 drivers/scsi/advansys.c ASC_SCSIQ_1 i1; i1 20 drivers/video/fbdev/c2p_core.h static inline void _transp(u32 d[], unsigned int i1, unsigned int i2, i1 23 drivers/video/fbdev/c2p_core.h u32 t = (d[i1] ^ (d[i2] >> shift)) & mask; i1 25 drivers/video/fbdev/c2p_core.h d[i1] ^= t; i1 419 fs/fat/fat.h extern int fat_flush_inodes(struct super_block *sb, struct inode *i1, i1 1937 fs/fat/inode.c int fat_flush_inodes(struct super_block *sb, struct inode *i1, struct inode *i2) i1 1942 fs/fat/inode.c if (i1) i1 1943 fs/fat/inode.c ret = writeback_inode(i1); i1 105 fs/jffs2/compr_rubin.c long i0, i1; i1 126 fs/jffs2/compr_rubin.c i1 = rs->p - i0; i1 131 fs/jffs2/compr_rubin.c rs->p = i1; i1 2741 fs/xfs/xfs_trace.h struct xfs_refcount_irec *i1, struct xfs_refcount_irec *i2), i1 2742 fs/xfs/xfs_trace.h TP_ARGS(mp, agno, i1, i2), i1 2756 fs/xfs/xfs_trace.h __entry->i1_startblock = i1->rc_startblock; i1 2757 fs/xfs/xfs_trace.h __entry->i1_blockcount = i1->rc_blockcount; i1 2758 fs/xfs/xfs_trace.h __entry->i1_refcount = i1->rc_refcount; i1 2778 fs/xfs/xfs_trace.h struct xfs_refcount_irec *i1, struct xfs_refcount_irec *i2), \ i1 2779 fs/xfs/xfs_trace.h TP_ARGS(mp, agno, i1, i2)) i1 2784 fs/xfs/xfs_trace.h struct xfs_refcount_irec *i1, struct xfs_refcount_irec *i2, i1 2786 fs/xfs/xfs_trace.h TP_ARGS(mp, agno, i1, i2, agbno), i1 2801 fs/xfs/xfs_trace.h __entry->i1_startblock = i1->rc_startblock; i1 2802 fs/xfs/xfs_trace.h __entry->i1_blockcount = i1->rc_blockcount; i1 2803 fs/xfs/xfs_trace.h __entry->i1_refcount = i1->rc_refcount; i1 2825 fs/xfs/xfs_trace.h struct xfs_refcount_irec *i1, struct xfs_refcount_irec *i2, \ i1 2827 fs/xfs/xfs_trace.h TP_ARGS(mp, agno, i1, i2, agbno)) i1 2832 fs/xfs/xfs_trace.h struct xfs_refcount_irec *i1, struct xfs_refcount_irec *i2, i1 2834 fs/xfs/xfs_trace.h TP_ARGS(mp, agno, i1, i2, i3), i1 2851 fs/xfs/xfs_trace.h __entry->i1_startblock = i1->rc_startblock; i1 2852 fs/xfs/xfs_trace.h __entry->i1_blockcount = i1->rc_blockcount; i1 2853 fs/xfs/xfs_trace.h __entry->i1_refcount = i1->rc_refcount; i1 2880 fs/xfs/xfs_trace.h struct xfs_refcount_irec *i1, struct xfs_refcount_irec *i2, \ i1 2882 fs/xfs/xfs_trace.h TP_ARGS(mp, agno, i1, i2, i3)) i1 287 include/sound/pcm_params.h static inline int snd_interval_eq(const struct snd_interval *i1, const struct snd_interval *i2) i1 289 include/sound/pcm_params.h if (i1->empty) i1 292 include/sound/pcm_params.h return i1->empty; i1 293 include/sound/pcm_params.h return i1->min == i2->min && i1->openmin == i2->openmin && i1 294 include/sound/pcm_params.h i1->max == i2->max && i1->openmax == i2->openmax; i1 914 net/decnet/dn_dev.c unsigned char *i1, *i2; i1 951 net/decnet/dn_dev.c i1 = ptr++; i1 959 net/decnet/dn_dev.c *i1 = 8 + *i2; i1 1111 sound/pci/cs46xx/cs46xx_dsp_scb_types.h u32 i1; i1 203 tools/perf/util/string.c int i1 = strlen(s1); i1 205 tools/perf/util/string.c while (--i1 >= 0 && --i2 >= 0) { i1 206 tools/perf/util/string.c if (s1[i1] != s2[i2]) i1 207 tools/perf/util/string.c return s1[i1] - s2[i2]; i1 28 tools/testing/selftests/proc/proc-uptime-001.c uint64_t start, u0, u1, i0, i1; i1 37 tools/testing/selftests/proc/proc-uptime-001.c proc_uptime(fd, &u1, &i1); i1 39 tools/testing/selftests/proc/proc-uptime-001.c assert(i1 >= i0); i1 41 tools/testing/selftests/proc/proc-uptime-001.c i0 = i1; i1 48 tools/testing/selftests/proc/proc-uptime-002.c uint64_t u0, u1, i0, i1; i1 71 tools/testing/selftests/proc/proc-uptime-002.c proc_uptime(fd, &u1, &i1); i1 73 tools/testing/selftests/proc/proc-uptime-002.c assert(i1 >= i0); i1 75 tools/testing/selftests/proc/proc-uptime-002.c i0 = i1;