i0 2051 arch/powerpc/kvm/book3s_xive.c u32 i0, i1, idx; i0 2060 arch/powerpc/kvm/book3s_xive.c i0 = be32_to_cpup(q->qpage + idx); i0 2064 arch/powerpc/kvm/book3s_xive.c i0, i1); i0 226 arch/powerpc/sysdev/xive/common.c u32 i0, i1, idx; i0 231 arch/powerpc/sysdev/xive/common.c i0 = be32_to_cpup(q->qpage + idx); i0 235 arch/powerpc/sysdev/xive/common.c q->idx, q->toggle, i0, i1); i0 67 arch/sparc/include/asm/head_32.h rd %psr, %i0; jmp %l2; rett %l2 + 4; nop; i0 260 arch/sparc/include/asm/ttable.h stx %i0, [%sp + STACK_BIAS + 0x40]; \ i0 281 arch/sparc/include/asm/ttable.h stx %i0, [%sp + STACK_BIAS + 0x40]; \ i0 312 arch/sparc/include/asm/ttable.h stxa %i0, [%g1 + %g0] ASI; \ i0 339 arch/sparc/include/asm/ttable.h stxa %i0, [%sp + STACK_BIAS + 0x40] %asi; \ i0 373 arch/sparc/include/asm/ttable.h stx %i0, [%g3 + TI_REG_WINDOW + 0x40]; \ i0 408 arch/sparc/include/asm/ttable.h stwa %i0, [%g1 + %g0] ASI; \ i0 438 arch/sparc/include/asm/ttable.h stwa %i0, [%sp + 0x20] %asi; \ i0 472 arch/sparc/include/asm/ttable.h stw %i0, [%g3 + TI_REG_WINDOW + 0x20]; \ i0 516 arch/sparc/include/asm/ttable.h ldx [%sp + STACK_BIAS + 0x40], %i0; \ i0 540 arch/sparc/include/asm/ttable.h ldx [%sp + STACK_BIAS + 0x40], %i0; \ i0 572 arch/sparc/include/asm/ttable.h ldxa [%g1 + %g0] ASI, %i0; \ i0 597 arch/sparc/include/asm/ttable.h ldxa [%sp + STACK_BIAS + 0x40] %asi, %i0; \ i0 632 arch/sparc/include/asm/ttable.h lduwa [%g1 + %g0] ASI, %i0; \ i0 660 arch/sparc/include/asm/ttable.h lduwa [%sp + 0x20] %asi, %i0; \ i0 21 arch/sparc/include/asm/winmacro.h std %i0, [%reg + RW_I0]; \ i0 32 arch/sparc/include/asm/winmacro.h ldd [%reg + RW_I0], %i0; \ i0 39 arch/sparc/include/asm/winmacro.h ldd [%base_reg + STACKFRAME_SZ + PT_I0], %i0; \ i0 66 arch/sparc/include/asm/winmacro.h std %i0, [%base_reg + STACKFRAME_SZ + PT_I0]; \ i0 73 drivers/gpu/drm/etnaviv/state.xml.h #define VIVS_FE_VERTEX_ELEMENT_CONFIG(i0) (0x00000600 + 0x4*(i0)) i0 192 drivers/gpu/drm/etnaviv/state.xml.h #define VIVS_FE_VERTEX_STREAMS(i0) (0x00000000 + 0x4*(i0)) i0 196 drivers/gpu/drm/etnaviv/state.xml.h #define VIVS_FE_VERTEX_STREAMS_BASE_ADDR(i0) (0x00000680 + 0x4*(i0)) i0 198 drivers/gpu/drm/etnaviv/state.xml.h #define VIVS_FE_VERTEX_STREAMS_CONTROL(i0) (0x000006a0 + 0x4*(i0)) i0 200 drivers/gpu/drm/etnaviv/state.xml.h #define VIVS_FE_GENERIC_ATTRIB(i0) (0x00000000 + 0x4*(i0)) i0 204 drivers/gpu/drm/etnaviv/state.xml.h #define VIVS_FE_GENERIC_ATTRIB_UNK006C0(i0) (0x000006c0 + 0x4*(i0)) i0 206 drivers/gpu/drm/etnaviv/state.xml.h #define VIVS_FE_GENERIC_ATTRIB_UNK00700(i0) (0x00000700 + 0x4*(i0)) i0 208 drivers/gpu/drm/etnaviv/state.xml.h #define VIVS_FE_GENERIC_ATTRIB_UNK00740(i0) (0x00000740 + 0x4*(i0)) i0 210 drivers/gpu/drm/etnaviv/state.xml.h #define VIVS_FE_GENERIC_ATTRIB_SCALE(i0) (0x00000780 + 0x4*(i0)) i0 214 drivers/gpu/drm/etnaviv/state.xml.h #define VIVS_FE_HALTI5_UNK007D0(i0) (0x000007d0 + 0x4*(i0)) i0 315 drivers/gpu/drm/etnaviv/state.xml.h #define VIVS_GL_VARYING_COMPONENT_USE(i0) (0x00003828 + 0x4*(i0)) i0 412 drivers/gpu/drm/etnaviv/state.xml.h #define VIVS_GL_GS_UNK038A0(i0) (0x000038a0 + 0x4*(i0)) i0 416 drivers/gpu/drm/etnaviv/state.xml.h #define VIVS_GL_HALTI5_UNK038C0(i0) (0x000038c0 + 0x4*(i0)) i0 446 drivers/gpu/drm/etnaviv/state.xml.h #define VIVS_NFE_VERTEX_STREAMS(i0) (0x00000000 + 0x4*(i0)) i0 450 drivers/gpu/drm/etnaviv/state.xml.h #define VIVS_NFE_VERTEX_STREAMS_BASE_ADDR(i0) (0x00014600 + 0x4*(i0)) i0 452 drivers/gpu/drm/etnaviv/state.xml.h #define VIVS_NFE_VERTEX_STREAMS_CONTROL(i0) (0x00014640 + 0x4*(i0)) i0 454 drivers/gpu/drm/etnaviv/state.xml.h #define VIVS_NFE_VERTEX_STREAMS_UNK14680(i0) (0x00014680 + 0x4*(i0)) i0 456 drivers/gpu/drm/etnaviv/state.xml.h #define VIVS_NFE_VERTEX_STREAMS_ROBUSTNESS_UNK146C0(i0) (0x000146c0 + 0x4*(i0)) i0 458 drivers/gpu/drm/etnaviv/state.xml.h #define VIVS_NFE_GENERIC_ATTRIB(i0) (0x00000000 + 0x4*(i0)) i0 462 drivers/gpu/drm/etnaviv/state.xml.h #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0(i0) (0x00017800 + 0x4*(i0)) i0 483 drivers/gpu/drm/etnaviv/state.xml.h #define VIVS_NFE_GENERIC_ATTRIB_UNK17880(i0) (0x00017880 + 0x4*(i0)) i0 485 drivers/gpu/drm/etnaviv/state.xml.h #define VIVS_NFE_GENERIC_ATTRIB_UNK17900(i0) (0x00017900 + 0x4*(i0)) i0 487 drivers/gpu/drm/etnaviv/state.xml.h #define VIVS_NFE_GENERIC_ATTRIB_UNK17980(i0) (0x00017980 + 0x4*(i0)) i0 489 drivers/gpu/drm/etnaviv/state.xml.h #define VIVS_NFE_GENERIC_ATTRIB_SCALE(i0) (0x00017a00 + 0x4*(i0)) i0 491 drivers/gpu/drm/etnaviv/state.xml.h #define VIVS_NFE_GENERIC_ATTRIB_CONFIG1(i0) (0x00017a80 + 0x4*(i0)) i0 326 drivers/gpu/drm/etnaviv/state_hi.xml.h #define VIVS_MMUv2_EXCEPTION_ADDR(i0) (0x00000190 + 0x4*(i0)) i0 338 drivers/gpu/drm/etnaviv/state_hi.xml.h #define VIVS_MMUv2_AXI_POLICY(i0) (0x000001c0 + 0x4*(i0)) i0 574 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t REG_A2XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; } i0 576 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t REG_A2XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; } i0 578 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t REG_A2XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; } i0 580 drivers/gpu/drm/msm/adreno/a2xx.xml.h static inline uint32_t REG_A2XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; } i0 917 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_CP_PROTECT(uint32_t i0) { return 0x00000460 + 0x1*i0; } i0 919 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000460 + 0x1*i0; } i0 1218 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_RB_MRT(uint32_t i0) { return 0x000020c4 + 0x4*i0; } i0 1220 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020c4 + 0x4*i0; } i0 1243 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020c5 + 0x4*i0; } i0 1270 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_RB_MRT_BUF_BASE(uint32_t i0) { return 0x000020c6 + 0x4*i0; } i0 1278 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020c7 + 0x4*i0; } i0 1859 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK(uint32_t i0) { return 0x0000220b + 0x2*i0; } i0 1861 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_SIZE(uint32_t i0) { return 0x0000220b + 0x2*i0; } i0 1863 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_OFFSET(uint32_t i0) { return 0x0000220c + 0x2*i0; } i0 1871 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP(uint32_t i0) { return 0x00002215 + 0x1*i0; } i0 1873 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP_RATIO(uint32_t i0) { return 0x00002215 + 0x1*i0; } i0 1949 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_VFD_FETCH(uint32_t i0) { return 0x00002246 + 0x2*i0; } i0 1951 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x00002246 + 0x2*i0; } i0 1979 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x00002247 + 0x2*i0; } i0 1981 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_VFD_DECODE(uint32_t i0) { return 0x00002266 + 0x1*i0; } i0 1983 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x00002266 + 0x1*i0; } i0 2068 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002282 + 0x1*i0; } i0 2070 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002282 + 0x1*i0; } i0 2168 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00002286 + 0x1*i0; } i0 2170 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00002286 + 0x1*i0; } i0 2376 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; } i0 2378 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; } i0 2406 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d0 + 0x1*i0; } i0 2408 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d0 + 0x1*i0; } i0 2649 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_SP_FS_MRT(uint32_t i0) { return 0x000022f0 + 0x1*i0; } i0 2651 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f0 + 0x1*i0; } i0 2662 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT(uint32_t i0) { return 0x000022f4 + 0x1*i0; } i0 2664 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(uint32_t i0) { return 0x000022f4 + 0x1*i0; } i0 2816 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; } i0 2818 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; } i0 2844 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; } i0 2846 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; } i0 2871 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE(uint32_t i0) { return 0x00000ca0 + 0x4*i0; } i0 2873 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_X(uint32_t i0) { return 0x00000ca0 + 0x4*i0; } i0 2875 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Y(uint32_t i0) { return 0x00000ca1 + 0x4*i0; } i0 2877 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Z(uint32_t i0) { return 0x00000ca2 + 0x4*i0; } i0 2879 drivers/gpu/drm/msm/adreno/a3xx.xml.h static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_W(uint32_t i0) { return 0x00000ca3 + 0x4*i0; } i0 968 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; } i0 970 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020a4 + 0x5*i0; } i0 988 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020a5 + 0x5*i0; } i0 1021 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RB_MRT_BASE(uint32_t i0) { return 0x000020a6 + 0x5*i0; } i0 1023 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RB_MRT_CONTROL3(uint32_t i0) { return 0x000020a7 + 0x5*i0; } i0 1031 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020a8 + 0x5*i0; } i0 1534 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP(uint32_t i0) { return 0x00002120 + 0x2*i0; } i0 1536 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MIN(uint32_t i0) { return 0x00002120 + 0x2*i0; } i0 1538 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MAX(uint32_t i0) { return 0x00002121 + 0x2*i0; } i0 1544 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP(uint32_t i0) { return 0x00000004 + 0x1*i0; } i0 1546 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP_REG(uint32_t i0) { return 0x00000004 + 0x1*i0; } i0 1548 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP(uint32_t i0) { return 0x00000008 + 0x1*i0; } i0 1550 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP_REG(uint32_t i0) { return 0x00000008 + 0x1*i0; } i0 1552 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP(uint32_t i0) { return 0x0000000c + 0x1*i0; } i0 1554 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP_REG(uint32_t i0) { return 0x0000000c + 0x1*i0; } i0 1556 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP(uint32_t i0) { return 0x00000010 + 0x1*i0; } i0 1558 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP_REG(uint32_t i0) { return 0x00000010 + 0x1*i0; } i0 2012 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP(uint32_t i0) { return 0x00000068 + 0x1*i0; } i0 2014 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP_REG(uint32_t i0) { return 0x00000068 + 0x1*i0; } i0 2016 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP(uint32_t i0) { return 0x0000006c + 0x1*i0; } i0 2018 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP_REG(uint32_t i0) { return 0x0000006c + 0x1*i0; } i0 2020 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP(uint32_t i0) { return 0x00000070 + 0x1*i0; } i0 2022 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP_REG(uint32_t i0) { return 0x00000070 + 0x1*i0; } i0 2024 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP(uint32_t i0) { return 0x00000074 + 0x1*i0; } i0 2026 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP_REG(uint32_t i0) { return 0x00000074 + 0x1*i0; } i0 2028 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB(uint32_t i0) { return 0x00000078 + 0x1*i0; } i0 2030 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB_REG(uint32_t i0) { return 0x00000078 + 0x1*i0; } i0 2032 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB(uint32_t i0) { return 0x0000007c + 0x1*i0; } i0 2034 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB_REG(uint32_t i0) { return 0x0000007c + 0x1*i0; } i0 2036 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU(uint32_t i0) { return 0x00000082 + 0x1*i0; } i0 2038 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU_REG(uint32_t i0) { return 0x00000082 + 0x1*i0; } i0 2040 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU(uint32_t i0) { return 0x00000086 + 0x1*i0; } i0 2042 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU_REG(uint32_t i0) { return 0x00000086 + 0x1*i0; } i0 2056 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(uint32_t i0) { return 0x0000008e + 0x1*i0; } i0 2058 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0) { return 0x0000008e + 0x1*i0; } i0 2198 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_CP_PROTECT(uint32_t i0) { return 0x00000240 + 0x1*i0; } i0 2200 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000240 + 0x1*i0; } i0 2250 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_CP_SCRATCH(uint32_t i0) { return 0x00000578 + 0x1*i0; } i0 2252 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000578 + 0x1*i0; } i0 2360 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; } i0 2362 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; } i0 2388 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d8 + 0x1*i0; } i0 2390 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d8 + 0x1*i0; } i0 2528 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_SP_FS_MRT(uint32_t i0) { return 0x000022f1 + 0x1*i0; } i0 2530 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f1 + 0x1*i0; } i0 2596 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_SP_DS_OUT(uint32_t i0) { return 0x0000231b + 0x1*i0; } i0 2598 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000231b + 0x1*i0; } i0 2624 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000232c + 0x1*i0; } i0 2626 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000232c + 0x1*i0; } i0 2694 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_SP_GS_OUT(uint32_t i0) { return 0x00002342 + 0x1*i0; } i0 2696 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_SP_GS_OUT_REG(uint32_t i0) { return 0x00002342 + 0x1*i0; } i0 2722 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_SP_GS_VPC_DST(uint32_t i0) { return 0x00002353 + 0x1*i0; } i0 2724 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x00002353 + 0x1*i0; } i0 2822 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002142 + 0x1*i0; } i0 2824 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002142 + 0x1*i0; } i0 2826 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000214a + 0x1*i0; } i0 2828 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000214a + 0x1*i0; } i0 2852 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c08 + 0x1*i0; } i0 2854 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c08 + 0x1*i0; } i0 2880 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c10 + 0x1*i0; } i0 2882 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } i0 2884 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c18 + 0x1*i0; } i0 2886 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c18 + 0x1*i0; } i0 2988 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_VFD_FETCH(uint32_t i0) { return 0x0000220a + 0x4*i0; } i0 2990 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x0000220a + 0x4*i0; } i0 3006 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x0000220b + 0x4*i0; } i0 3008 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_2(uint32_t i0) { return 0x0000220c + 0x4*i0; } i0 3016 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_3(uint32_t i0) { return 0x0000220d + 0x4*i0; } i0 3024 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_VFD_DECODE(uint32_t i0) { return 0x0000228a + 0x1*i0; } i0 3026 drivers/gpu/drm/msm/adreno/a4xx.xml.h static inline uint32_t REG_A4XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000228a + 0x1*i0; } i0 1036 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_CP_SCRATCH(uint32_t i0) { return 0x00000b78 + 0x1*i0; } i0 1038 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000b78 + 0x1*i0; } i0 1040 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_CP_PROTECT(uint32_t i0) { return 0x00000880 + 0x1*i0; } i0 1042 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000880 + 0x1*i0; } i0 1977 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; } i0 1979 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; } i0 2005 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000be0 + 0x2*i0; } i0 2007 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_LO(uint32_t i0) { return 0x00000be0 + 0x2*i0; } i0 2009 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_HI(uint32_t i0) { return 0x00000be1 + 0x2*i0; } i0 2011 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c00 + 0x1*i0; } i0 2013 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c00 + 0x1*i0; } i0 3065 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_RB_MRT(uint32_t i0) { return 0x0000e150 + 0x7*i0; } i0 3067 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_RB_MRT_CONTROL(uint32_t i0) { return 0x0000e150 + 0x7*i0; } i0 3084 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x0000e151 + 0x7*i0; } i0 3122 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x0000e152 + 0x7*i0; } i0 3149 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_RB_MRT_PITCH(uint32_t i0) { return 0x0000e153 + 0x7*i0; } i0 3157 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x0000e154 + 0x7*i0; } i0 3165 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_RB_MRT_BASE_LO(uint32_t i0) { return 0x0000e155 + 0x7*i0; } i0 3167 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_RB_MRT_BASE_HI(uint32_t i0) { return 0x0000e156 + 0x7*i0; } i0 3574 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x0000e243 + 0x4*i0; } i0 3576 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0) { return 0x0000e243 + 0x4*i0; } i0 3578 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0) { return 0x0000e244 + 0x4*i0; } i0 3580 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x0000e245 + 0x4*i0; } i0 3588 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t i0) { return 0x0000e246 + 0x4*i0; } i0 3629 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x0000e282 + 0x1*i0; } i0 3631 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x0000e282 + 0x1*i0; } i0 3633 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000e28a + 0x1*i0; } i0 3635 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000e28a + 0x1*i0; } i0 3641 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VPC_VAR(uint32_t i0) { return 0x0000e294 + 0x1*i0; } i0 3643 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x0000e294 + 0x1*i0; } i0 3706 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VPC_SO(uint32_t i0) { return 0x0000e2a7 + 0x7*i0; } i0 3708 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VPC_SO_BUFFER_BASE_LO(uint32_t i0) { return 0x0000e2a7 + 0x7*i0; } i0 3710 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VPC_SO_BUFFER_BASE_HI(uint32_t i0) { return 0x0000e2a8 + 0x7*i0; } i0 3712 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000e2a9 + 0x7*i0; } i0 3714 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VPC_SO_NCOMP(uint32_t i0) { return 0x0000e2aa + 0x7*i0; } i0 3716 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000e2ab + 0x7*i0; } i0 3718 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VPC_SO_FLUSH_BASE_LO(uint32_t i0) { return 0x0000e2ac + 0x7*i0; } i0 3720 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VPC_SO_FLUSH_BASE_HI(uint32_t i0) { return 0x0000e2ad + 0x7*i0; } i0 3859 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VFD_FETCH(uint32_t i0) { return 0x0000e40a + 0x4*i0; } i0 3861 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VFD_FETCH_BASE_LO(uint32_t i0) { return 0x0000e40a + 0x4*i0; } i0 3863 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VFD_FETCH_BASE_HI(uint32_t i0) { return 0x0000e40b + 0x4*i0; } i0 3865 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000e40c + 0x4*i0; } i0 3867 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000e40d + 0x4*i0; } i0 3869 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VFD_DECODE(uint32_t i0) { return 0x0000e48a + 0x2*i0; } i0 3871 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000e48a + 0x2*i0; } i0 3894 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000e48b + 0x2*i0; } i0 3896 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000e4ca + 0x1*i0; } i0 3898 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000e4ca + 0x1*i0; } i0 4046 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_SP_VS_OUT(uint32_t i0) { return 0x0000e593 + 0x1*i0; } i0 4048 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000e593 + 0x1*i0; } i0 4074 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000e5a3 + 0x1*i0; } i0 4076 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000e5a3 + 0x1*i0; } i0 4167 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000e5cb + 0x1*i0; } i0 4169 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000e5cb + 0x1*i0; } i0 4178 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_SP_FS_MRT(uint32_t i0) { return 0x0000e5d3 + 0x1*i0; } i0 4180 drivers/gpu/drm/msm/adreno/a5xx.xml.h static inline uint32_t REG_A5XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000e5d3 + 0x1*i0; } i0 1064 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_CP_SCRATCH(uint32_t i0) { return 0x00000883 + 0x1*i0; } i0 1066 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000883 + 0x1*i0; } i0 1068 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_CP_PROTECT(uint32_t i0) { return 0x00000850 + 0x1*i0; } i0 1070 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000850 + 0x1*i0; } i0 2629 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } i0 2631 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } i0 2685 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VSC_SIZE(uint32_t i0) { return 0x00000c78 + 0x1*i0; } i0 2687 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VSC_SIZE_REG(uint32_t i0) { return 0x00000c78 + 0x1*i0; } i0 3307 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_RB_MRT(uint32_t i0) { return 0x00008820 + 0x8*i0; } i0 3309 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_RB_MRT_CONTROL(uint32_t i0) { return 0x00008820 + 0x8*i0; } i0 3326 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x00008821 + 0x8*i0; } i0 3364 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x00008822 + 0x8*i0; } i0 3384 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_RB_MRT_PITCH(uint32_t i0) { return 0x00008823 + 0x8*i0; } i0 3392 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x00008824 + 0x8*i0; } i0 3400 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_RB_MRT_BASE_LO(uint32_t i0) { return 0x00008825 + 0x8*i0; } i0 3402 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_RB_MRT_BASE_HI(uint32_t i0) { return 0x00008826 + 0x8*i0; } i0 3404 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_RB_MRT_BASE_GMEM(uint32_t i0) { return 0x00008827 + 0x8*i0; } i0 3779 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x00008903 + 0x3*i0; } i0 3781 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0) { return 0x00008903 + 0x3*i0; } i0 3783 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0) { return 0x00008904 + 0x3*i0; } i0 3785 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x00008905 + 0x3*i0; } i0 3873 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00009200 + 0x1*i0; } i0 3875 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00009200 + 0x1*i0; } i0 3877 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00009208 + 0x1*i0; } i0 3879 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00009208 + 0x1*i0; } i0 3885 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VPC_VAR(uint32_t i0) { return 0x00009212 + 0x1*i0; } i0 3887 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x00009212 + 0x1*i0; } i0 3920 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VPC_SO(uint32_t i0) { return 0x0000921a + 0x7*i0; } i0 3922 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE_LO(uint32_t i0) { return 0x0000921a + 0x7*i0; } i0 3924 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE_HI(uint32_t i0) { return 0x0000921b + 0x7*i0; } i0 3926 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000921c + 0x7*i0; } i0 3928 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VPC_SO_NCOMP(uint32_t i0) { return 0x0000921d + 0x7*i0; } i0 3930 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000921e + 0x7*i0; } i0 3932 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE_LO(uint32_t i0) { return 0x0000921f + 0x7*i0; } i0 3934 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE_HI(uint32_t i0) { return 0x00009220 + 0x7*i0; } i0 4095 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VFD_FETCH(uint32_t i0) { return 0x0000a010 + 0x4*i0; } i0 4097 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VFD_FETCH_BASE_LO(uint32_t i0) { return 0x0000a010 + 0x4*i0; } i0 4099 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VFD_FETCH_BASE_HI(uint32_t i0) { return 0x0000a011 + 0x4*i0; } i0 4101 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000a012 + 0x4*i0; } i0 4103 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000a013 + 0x4*i0; } i0 4105 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VFD_DECODE(uint32_t i0) { return 0x0000a090 + 0x2*i0; } i0 4107 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000a090 + 0x2*i0; } i0 4130 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000a091 + 0x2*i0; } i0 4132 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; } i0 4134 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; } i0 4158 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_SP_VS_OUT(uint32_t i0) { return 0x0000a803 + 0x1*i0; } i0 4160 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000a803 + 0x1*i0; } i0 4186 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000a813 + 0x1*i0; } i0 4188 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000a813 + 0x1*i0; } i0 4576 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_SP_FS_MRT(uint32_t i0) { return 0x0000a996 + 0x1*i0; } i0 4578 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000a996 + 0x1*i0; } i0 4610 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000a98e + 0x1*i0; } i0 4612 drivers/gpu/drm/msm/adreno/a6xx.xml.h static inline uint32_t REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000a98e + 0x1*i0; } i0 844 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t REG_CP_SET_DRAW_STATE_(uint32_t i0) { return 0x00000000 + 0x3*i0; } i0 846 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t REG_CP_SET_DRAW_STATE__0(uint32_t i0) { return 0x00000000 + 0x3*i0; } i0 870 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t REG_CP_SET_DRAW_STATE__1(uint32_t i0) { return 0x00000001 + 0x3*i0; } i0 878 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t REG_CP_SET_DRAW_STATE__2(uint32_t i0) { return 0x00000002 + 0x3*i0; } i0 1524 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG_(uint32_t i0) { return 0x00000000 + 0x3*i0; } i0 1526 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG__0(uint32_t i0) { return 0x00000000 + 0x3*i0; } i0 1534 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG__1(uint32_t i0) { return 0x00000001 + 0x3*i0; } i0 1542 drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG__2(uint32_t i0) { return 0x00000002 + 0x3*i0; } i0 319 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP(uint32_t i0) { return 0x00000000 + __offset_OVLP(i0); } i0 321 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_CFG(uint32_t i0) { return 0x00000004 + __offset_OVLP(i0); } i0 323 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_SIZE(uint32_t i0) { return 0x00000008 + __offset_OVLP(i0); } i0 337 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_BASE(uint32_t i0) { return 0x0000000c + __offset_OVLP(i0); } i0 339 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_STRIDE(uint32_t i0) { return 0x00000010 + __offset_OVLP(i0); } i0 341 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_OPMODE(uint32_t i0) { return 0x00000014 + __offset_OVLP(i0); } i0 353 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_STAGE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); } i0 355 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); } i0 375 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_STAGE_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_OVLP(i0) + __offset_STAGE(i1); } i0 377 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_STAGE_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_OVLP(i0) + __offset_STAGE(i1); } i0 379 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000c + __offset_OVLP(i0) + __offset_STAGE(i1); } i0 381 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000010 + __offset_OVLP(i0) + __offset_STAGE(i1); } i0 383 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000014 + __offset_OVLP(i0) + __offset_STAGE(i1); } i0 385 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000018 + __offset_OVLP(i0) + __offset_STAGE(i1); } i0 397 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_STAGE_CO3(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE_CO3(i1); } i0 399 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_STAGE_CO3_SEL(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE_CO3(i1); } i0 402 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_TRANSP_LOW0(uint32_t i0) { return 0x00000180 + __offset_OVLP(i0); } i0 404 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_TRANSP_LOW1(uint32_t i0) { return 0x00000184 + __offset_OVLP(i0); } i0 406 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH0(uint32_t i0) { return 0x00000188 + __offset_OVLP(i0); } i0 408 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_TRANSP_HIGH1(uint32_t i0) { return 0x0000018c + __offset_OVLP(i0); } i0 410 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_CSC_CONFIG(uint32_t i0) { return 0x00000200 + __offset_OVLP(i0); } i0 412 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_CSC(uint32_t i0) { return 0x00002000 + __offset_OVLP(i0); } i0 415 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_CSC_MV(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_OVLP(i0) + 0x4*i1; } i0 417 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_CSC_MV_VAL(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_OVLP(i0) + 0x4*i1; } i0 419 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_CSC_PRE_BV(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_OVLP(i0) + 0x4*i1; } i0 421 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_CSC_PRE_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_OVLP(i0) + 0x4*i1; } i0 423 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_CSC_POST_BV(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_OVLP(i0) + 0x4*i1; } i0 425 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_CSC_POST_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_OVLP(i0) + 0x4*i1; } i0 427 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_CSC_PRE_LV(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_OVLP(i0) + 0x4*i1; } i0 429 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_CSC_PRE_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_OVLP(i0) + 0x4*i1; } i0 431 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_CSC_POST_LV(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_OVLP(i0) + 0x4*i1; } i0 433 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_OVLP_CSC_POST_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_OVLP(i0) + 0x4*i1; } i0 437 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_LUTN(uint32_t i0) { return 0x00094800 + 0x400*i0; } i0 439 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_LUTN_LUT(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 + 0x4*i1; } i0 441 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_LUTN_LUT_VAL(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 + 0x4*i1; } i0 445 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_E_QUANT(uint32_t i0) { return 0x000b0070 + 0x4*i0; } i0 456 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); } i0 458 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CONFIG(enum mdp4_dma i0) { return 0x00000000 + __offset_DMA(i0); } i0 487 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_SRC_SIZE(enum mdp4_dma i0) { return 0x00000004 + __offset_DMA(i0); } i0 501 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_SRC_BASE(enum mdp4_dma i0) { return 0x00000008 + __offset_DMA(i0); } i0 503 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_SRC_STRIDE(enum mdp4_dma i0) { return 0x0000000c + __offset_DMA(i0); } i0 505 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_DST_SIZE(enum mdp4_dma i0) { return 0x00000010 + __offset_DMA(i0); } i0 519 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CURSOR_SIZE(enum mdp4_dma i0) { return 0x00000044 + __offset_DMA(i0); } i0 533 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CURSOR_BASE(enum mdp4_dma i0) { return 0x00000048 + __offset_DMA(i0); } i0 535 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CURSOR_POS(enum mdp4_dma i0) { return 0x0000004c + __offset_DMA(i0); } i0 549 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_CONFIG(enum mdp4_dma i0) { return 0x00000060 + __offset_DMA(i0); } i0 559 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CURSOR_BLEND_PARAM(enum mdp4_dma i0) { return 0x00000064 + __offset_DMA(i0); } i0 561 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_LOW(enum mdp4_dma i0) { return 0x00000068 + __offset_DMA(i0); } i0 563 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_BLEND_TRANS_HIGH(enum mdp4_dma i0) { return 0x0000006c + __offset_DMA(i0); } i0 565 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_FETCH_CONFIG(enum mdp4_dma i0) { return 0x00001004 + __offset_DMA(i0); } i0 567 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CSC(enum mdp4_dma i0) { return 0x00003000 + __offset_DMA(i0); } i0 570 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CSC_MV(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1; } i0 572 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CSC_MV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1; } i0 574 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1; } i0 576 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1; } i0 578 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CSC_POST_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1; } i0 580 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CSC_POST_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1; } i0 582 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1; } i0 584 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1; } i0 586 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CSC_POST_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1; } i0 588 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_DMA_CSC_POST_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1; } i0 590 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; } i0 592 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_SRC_SIZE(enum mdp4_pipe i0) { return 0x00020000 + 0x10000*i0; } i0 606 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_SRC_XY(enum mdp4_pipe i0) { return 0x00020004 + 0x10000*i0; } i0 620 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_DST_SIZE(enum mdp4_pipe i0) { return 0x00020008 + 0x10000*i0; } i0 634 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_DST_XY(enum mdp4_pipe i0) { return 0x0002000c + 0x10000*i0; } i0 648 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_SRCP0_BASE(enum mdp4_pipe i0) { return 0x00020010 + 0x10000*i0; } i0 650 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_SRCP1_BASE(enum mdp4_pipe i0) { return 0x00020014 + 0x10000*i0; } i0 652 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_SRCP2_BASE(enum mdp4_pipe i0) { return 0x00020018 + 0x10000*i0; } i0 654 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_SRCP3_BASE(enum mdp4_pipe i0) { return 0x0002001c + 0x10000*i0; } i0 656 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_A(enum mdp4_pipe i0) { return 0x00020040 + 0x10000*i0; } i0 670 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_SRC_STRIDE_B(enum mdp4_pipe i0) { return 0x00020044 + 0x10000*i0; } i0 684 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_SSTILE_FRAME_SIZE(enum mdp4_pipe i0) { return 0x00020048 + 0x10000*i0; } i0 698 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_SRC_FORMAT(enum mdp4_pipe i0) { return 0x00020050 + 0x10000*i0; } i0 759 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_SRC_UNPACK(enum mdp4_pipe i0) { return 0x00020054 + 0x10000*i0; } i0 785 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_OP_MODE(enum mdp4_pipe i0) { return 0x00020058 + 0x10000*i0; } i0 810 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_PHASEX_STEP(enum mdp4_pipe i0) { return 0x0002005c + 0x10000*i0; } i0 812 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_PHASEY_STEP(enum mdp4_pipe i0) { return 0x00020060 + 0x10000*i0; } i0 814 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_FETCH_CONFIG(enum mdp4_pipe i0) { return 0x00021004 + 0x10000*i0; } i0 816 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_SOLID_COLOR(enum mdp4_pipe i0) { return 0x00021008 + 0x10000*i0; } i0 818 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_CSC(enum mdp4_pipe i0) { return 0x00024000 + 0x10000*i0; } i0 821 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_CSC_MV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; } i0 823 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_CSC_MV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; } i0 825 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; } i0 827 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; } i0 829 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; } i0 831 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; } i0 833 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; } i0 835 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; } i0 837 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; } i0 839 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; } i0 938 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL(uint32_t i0) { return 0x000c2014 + 0x8*i0; } i0 940 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(uint32_t i0) { return 0x000c2014 + 0x8*i0; } i0 966 drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h static inline uint32_t REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(uint32_t i0) { return 0x000c2018 + 0x8*i0; } i0 265 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_SMP_ALLOC_W(uint32_t i0) { return 0x00000080 + 0x4*i0; } i0 267 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_SMP_ALLOC_W_REG(uint32_t i0) { return 0x00000080 + 0x4*i0; } i0 287 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_SMP_ALLOC_R(uint32_t i0) { return 0x00000130 + 0x4*i0; } i0 289 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_SMP_ALLOC_R_REG(uint32_t i0) { return 0x00000130 + 0x4*i0; } i0 319 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_IGC(enum mdp5_igc_type i0) { return 0x00000000 + __offset_IGC(i0); } i0 321 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_IGC_LUT(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1; } i0 323 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_IGC_LUT_REG(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1; } i0 360 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_CTL(uint32_t i0) { return 0x00000000 + __offset_CTL(i0); } i0 374 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_CTL_LAYER(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); } i0 376 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_CTL_LAYER_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); } i0 440 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_CTL_OP(uint32_t i0) { return 0x00000014 + __offset_CTL(i0); } i0 462 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_CTL_FLUSH(uint32_t i0) { return 0x00000018 + __offset_CTL(i0); } i0 493 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_CTL_START(uint32_t i0) { return 0x0000001c + __offset_CTL(i0); } i0 495 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_CTL_PACK_3D(uint32_t i0) { return 0x00000020 + __offset_CTL(i0); } i0 509 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_CTL_LAYER_EXT(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER_EXT(i1); } i0 511 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_CTL_LAYER_EXT_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER_EXT(i1); } i0 554 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); } i0 556 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_OP_MODE(enum mdp5_pipe i0) { return 0x00000200 + __offset_PIPE(i0); } i0 571 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_HIST_CTL_BASE(enum mdp5_pipe i0) { return 0x000002c4 + __offset_PIPE(i0); } i0 573 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_HIST_LUT_BASE(enum mdp5_pipe i0) { return 0x000002f0 + __offset_PIPE(i0); } i0 575 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_HIST_LUT_SWAP(enum mdp5_pipe i0) { return 0x00000300 + __offset_PIPE(i0); } i0 577 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(enum mdp5_pipe i0) { return 0x00000320 + __offset_PIPE(i0); } i0 591 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(enum mdp5_pipe i0) { return 0x00000324 + __offset_PIPE(i0); } i0 605 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(enum mdp5_pipe i0) { return 0x00000328 + __offset_PIPE(i0); } i0 619 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(enum mdp5_pipe i0) { return 0x0000032c + __offset_PIPE(i0); } i0 633 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(enum mdp5_pipe i0) { return 0x00000330 + __offset_PIPE(i0); } i0 641 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x4*i1; } i0 643 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x4*i1; } i0 657 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x4*i1; } i0 659 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x4*i1; } i0 673 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_PIPE(i0) + 0x4*i1; } i0 675 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_PIPE(i0) + 0x4*i1; } i0 683 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_PIPE(i0) + 0x4*i1; } i0 685 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_PIPE(i0) + 0x4*i1; } i0 693 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SRC_SIZE(enum mdp5_pipe i0) { return 0x00000000 + __offset_PIPE(i0); } i0 707 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SRC_IMG_SIZE(enum mdp5_pipe i0) { return 0x00000004 + __offset_PIPE(i0); } i0 721 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SRC_XY(enum mdp5_pipe i0) { return 0x00000008 + __offset_PIPE(i0); } i0 735 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_OUT_SIZE(enum mdp5_pipe i0) { return 0x0000000c + __offset_PIPE(i0); } i0 749 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_OUT_XY(enum mdp5_pipe i0) { return 0x00000010 + __offset_PIPE(i0); } i0 763 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SRC0_ADDR(enum mdp5_pipe i0) { return 0x00000014 + __offset_PIPE(i0); } i0 765 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SRC1_ADDR(enum mdp5_pipe i0) { return 0x00000018 + __offset_PIPE(i0); } i0 767 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SRC2_ADDR(enum mdp5_pipe i0) { return 0x0000001c + __offset_PIPE(i0); } i0 769 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SRC3_ADDR(enum mdp5_pipe i0) { return 0x00000020 + __offset_PIPE(i0); } i0 771 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_A(enum mdp5_pipe i0) { return 0x00000024 + __offset_PIPE(i0); } i0 785 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_B(enum mdp5_pipe i0) { return 0x00000028 + __offset_PIPE(i0); } i0 799 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_STILE_FRAME_SIZE(enum mdp5_pipe i0) { return 0x0000002c + __offset_PIPE(i0); } i0 801 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SRC_FORMAT(enum mdp5_pipe i0) { return 0x00000030 + __offset_PIPE(i0); } i0 855 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SRC_UNPACK(enum mdp5_pipe i0) { return 0x00000034 + __offset_PIPE(i0); } i0 881 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SRC_OP_MODE(enum mdp5_pipe i0) { return 0x00000038 + __offset_PIPE(i0); } i0 898 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SRC_CONSTANT_COLOR(enum mdp5_pipe i0) { return 0x0000003c + __offset_PIPE(i0); } i0 900 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_FETCH_CONFIG(enum mdp5_pipe i0) { return 0x00000048 + __offset_PIPE(i0); } i0 902 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_VC1_RANGE(enum mdp5_pipe i0) { return 0x0000004c + __offset_PIPE(i0); } i0 904 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(enum mdp5_pipe i0) { return 0x00000050 + __offset_PIPE(i0); } i0 906 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(enum mdp5_pipe i0) { return 0x00000054 + __offset_PIPE(i0); } i0 908 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(enum mdp5_pipe i0) { return 0x00000058 + __offset_PIPE(i0); } i0 910 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(enum mdp5_pipe i0) { return 0x00000070 + __offset_PIPE(i0); } i0 912 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC0_ADDR(enum mdp5_pipe i0) { return 0x000000a4 + __offset_PIPE(i0); } i0 914 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC1_ADDR(enum mdp5_pipe i0) { return 0x000000a8 + __offset_PIPE(i0); } i0 916 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC2_ADDR(enum mdp5_pipe i0) { return 0x000000ac + __offset_PIPE(i0); } i0 918 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC3_ADDR(enum mdp5_pipe i0) { return 0x000000b0 + __offset_PIPE(i0); } i0 920 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_DECIMATION(enum mdp5_pipe i0) { return 0x000000b4 + __offset_PIPE(i0); } i0 943 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000000 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); } i0 945 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_LR(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000000 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); } i0 971 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_TB(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000004 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); } i0 997 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000008 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); } i0 1011 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SCALE_CONFIG(enum mdp5_pipe i0) { return 0x00000204 + __offset_PIPE(i0); } i0 1051 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000210 + __offset_PIPE(i0); } i0 1053 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x00000214 + __offset_PIPE(i0); } i0 1055 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00000218 + __offset_PIPE(i0); } i0 1057 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x0000021c + __offset_PIPE(i0); } i0 1059 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_X(enum mdp5_pipe i0) { return 0x00000220 + __offset_PIPE(i0); } i0 1061 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_Y(enum mdp5_pipe i0) { return 0x00000224 + __offset_PIPE(i0); } i0 1075 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM(uint32_t i0) { return 0x00000000 + __offset_LM(i0); } i0 1077 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_BLEND_COLOR_OUT(uint32_t i0) { return 0x00000000 + __offset_LM(i0); } i0 1087 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_OUT_SIZE(uint32_t i0) { return 0x00000004 + __offset_LM(i0); } i0 1101 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_BORDER_COLOR_0(uint32_t i0) { return 0x00000008 + __offset_LM(i0); } i0 1103 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_BORDER_COLOR_1(uint32_t i0) { return 0x00000010 + __offset_LM(i0); } i0 1118 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_BLEND(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_LM(i0) + __offset_BLEND(i1); } i0 1120 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_BLEND_OP_MODE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_LM(i0) + __offset_BLEND(i1); } i0 1142 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_BLEND_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_LM(i0) + __offset_BLEND(i1); } i0 1144 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_BLEND_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_LM(i0) + __offset_BLEND(i1); } i0 1146 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000c + __offset_LM(i0) + __offset_BLEND(i1); } i0 1148 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000010 + __offset_LM(i0) + __offset_BLEND(i1); } i0 1150 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000014 + __offset_LM(i0) + __offset_BLEND(i1); } i0 1152 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000018 + __offset_LM(i0) + __offset_BLEND(i1); } i0 1154 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000001c + __offset_LM(i0) + __offset_BLEND(i1); } i0 1156 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000020 + __offset_LM(i0) + __offset_BLEND(i1); } i0 1158 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000024 + __offset_LM(i0) + __offset_BLEND(i1); } i0 1160 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000028 + __offset_LM(i0) + __offset_BLEND(i1); } i0 1162 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_CURSOR_IMG_SIZE(uint32_t i0) { return 0x000000e0 + __offset_LM(i0); } i0 1176 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_CURSOR_SIZE(uint32_t i0) { return 0x000000e4 + __offset_LM(i0); } i0 1190 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_CURSOR_XY(uint32_t i0) { return 0x000000e8 + __offset_LM(i0); } i0 1204 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_CURSOR_STRIDE(uint32_t i0) { return 0x000000dc + __offset_LM(i0); } i0 1212 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_CURSOR_FORMAT(uint32_t i0) { return 0x000000ec + __offset_LM(i0); } i0 1220 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_CURSOR_BASE_ADDR(uint32_t i0) { return 0x000000f0 + __offset_LM(i0); } i0 1222 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_CURSOR_START_XY(uint32_t i0) { return 0x000000f4 + __offset_LM(i0); } i0 1236 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_CONFIG(uint32_t i0) { return 0x000000f8 + __offset_LM(i0); } i0 1246 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_PARAM(uint32_t i0) { return 0x000000fc + __offset_LM(i0); } i0 1248 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0(uint32_t i0) { return 0x00000100 + __offset_LM(i0); } i0 1250 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1(uint32_t i0) { return 0x00000104 + __offset_LM(i0); } i0 1252 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0(uint32_t i0) { return 0x00000108 + __offset_LM(i0); } i0 1254 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1(uint32_t i0) { return 0x0000010c + __offset_LM(i0); } i0 1256 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_LM_GC_LUT_BASE(uint32_t i0) { return 0x00000110 + __offset_LM(i0); } i0 1268 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_DSPP(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); } i0 1270 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_DSPP_OP_MODE(uint32_t i0) { return 0x00000000 + __offset_DSPP(i0); } i0 1287 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_DSPP_PCC_BASE(uint32_t i0) { return 0x00000030 + __offset_DSPP(i0); } i0 1289 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_DSPP_DITHER_DEPTH(uint32_t i0) { return 0x00000150 + __offset_DSPP(i0); } i0 1291 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_DSPP_HIST_CTL_BASE(uint32_t i0) { return 0x00000210 + __offset_DSPP(i0); } i0 1293 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_DSPP_HIST_LUT_BASE(uint32_t i0) { return 0x00000230 + __offset_DSPP(i0); } i0 1295 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_DSPP_HIST_LUT_SWAP(uint32_t i0) { return 0x00000234 + __offset_DSPP(i0); } i0 1297 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_DSPP_PA_BASE(uint32_t i0) { return 0x00000238 + __offset_DSPP(i0); } i0 1299 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_DSPP_GAMUT_BASE(uint32_t i0) { return 0x000002dc + __offset_DSPP(i0); } i0 1301 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_DSPP_GC_BASE(uint32_t i0) { return 0x000002b0 + __offset_DSPP(i0); } i0 1313 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PP(uint32_t i0) { return 0x00000000 + __offset_PP(i0); } i0 1315 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PP_TEAR_CHECK_EN(uint32_t i0) { return 0x00000000 + __offset_PP(i0); } i0 1317 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PP_SYNC_CONFIG_VSYNC(uint32_t i0) { return 0x00000004 + __offset_PP(i0); } i0 1327 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PP_SYNC_CONFIG_HEIGHT(uint32_t i0) { return 0x00000008 + __offset_PP(i0); } i0 1329 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PP_SYNC_WRCOUNT(uint32_t i0) { return 0x0000000c + __offset_PP(i0); } i0 1343 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PP_VSYNC_INIT_VAL(uint32_t i0) { return 0x00000010 + __offset_PP(i0); } i0 1345 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PP_INT_COUNT_VAL(uint32_t i0) { return 0x00000014 + __offset_PP(i0); } i0 1359 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PP_SYNC_THRESH(uint32_t i0) { return 0x00000018 + __offset_PP(i0); } i0 1373 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PP_START_POS(uint32_t i0) { return 0x0000001c + __offset_PP(i0); } i0 1375 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PP_RD_PTR_IRQ(uint32_t i0) { return 0x00000020 + __offset_PP(i0); } i0 1377 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PP_WR_PTR_IRQ(uint32_t i0) { return 0x00000024 + __offset_PP(i0); } i0 1379 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PP_OUT_LINE_COUNT(uint32_t i0) { return 0x00000028 + __offset_PP(i0); } i0 1381 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PP_PP_LINE_COUNT(uint32_t i0) { return 0x0000002c + __offset_PP(i0); } i0 1383 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PP_AUTOREFRESH_CONFIG(uint32_t i0) { return 0x00000030 + __offset_PP(i0); } i0 1385 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PP_FBC_MODE(uint32_t i0) { return 0x00000034 + __offset_PP(i0); } i0 1387 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PP_FBC_BUDGET_CTL(uint32_t i0) { return 0x00000038 + __offset_PP(i0); } i0 1389 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_PP_FBC_LOSSY_MODE(uint32_t i0) { return 0x0000003c + __offset_PP(i0); } i0 1404 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB(uint32_t i0) { return 0x00000000 + __offset_WB(i0); } i0 1406 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_DST_FORMAT(uint32_t i0) { return 0x00000000 + __offset_WB(i0); } i0 1473 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_DST_OP_MODE(uint32_t i0) { return 0x00000004 + __offset_WB(i0); } i0 1527 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_DST_PACK_PATTERN(uint32_t i0) { return 0x00000008 + __offset_WB(i0); } i0 1553 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_DST0_ADDR(uint32_t i0) { return 0x0000000c + __offset_WB(i0); } i0 1555 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_DST1_ADDR(uint32_t i0) { return 0x00000010 + __offset_WB(i0); } i0 1557 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_DST2_ADDR(uint32_t i0) { return 0x00000014 + __offset_WB(i0); } i0 1559 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_DST3_ADDR(uint32_t i0) { return 0x00000018 + __offset_WB(i0); } i0 1561 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_DST_YSTRIDE0(uint32_t i0) { return 0x0000001c + __offset_WB(i0); } i0 1575 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_DST_YSTRIDE1(uint32_t i0) { return 0x00000020 + __offset_WB(i0); } i0 1589 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_DST_DITHER_BITDEPTH(uint32_t i0) { return 0x00000024 + __offset_WB(i0); } i0 1591 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW0(uint32_t i0) { return 0x00000030 + __offset_WB(i0); } i0 1593 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW1(uint32_t i0) { return 0x00000034 + __offset_WB(i0); } i0 1595 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW2(uint32_t i0) { return 0x00000038 + __offset_WB(i0); } i0 1597 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_DITHER_MATRIX_ROW3(uint32_t i0) { return 0x0000003c + __offset_WB(i0); } i0 1599 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_DST_WRITE_CONFIG(uint32_t i0) { return 0x00000048 + __offset_WB(i0); } i0 1601 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_ROTATION_DNSCALER(uint32_t i0) { return 0x00000050 + __offset_WB(i0); } i0 1603 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_X_0_3(uint32_t i0) { return 0x00000060 + __offset_WB(i0); } i0 1605 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_X_1_2(uint32_t i0) { return 0x00000064 + __offset_WB(i0); } i0 1607 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_Y_0_3(uint32_t i0) { return 0x00000068 + __offset_WB(i0); } i0 1609 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_N16_INIT_PHASE_Y_1_2(uint32_t i0) { return 0x0000006c + __offset_WB(i0); } i0 1611 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_OUT_SIZE(uint32_t i0) { return 0x00000074 + __offset_WB(i0); } i0 1625 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_ALPHA_X_VALUE(uint32_t i0) { return 0x00000078 + __offset_WB(i0); } i0 1627 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_0(uint32_t i0) { return 0x00000260 + __offset_WB(i0); } i0 1641 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_1(uint32_t i0) { return 0x00000264 + __offset_WB(i0); } i0 1655 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_2(uint32_t i0) { return 0x00000268 + __offset_WB(i0); } i0 1669 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_3(uint32_t i0) { return 0x0000026c + __offset_WB(i0); } i0 1683 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_CSC_MATRIX_COEFF_4(uint32_t i0) { return 0x00000270 + __offset_WB(i0); } i0 1691 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP(uint32_t i0, uint32_t i1) { return 0x00000274 + __offset_WB(i0) + 0x4*i1; } i0 1693 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000274 + __offset_WB(i0) + 0x4*i1; } i0 1707 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP(uint32_t i0, uint32_t i1) { return 0x00000280 + __offset_WB(i0) + 0x4*i1; } i0 1709 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000280 + __offset_WB(i0) + 0x4*i1; } i0 1723 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS(uint32_t i0, uint32_t i1) { return 0x0000028c + __offset_WB(i0) + 0x4*i1; } i0 1725 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS_REG(uint32_t i0, uint32_t i1) { return 0x0000028c + __offset_WB(i0) + 0x4*i1; } i0 1733 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS(uint32_t i0, uint32_t i1) { return 0x00000298 + __offset_WB(i0) + 0x4*i1; } i0 1735 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS_REG(uint32_t i0, uint32_t i1) { return 0x00000298 + __offset_WB(i0) + 0x4*i1; } i0 1754 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); } i0 1756 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_TIMING_ENGINE_EN(uint32_t i0) { return 0x00000000 + __offset_INTF(i0); } i0 1758 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_CONFIG(uint32_t i0) { return 0x00000004 + __offset_INTF(i0); } i0 1760 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_HSYNC_CTL(uint32_t i0) { return 0x00000008 + __offset_INTF(i0); } i0 1774 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F0(uint32_t i0) { return 0x0000000c + __offset_INTF(i0); } i0 1776 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F1(uint32_t i0) { return 0x00000010 + __offset_INTF(i0); } i0 1778 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F0(uint32_t i0) { return 0x00000014 + __offset_INTF(i0); } i0 1780 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F1(uint32_t i0) { return 0x00000018 + __offset_INTF(i0); } i0 1782 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F0(uint32_t i0) { return 0x0000001c + __offset_INTF(i0); } i0 1784 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F1(uint32_t i0) { return 0x00000020 + __offset_INTF(i0); } i0 1786 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F0(uint32_t i0) { return 0x00000024 + __offset_INTF(i0); } i0 1788 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F1(uint32_t i0) { return 0x00000028 + __offset_INTF(i0); } i0 1790 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F0(uint32_t i0) { return 0x0000002c + __offset_INTF(i0); } i0 1799 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F1(uint32_t i0) { return 0x00000030 + __offset_INTF(i0); } i0 1807 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F0(uint32_t i0) { return 0x00000034 + __offset_INTF(i0); } i0 1809 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F1(uint32_t i0) { return 0x00000038 + __offset_INTF(i0); } i0 1811 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_DISPLAY_HCTL(uint32_t i0) { return 0x0000003c + __offset_INTF(i0); } i0 1825 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_ACTIVE_HCTL(uint32_t i0) { return 0x00000040 + __offset_INTF(i0); } i0 1840 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_BORDER_COLOR(uint32_t i0) { return 0x00000044 + __offset_INTF(i0); } i0 1842 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_UNDERFLOW_COLOR(uint32_t i0) { return 0x00000048 + __offset_INTF(i0); } i0 1844 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_HSYNC_SKEW(uint32_t i0) { return 0x0000004c + __offset_INTF(i0); } i0 1846 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_POLARITY_CTL(uint32_t i0) { return 0x00000050 + __offset_INTF(i0); } i0 1851 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_TEST_CTL(uint32_t i0) { return 0x00000054 + __offset_INTF(i0); } i0 1853 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_TP_COLOR0(uint32_t i0) { return 0x00000058 + __offset_INTF(i0); } i0 1855 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_TP_COLOR1(uint32_t i0) { return 0x0000005c + __offset_INTF(i0); } i0 1857 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN(uint32_t i0) { return 0x00000084 + __offset_INTF(i0); } i0 1859 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_PANEL_FORMAT(uint32_t i0) { return 0x00000090 + __offset_INTF(i0); } i0 1861 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_FRAME_LINE_COUNT_EN(uint32_t i0) { return 0x000000a8 + __offset_INTF(i0); } i0 1863 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_FRAME_COUNT(uint32_t i0) { return 0x000000ac + __offset_INTF(i0); } i0 1865 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_LINE_COUNT(uint32_t i0) { return 0x000000b0 + __offset_INTF(i0); } i0 1867 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_DEFLICKER_CONFIG(uint32_t i0) { return 0x000000f0 + __offset_INTF(i0); } i0 1869 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_DEFLICKER_STRNG_COEFF(uint32_t i0) { return 0x000000f4 + __offset_INTF(i0); } i0 1871 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_DEFLICKER_WEAK_COEFF(uint32_t i0) { return 0x000000f8 + __offset_INTF(i0); } i0 1873 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_TPG_ENABLE(uint32_t i0) { return 0x00000100 + __offset_INTF(i0); } i0 1875 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_TPG_MAIN_CONTROL(uint32_t i0) { return 0x00000104 + __offset_INTF(i0); } i0 1877 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_TPG_VIDEO_CONFIG(uint32_t i0) { return 0x00000108 + __offset_INTF(i0); } i0 1879 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_TPG_COMPONENT_LIMITS(uint32_t i0) { return 0x0000010c + __offset_INTF(i0); } i0 1881 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_TPG_RECTANGLE(uint32_t i0) { return 0x00000110 + __offset_INTF(i0); } i0 1883 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_TPG_INITIAL_VALUE(uint32_t i0) { return 0x00000114 + __offset_INTF(i0); } i0 1885 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME(uint32_t i0) { return 0x00000118 + __offset_INTF(i0); } i0 1887 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_INTF_TPG_RGB_MAPPING(uint32_t i0) { return 0x0000011c + __offset_INTF(i0); } i0 1897 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD(uint32_t i0) { return 0x00000000 + __offset_AD(i0); } i0 1899 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_BYPASS(uint32_t i0) { return 0x00000000 + __offset_AD(i0); } i0 1901 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_CTRL_0(uint32_t i0) { return 0x00000004 + __offset_AD(i0); } i0 1903 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_CTRL_1(uint32_t i0) { return 0x00000008 + __offset_AD(i0); } i0 1905 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_FRAME_SIZE(uint32_t i0) { return 0x0000000c + __offset_AD(i0); } i0 1907 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_CON_CTRL_0(uint32_t i0) { return 0x00000010 + __offset_AD(i0); } i0 1909 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_CON_CTRL_1(uint32_t i0) { return 0x00000014 + __offset_AD(i0); } i0 1911 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_STR_MAN(uint32_t i0) { return 0x00000018 + __offset_AD(i0); } i0 1913 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_VAR(uint32_t i0) { return 0x0000001c + __offset_AD(i0); } i0 1915 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_DITH(uint32_t i0) { return 0x00000020 + __offset_AD(i0); } i0 1917 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_DITH_CTRL(uint32_t i0) { return 0x00000024 + __offset_AD(i0); } i0 1919 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_AMP_LIM(uint32_t i0) { return 0x00000028 + __offset_AD(i0); } i0 1921 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_SLOPE(uint32_t i0) { return 0x0000002c + __offset_AD(i0); } i0 1923 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_BW_LVL(uint32_t i0) { return 0x00000030 + __offset_AD(i0); } i0 1925 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_LOGO_POS(uint32_t i0) { return 0x00000034 + __offset_AD(i0); } i0 1927 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_LUT_FI(uint32_t i0) { return 0x00000038 + __offset_AD(i0); } i0 1929 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_LUT_CC(uint32_t i0) { return 0x0000007c + __offset_AD(i0); } i0 1931 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_STR_LIM(uint32_t i0) { return 0x000000c8 + __offset_AD(i0); } i0 1933 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_CALIB_AB(uint32_t i0) { return 0x000000cc + __offset_AD(i0); } i0 1935 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_CALIB_CD(uint32_t i0) { return 0x000000d0 + __offset_AD(i0); } i0 1937 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_MODE_SEL(uint32_t i0) { return 0x000000d4 + __offset_AD(i0); } i0 1939 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_TFILT_CTRL(uint32_t i0) { return 0x000000d8 + __offset_AD(i0); } i0 1941 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_BL_MINMAX(uint32_t i0) { return 0x000000dc + __offset_AD(i0); } i0 1943 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_BL(uint32_t i0) { return 0x000000e0 + __offset_AD(i0); } i0 1945 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_BL_MAX(uint32_t i0) { return 0x000000e8 + __offset_AD(i0); } i0 1947 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_AL(uint32_t i0) { return 0x000000ec + __offset_AD(i0); } i0 1949 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_AL_MIN(uint32_t i0) { return 0x000000f0 + __offset_AD(i0); } i0 1951 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_AL_FILT(uint32_t i0) { return 0x000000f4 + __offset_AD(i0); } i0 1953 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_CFG_BUF(uint32_t i0) { return 0x000000f8 + __offset_AD(i0); } i0 1955 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_LUT_AL(uint32_t i0) { return 0x00000100 + __offset_AD(i0); } i0 1957 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_TARG_STR(uint32_t i0) { return 0x00000144 + __offset_AD(i0); } i0 1959 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_START_CALC(uint32_t i0) { return 0x00000148 + __offset_AD(i0); } i0 1961 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_STR_OUT(uint32_t i0) { return 0x0000014c + __offset_AD(i0); } i0 1963 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_BL_OUT(uint32_t i0) { return 0x00000154 + __offset_AD(i0); } i0 1965 drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h static inline uint32_t REG_MDP5_AD_CALC_DONE(uint32_t i0) { return 0x00000158 + __offset_AD(i0); } i0 357 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_RDBK(uint32_t i0) { return 0x00000068 + 0x4*i0; } i0 359 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_RDBK_DATA(uint32_t i0) { return 0x00000068 + 0x4*i0; } i0 571 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } i0 573 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } i0 575 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } i0 577 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } i0 579 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x40*i0; } i0 581 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x00000014 + 0x40*i0; } i0 583 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000018 + 0x40*i0; } i0 800 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } i0 802 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } i0 804 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } i0 806 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } i0 808 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; } i0 810 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; } i0 812 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; } i0 814 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_28nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; } i0 816 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; } i0 818 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; } i0 1127 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_20nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } i0 1129 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } i0 1131 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } i0 1133 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } i0 1135 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; } i0 1137 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; } i0 1139 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; } i0 1141 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_20nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; } i0 1143 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; } i0 1145 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; } i0 1368 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_14nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; } i0 1370 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_14nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; } i0 1378 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_14nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; } i0 1381 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_14nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; } i0 1383 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_14nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; } i0 1385 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0; } i0 1387 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_STR(uint32_t i0) { return 0x00000014 + 0x80*i0; } i0 1389 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(uint32_t i0) { return 0x00000018 + 0x80*i0; } i0 1397 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(uint32_t i0) { return 0x0000001c + 0x80*i0; } i0 1405 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(uint32_t i0) { return 0x00000020 + 0x80*i0; } i0 1413 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(uint32_t i0) { return 0x00000024 + 0x80*i0; } i0 1421 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(uint32_t i0) { return 0x00000028 + 0x80*i0; } i0 1429 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(uint32_t i0) { return 0x0000002c + 0x80*i0; } i0 1443 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(uint32_t i0) { return 0x00000030 + 0x80*i0; } i0 1451 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(uint32_t i0) { return 0x00000034 + 0x80*i0; } i0 1459 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(uint32_t i0) { return 0x00000038 + 0x80*i0; } i0 1461 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(uint32_t i0) { return 0x0000003c + 0x80*i0; } i0 1463 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_14nm_PHY_LN_VREG_CNTRL(uint32_t i0) { return 0x00000064 + 0x80*i0; } i0 1629 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_10nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; } i0 1631 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_10nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; } i0 1633 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_10nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; } i0 1635 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_10nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; } i0 1637 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_10nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; } i0 1639 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_10nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0; } i0 1641 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_10nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000014 + 0x80*i0; } i0 1643 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL(uint32_t i0) { return 0x00000018 + 0x80*i0; } i0 1645 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL(uint32_t i0) { return 0x0000001c + 0x80*i0; } i0 1647 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL(uint32_t i0) { return 0x00000020 + 0x80*i0; } i0 1649 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(uint32_t i0) { return 0x00000024 + 0x80*i0; } i0 1651 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_10nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000028 + 0x80*i0; } i0 1653 drivers/gpu/drm/msm/dsi/dsi.xml.h static inline uint32_t REG_DSI_10nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x0000002c + 0x80*i0; } i0 64 drivers/gpu/drm/msm/dsi/mmss_cc.xml.h static inline uint32_t REG_MMSS_CC_CLK(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i0); } i0 66 drivers/gpu/drm/msm/dsi/mmss_cc.xml.h static inline uint32_t REG_MMSS_CC_CLK_CC(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i0); } i0 83 drivers/gpu/drm/msm/dsi/mmss_cc.xml.h static inline uint32_t REG_MMSS_CC_CLK_MD(enum mmss_cc_clk i0) { return 0x00000004 + __offset_CLK(i0); } i0 97 drivers/gpu/drm/msm/dsi/mmss_cc.xml.h static inline uint32_t REG_MMSS_CC_CLK_NS(enum mmss_cc_clk i0) { return 0x00000008 + __offset_CLK(i0); } i0 276 drivers/gpu/drm/msm/edp/edp.xml.h static inline uint32_t REG_EDP_PHY_LN(uint32_t i0) { return 0x00000400 + 0x40*i0; } i0 278 drivers/gpu/drm/msm/edp/edp.xml.h static inline uint32_t REG_EDP_PHY_LN_PD_CTL(uint32_t i0) { return 0x00000404 + 0x40*i0; } i0 171 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t REG_HDMI_AVI_INFO(uint32_t i0) { return 0x0000006c + 0x4*i0; } i0 175 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t REG_HDMI_GENERIC0(uint32_t i0) { return 0x00000088 + 0x4*i0; } i0 179 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t REG_HDMI_GENERIC1(uint32_t i0) { return 0x000000a8 + 0x4*i0; } i0 181 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t REG_HDMI_ACR(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; } i0 183 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t REG_HDMI_ACR_0(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; } i0 191 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t REG_HDMI_ACR_1(enum hdmi_acr_cts i0) { return 0x000000c8 + 0x8*i0; } i0 388 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t REG_HDMI_I2C_TRANSACTION(uint32_t i0) { return 0x00000228 + 0x4*i0; } i0 390 drivers/gpu/drm/msm/hdmi/hdmi.xml.h static inline uint32_t REG_HDMI_I2C_TRANSACTION_REG(uint32_t i0) { return 0x00000228 + 0x4*i0; } i0 477 drivers/gpu/drm/savage/savage_drv.h #define BCI_DRAW_INDICES_S3D(n, type, i0) \ i0 479 drivers/gpu/drm/savage/savage_drv.h ((n) << 16) | (i0)) i0 105 fs/jffs2/compr_rubin.c long i0, i1; i0 119 fs/jffs2/compr_rubin.c i0 = A * rs->p / (A + B); i0 120 fs/jffs2/compr_rubin.c if (i0 <= 0) i0 121 fs/jffs2/compr_rubin.c i0 = 1; i0 123 fs/jffs2/compr_rubin.c if (i0 >= rs->p) i0 124 fs/jffs2/compr_rubin.c i0 = rs->p - 1; i0 126 fs/jffs2/compr_rubin.c i1 = rs->p - i0; i0 129 fs/jffs2/compr_rubin.c rs->p = i0; i0 132 fs/jffs2/compr_rubin.c rs->q += i0; i0 203 fs/jffs2/compr_rubin.c long i0, threshold; i0 209 fs/jffs2/compr_rubin.c i0 = A * rs->p / (A + B); i0 210 fs/jffs2/compr_rubin.c if (i0 <= 0) i0 211 fs/jffs2/compr_rubin.c i0 = 1; i0 213 fs/jffs2/compr_rubin.c if (i0 >= rs->p) i0 214 fs/jffs2/compr_rubin.c i0 = rs->p - 1; i0 216 fs/jffs2/compr_rubin.c threshold = rs->q + i0; i0 219 fs/jffs2/compr_rubin.c rs->q += i0; i0 220 fs/jffs2/compr_rubin.c i0 = rs->p - i0; i0 223 fs/jffs2/compr_rubin.c rs->p = i0; i0 3375 fs/jfs/jfs_dmap.c int i, i0 = true, j, j0 = true, k, n; i0 3503 fs/jfs/jfs_dmap.c if (i0) { i0 3517 fs/jfs/jfs_dmap.c i0 = false; i0 1110 sound/pci/cs46xx/cs46xx_dsp_scb_types.h u32 i0; i0 28 tools/testing/selftests/proc/proc-uptime-001.c uint64_t start, u0, u1, i0, i1; i0 34 tools/testing/selftests/proc/proc-uptime-001.c proc_uptime(fd, &u0, &i0); i0 39 tools/testing/selftests/proc/proc-uptime-001.c assert(i1 >= i0); i0 41 tools/testing/selftests/proc/proc-uptime-001.c i0 = i1; i0 48 tools/testing/selftests/proc/proc-uptime-002.c uint64_t u0, u1, i0, i1; i0 63 tools/testing/selftests/proc/proc-uptime-002.c proc_uptime(fd, &u0, &i0); i0 73 tools/testing/selftests/proc/proc-uptime-002.c assert(i1 >= i0); i0 75 tools/testing/selftests/proc/proc-uptime-002.c i0 = i1;