hwsp_offset 1294 drivers/gpu/drm/i915/gt/intel_engine_cs.c rq->timeline->hwsp_offset, hwsp_offset 1306 drivers/gpu/drm/i915/gt/intel_engine_cs.c rq->timeline->hwsp_offset, hwsp_offset 1399 drivers/gpu/drm/i915/gt/intel_engine_cs.c rq->timeline->hwsp_offset); hwsp_offset 1890 drivers/gpu/drm/i915/gt/intel_lrc.c *cs++ = rq->timeline->hwsp_offset; hwsp_offset 2946 drivers/gpu/drm/i915/gt/intel_lrc.c request->timeline->hwsp_offset, hwsp_offset 2956 drivers/gpu/drm/i915/gt/intel_lrc.c request->timeline->hwsp_offset, hwsp_offset 2975 drivers/gpu/drm/i915/gt/intel_lrc.c request->timeline->hwsp_offset, hwsp_offset 325 drivers/gpu/drm/i915/gt/intel_ringbuffer.c *cs++ = rq->timeline->hwsp_offset | PIPE_CONTROL_GLOBAL_GTT; hwsp_offset 428 drivers/gpu/drm/i915/gt/intel_ringbuffer.c *cs++ = rq->timeline->hwsp_offset; hwsp_offset 443 drivers/gpu/drm/i915/gt/intel_ringbuffer.c GEM_BUG_ON(offset_in_page(rq->timeline->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); hwsp_offset 463 drivers/gpu/drm/i915/gt/intel_ringbuffer.c GEM_BUG_ON(offset_in_page(rq->timeline->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); hwsp_offset 941 drivers/gpu/drm/i915/gt/intel_ringbuffer.c GEM_BUG_ON(offset_in_page(rq->timeline->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); hwsp_offset 964 drivers/gpu/drm/i915/gt/intel_ringbuffer.c GEM_BUG_ON(offset_in_page(rq->timeline->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR); hwsp_offset 236 drivers/gpu/drm/i915/gt/intel_timeline.c timeline->hwsp_offset = cacheline * CACHELINE_BYTES; hwsp_offset 240 drivers/gpu/drm/i915/gt/intel_timeline.c timeline->hwsp_offset = I915_GEM_HWS_SEQNO_ADDR; hwsp_offset 248 drivers/gpu/drm/i915/gt/intel_timeline.c memset(vaddr + timeline->hwsp_offset, 0, CACHELINE_BYTES); hwsp_offset 251 drivers/gpu/drm/i915/gt/intel_timeline.c GEM_BUG_ON(timeline->hwsp_offset >= hwsp->size); hwsp_offset 324 drivers/gpu/drm/i915/gt/intel_timeline.c tl->hwsp_offset = hwsp_offset 326 drivers/gpu/drm/i915/gt/intel_timeline.c offset_in_page(tl->hwsp_offset); hwsp_offset 458 drivers/gpu/drm/i915/gt/intel_timeline.c tl->hwsp_offset = cacheline * CACHELINE_BYTES; hwsp_offset 460 drivers/gpu/drm/i915/gt/intel_timeline.c memset(vaddr + tl->hwsp_offset, 0, CACHELINE_BYTES); hwsp_offset 462 drivers/gpu/drm/i915/gt/intel_timeline.c tl->hwsp_offset += i915_ggtt_offset(vma); hwsp_offset 515 drivers/gpu/drm/i915/gt/intel_timeline.c *hwsp = tl->hwsp_offset; hwsp_offset 89 drivers/gpu/drm/i915/gt/intel_timeline.h u32 *hwsp_offset); hwsp_offset 49 drivers/gpu/drm/i915/gt/intel_timeline_types.h u32 hwsp_offset; hwsp_offset 31 drivers/gpu/drm/i915/gt/selftest_timeline.c return (address + tl->hwsp_offset) / CACHELINE_BYTES; hwsp_offset 464 drivers/gpu/drm/i915/gt/selftest_timeline.c err = emit_ggtt_store_dw(rq, tl->hwsp_offset, value); hwsp_offset 700 drivers/gpu/drm/i915/gt/selftest_timeline.c seqno[0], tl->hwsp_offset); hwsp_offset 702 drivers/gpu/drm/i915/gt/selftest_timeline.c err = emit_ggtt_store_dw(rq, tl->hwsp_offset, seqno[0]); hwsp_offset 717 drivers/gpu/drm/i915/gt/selftest_timeline.c seqno[1], tl->hwsp_offset); hwsp_offset 719 drivers/gpu/drm/i915/gt/selftest_timeline.c err = emit_ggtt_store_dw(rq, tl->hwsp_offset, seqno[1]); hwsp_offset 836 drivers/gpu/drm/i915/i915_request.c u32 hwsp_offset; hwsp_offset 859 drivers/gpu/drm/i915/i915_request.c err = intel_timeline_read_hwsp(from, to, &hwsp_offset); hwsp_offset 880 drivers/gpu/drm/i915/i915_request.c *cs++ = hwsp_offset;