hwsp              534 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	i915_reg_t hwsp;
hwsp              550 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 			hwsp = RENDER_HWS_PGA_GEN7;
hwsp              553 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 			hwsp = BLT_HWS_PGA_GEN7;
hwsp              556 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 			hwsp = BSD_HWS_PGA_GEN7;
hwsp              559 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 			hwsp = VEBOX_HWS_PGA_GEN7;
hwsp              563 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		hwsp = RING_HWS_PGA_GEN6(engine->mmio_base);
hwsp              565 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 		hwsp = RING_HWS_PGA(engine->mmio_base);
hwsp              568 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	I915_WRITE(hwsp, offset);
hwsp              569 drivers/gpu/drm/i915/gt/intel_ringbuffer.c 	POSTING_READ(hwsp);
hwsp               28 drivers/gpu/drm/i915/gt/intel_timeline.c 	struct intel_timeline_hwsp *hwsp;
hwsp               57 drivers/gpu/drm/i915/gt/intel_timeline.c 	struct intel_timeline_hwsp *hwsp;
hwsp               64 drivers/gpu/drm/i915/gt/intel_timeline.c 	hwsp = list_first_entry_or_null(&gt->hwsp_free_list,
hwsp               65 drivers/gpu/drm/i915/gt/intel_timeline.c 					typeof(*hwsp), free_link);
hwsp               66 drivers/gpu/drm/i915/gt/intel_timeline.c 	if (!hwsp) {
hwsp               71 drivers/gpu/drm/i915/gt/intel_timeline.c 		hwsp = kmalloc(sizeof(*hwsp), GFP_KERNEL);
hwsp               72 drivers/gpu/drm/i915/gt/intel_timeline.c 		if (!hwsp)
hwsp               77 drivers/gpu/drm/i915/gt/intel_timeline.c 			kfree(hwsp);
hwsp               81 drivers/gpu/drm/i915/gt/intel_timeline.c 		vma->private = hwsp;
hwsp               82 drivers/gpu/drm/i915/gt/intel_timeline.c 		hwsp->gt = timeline->gt;
hwsp               83 drivers/gpu/drm/i915/gt/intel_timeline.c 		hwsp->vma = vma;
hwsp               84 drivers/gpu/drm/i915/gt/intel_timeline.c 		hwsp->free_bitmap = ~0ull;
hwsp               85 drivers/gpu/drm/i915/gt/intel_timeline.c 		hwsp->gt_timelines = gt;
hwsp               88 drivers/gpu/drm/i915/gt/intel_timeline.c 		list_add(&hwsp->free_link, &gt->hwsp_free_list);
hwsp               91 drivers/gpu/drm/i915/gt/intel_timeline.c 	GEM_BUG_ON(!hwsp->free_bitmap);
hwsp               92 drivers/gpu/drm/i915/gt/intel_timeline.c 	*cacheline = __ffs64(hwsp->free_bitmap);
hwsp               93 drivers/gpu/drm/i915/gt/intel_timeline.c 	hwsp->free_bitmap &= ~BIT_ULL(*cacheline);
hwsp               94 drivers/gpu/drm/i915/gt/intel_timeline.c 	if (!hwsp->free_bitmap)
hwsp               95 drivers/gpu/drm/i915/gt/intel_timeline.c 		list_del(&hwsp->free_link);
hwsp               99 drivers/gpu/drm/i915/gt/intel_timeline.c 	GEM_BUG_ON(hwsp->vma->private != hwsp);
hwsp              100 drivers/gpu/drm/i915/gt/intel_timeline.c 	return hwsp->vma;
hwsp              103 drivers/gpu/drm/i915/gt/intel_timeline.c static void __idle_hwsp_free(struct intel_timeline_hwsp *hwsp, int cacheline)
hwsp              105 drivers/gpu/drm/i915/gt/intel_timeline.c 	struct intel_gt_timelines *gt = hwsp->gt_timelines;
hwsp              111 drivers/gpu/drm/i915/gt/intel_timeline.c 	if (!hwsp->free_bitmap)
hwsp              112 drivers/gpu/drm/i915/gt/intel_timeline.c 		list_add_tail(&hwsp->free_link, &gt->hwsp_free_list);
hwsp              114 drivers/gpu/drm/i915/gt/intel_timeline.c 	GEM_BUG_ON(cacheline >= BITS_PER_TYPE(hwsp->free_bitmap));
hwsp              115 drivers/gpu/drm/i915/gt/intel_timeline.c 	hwsp->free_bitmap |= BIT_ULL(cacheline);
hwsp              118 drivers/gpu/drm/i915/gt/intel_timeline.c 	if (hwsp->free_bitmap == ~0ull) {
hwsp              119 drivers/gpu/drm/i915/gt/intel_timeline.c 		i915_vma_put(hwsp->vma);
hwsp              120 drivers/gpu/drm/i915/gt/intel_timeline.c 		list_del(&hwsp->free_link);
hwsp              121 drivers/gpu/drm/i915/gt/intel_timeline.c 		kfree(hwsp);
hwsp              131 drivers/gpu/drm/i915/gt/intel_timeline.c 	i915_gem_object_unpin_map(cl->hwsp->vma->obj);
hwsp              132 drivers/gpu/drm/i915/gt/intel_timeline.c 	i915_vma_put(cl->hwsp->vma);
hwsp              133 drivers/gpu/drm/i915/gt/intel_timeline.c 	__idle_hwsp_free(cl->hwsp, ptr_unmask_bits(cl->vaddr, CACHELINE_BITS));
hwsp              144 drivers/gpu/drm/i915/gt/intel_timeline.c 	i915_vma_unpin(cl->hwsp->vma);
hwsp              154 drivers/gpu/drm/i915/gt/intel_timeline.c 	__i915_vma_pin(cl->hwsp->vma);
hwsp              159 drivers/gpu/drm/i915/gt/intel_timeline.c cacheline_alloc(struct intel_timeline_hwsp *hwsp, unsigned int cacheline)
hwsp              170 drivers/gpu/drm/i915/gt/intel_timeline.c 	vaddr = i915_gem_object_pin_map(hwsp->vma->obj, I915_MAP_WB);
hwsp              176 drivers/gpu/drm/i915/gt/intel_timeline.c 	i915_vma_get(hwsp->vma);
hwsp              177 drivers/gpu/drm/i915/gt/intel_timeline.c 	cl->hwsp = hwsp;
hwsp              180 drivers/gpu/drm/i915/gt/intel_timeline.c 	i915_active_init(hwsp->gt->i915, &cl->active,
hwsp              209 drivers/gpu/drm/i915/gt/intel_timeline.c 			struct i915_vma *hwsp)
hwsp              218 drivers/gpu/drm/i915/gt/intel_timeline.c 	timeline->has_initial_breadcrumb = !hwsp;
hwsp              221 drivers/gpu/drm/i915/gt/intel_timeline.c 	if (!hwsp) {
hwsp              225 drivers/gpu/drm/i915/gt/intel_timeline.c 		hwsp = hwsp_alloc(timeline, &cacheline);
hwsp              226 drivers/gpu/drm/i915/gt/intel_timeline.c 		if (IS_ERR(hwsp))
hwsp              227 drivers/gpu/drm/i915/gt/intel_timeline.c 			return PTR_ERR(hwsp);
hwsp              229 drivers/gpu/drm/i915/gt/intel_timeline.c 		cl = cacheline_alloc(hwsp->private, cacheline);
hwsp              231 drivers/gpu/drm/i915/gt/intel_timeline.c 			__idle_hwsp_free(hwsp->private, cacheline);
hwsp              242 drivers/gpu/drm/i915/gt/intel_timeline.c 		vaddr = i915_gem_object_pin_map(hwsp->obj, I915_MAP_WB);
hwsp              250 drivers/gpu/drm/i915/gt/intel_timeline.c 	timeline->hwsp_ggtt = i915_vma_get(hwsp);
hwsp              251 drivers/gpu/drm/i915/gt/intel_timeline.c 	GEM_BUG_ON(timeline->hwsp_offset >= hwsp->size);
hwsp              438 drivers/gpu/drm/i915/gt/intel_timeline.c 	GEM_BUG_ON(cl->hwsp->vma != vma);
hwsp              501 drivers/gpu/drm/i915/gt/intel_timeline.c 			     u32 *hwsp)
hwsp              515 drivers/gpu/drm/i915/gt/intel_timeline.c 			*hwsp = tl->hwsp_offset;
hwsp              517 drivers/gpu/drm/i915/gt/intel_timeline.c 			*hwsp = i915_ggtt_offset(cl->hwsp->vma) +
hwsp               36 drivers/gpu/drm/i915/gt/intel_timeline.h 			struct i915_vma *hwsp);