hwmgr            2679 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
hwmgr            2681 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		if (hwmgr && hwmgr->hwmgr_func &&
hwmgr            2682 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 		    hwmgr->hwmgr_func->update_nbdpm_pstate)
hwmgr            2683 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 			hwmgr->hwmgr_func->update_nbdpm_pstate(hwmgr,
hwmgr            2772 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
hwmgr            2880 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 	    (!is_support_sw_smu(adev) && hwmgr->od_enabled)) {
hwmgr            2945 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
hwmgr            2976 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c 	    (!is_support_sw_smu(adev) && hwmgr->od_enabled))
hwmgr              40 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr;
hwmgr              45 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	hwmgr = kzalloc(sizeof(struct pp_hwmgr), GFP_KERNEL);
hwmgr              46 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (hwmgr == NULL)
hwmgr              49 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	hwmgr->adev = adev;
hwmgr              50 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	hwmgr->not_vf = !amdgpu_sriov_vf(adev);
hwmgr              51 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	hwmgr->pm_en = (amdgpu_dpm && hwmgr->not_vf) ? true : false;
hwmgr              52 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	hwmgr->device = amdgpu_cgs_create_device(adev);
hwmgr              53 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_init(&hwmgr->smu_lock);
hwmgr              54 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	hwmgr->chip_family = adev->family;
hwmgr              55 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	hwmgr->chip_id = adev->asic_type;
hwmgr              56 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	hwmgr->feature_mask = adev->pm.pp_feature;
hwmgr              57 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	hwmgr->display_config = &adev->pm.pm_display_cfg;
hwmgr              58 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	adev->powerplay.pp_handle = hwmgr;
hwmgr              66 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
hwmgr              68 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	kfree(hwmgr->hardcode_pp_table);
hwmgr              69 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	hwmgr->hardcode_pp_table = NULL;
hwmgr              71 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	kfree(hwmgr);
hwmgr              72 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	hwmgr = NULL;
hwmgr              95 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
hwmgr              98 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	ret = hwmgr_sw_init(hwmgr);
hwmgr             108 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
hwmgr             110 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	hwmgr_sw_fini(hwmgr);
hwmgr             122 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
hwmgr             124 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	ret = hwmgr_hw_init(hwmgr);
hwmgr             135 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
hwmgr             137 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	hwmgr_hw_fini(hwmgr);
hwmgr             147 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
hwmgr             158 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (hwmgr->hwmgr_func->notify_cac_buffer_info)
hwmgr             159 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 		r = hwmgr->hwmgr_func->notify_cac_buffer_info(hwmgr,
hwmgr             176 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
hwmgr             178 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (hwmgr && hwmgr->pm_en) {
hwmgr             179 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 		mutex_lock(&hwmgr->smu_lock);
hwmgr             180 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 		hwmgr_handle_task(hwmgr,
hwmgr             182 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 		mutex_unlock(&hwmgr->smu_lock);
hwmgr             224 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
hwmgr             226 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	return hwmgr_suspend(hwmgr);
hwmgr             232 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
hwmgr             234 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	return hwmgr_resume(hwmgr);
hwmgr             277 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr             279 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->smumgr_funcs || !hwmgr->smumgr_funcs->start_smu)
hwmgr             282 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (hwmgr->smumgr_funcs->start_smu(hwmgr)) {
hwmgr             297 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr             299 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en)
hwmgr             302 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (hwmgr->hwmgr_func->update_clock_gatings == NULL) {
hwmgr             307 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	return hwmgr->hwmgr_func->update_clock_gatings(hwmgr, &msg_id);
hwmgr             310 drivers/gpu/drm/amd/powerplay/amd_powerplay.c static void pp_dpm_en_umd_pstate(struct pp_hwmgr  *hwmgr,
hwmgr             318 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!(hwmgr->dpm_level & profile_mode_mask)) {
hwmgr             321 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 			hwmgr->saved_dpm_level = hwmgr->dpm_level;
hwmgr             322 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 			hwmgr->en_umd_pstate = true;
hwmgr             323 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 			amdgpu_device_ip_set_powergating_state(hwmgr->adev,
hwmgr             326 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 			amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
hwmgr             334 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 				*level = hwmgr->saved_dpm_level;
hwmgr             335 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 			hwmgr->en_umd_pstate = false;
hwmgr             336 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 			amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
hwmgr             339 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 			amdgpu_device_ip_set_powergating_state(hwmgr->adev,
hwmgr             349 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr             351 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en)
hwmgr             354 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (level == hwmgr->dpm_level)
hwmgr             357 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_lock(&hwmgr->smu_lock);
hwmgr             358 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	pp_dpm_en_umd_pstate(hwmgr, &level);
hwmgr             359 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	hwmgr->request_dpm_level = level;
hwmgr             360 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	hwmgr_handle_task(hwmgr, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
hwmgr             361 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr             369 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr             372 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en)
hwmgr             375 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_lock(&hwmgr->smu_lock);
hwmgr             376 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	level = hwmgr->dpm_level;
hwmgr             377 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr             383 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr             386 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en)
hwmgr             389 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (hwmgr->hwmgr_func->get_sclk == NULL) {
hwmgr             393 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_lock(&hwmgr->smu_lock);
hwmgr             394 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	clk = hwmgr->hwmgr_func->get_sclk(hwmgr, low);
hwmgr             395 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr             401 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr             404 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en)
hwmgr             407 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (hwmgr->hwmgr_func->get_mclk == NULL) {
hwmgr             411 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_lock(&hwmgr->smu_lock);
hwmgr             412 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	clk = hwmgr->hwmgr_func->get_mclk(hwmgr, low);
hwmgr             413 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr             419 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr             421 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en)
hwmgr             424 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (hwmgr->hwmgr_func->powergate_vce == NULL) {
hwmgr             428 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_lock(&hwmgr->smu_lock);
hwmgr             429 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	hwmgr->hwmgr_func->powergate_vce(hwmgr, gate);
hwmgr             430 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr             435 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr             437 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en)
hwmgr             440 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (hwmgr->hwmgr_func->powergate_uvd == NULL) {
hwmgr             444 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_lock(&hwmgr->smu_lock);
hwmgr             445 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate);
hwmgr             446 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr             453 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr             455 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en)
hwmgr             458 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_lock(&hwmgr->smu_lock);
hwmgr             459 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	ret = hwmgr_handle_task(hwmgr, task_id, user_state);
hwmgr             460 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr             467 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr             471 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en || !hwmgr->current_ps)
hwmgr             474 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_lock(&hwmgr->smu_lock);
hwmgr             476 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	state = hwmgr->current_ps;
hwmgr             495 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr             502 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr             504 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en)
hwmgr             507 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (hwmgr->hwmgr_func->set_fan_control_mode == NULL) {
hwmgr             511 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_lock(&hwmgr->smu_lock);
hwmgr             512 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	hwmgr->hwmgr_func->set_fan_control_mode(hwmgr, mode);
hwmgr             513 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr             518 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr             521 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en)
hwmgr             524 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (hwmgr->hwmgr_func->get_fan_control_mode == NULL) {
hwmgr             528 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_lock(&hwmgr->smu_lock);
hwmgr             529 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mode = hwmgr->hwmgr_func->get_fan_control_mode(hwmgr);
hwmgr             530 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr             536 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr             539 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en)
hwmgr             542 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (hwmgr->hwmgr_func->set_fan_speed_percent == NULL) {
hwmgr             546 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_lock(&hwmgr->smu_lock);
hwmgr             547 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	ret = hwmgr->hwmgr_func->set_fan_speed_percent(hwmgr, percent);
hwmgr             548 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr             554 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr             557 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en)
hwmgr             560 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (hwmgr->hwmgr_func->get_fan_speed_percent == NULL) {
hwmgr             565 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_lock(&hwmgr->smu_lock);
hwmgr             566 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	ret = hwmgr->hwmgr_func->get_fan_speed_percent(hwmgr, speed);
hwmgr             567 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr             573 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr             576 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en)
hwmgr             579 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (hwmgr->hwmgr_func->get_fan_speed_rpm == NULL)
hwmgr             582 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_lock(&hwmgr->smu_lock);
hwmgr             583 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	ret = hwmgr->hwmgr_func->get_fan_speed_rpm(hwmgr, rpm);
hwmgr             584 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr             590 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr             593 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en)
hwmgr             596 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (hwmgr->hwmgr_func->set_fan_speed_rpm == NULL) {
hwmgr             600 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_lock(&hwmgr->smu_lock);
hwmgr             601 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	ret = hwmgr->hwmgr_func->set_fan_speed_rpm(hwmgr, rpm);
hwmgr             602 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr             609 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr             614 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en ||!hwmgr->ps)
hwmgr             617 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_lock(&hwmgr->smu_lock);
hwmgr             619 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	data->nums = hwmgr->num_ps;
hwmgr             621 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	for (i = 0; i < hwmgr->num_ps; i++) {
hwmgr             623 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 				((unsigned long)hwmgr->ps + i * hwmgr->ps_size);
hwmgr             641 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr             647 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr             650 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en ||!hwmgr->soft_pp_table)
hwmgr             653 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_lock(&hwmgr->smu_lock);
hwmgr             654 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	*table = (char *)hwmgr->soft_pp_table;
hwmgr             655 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	size = hwmgr->soft_pp_table_size;
hwmgr             656 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr             662 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr             665 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	ret = hwmgr_hw_fini(hwmgr);
hwmgr             669 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	ret = hwmgr_hw_init(hwmgr);
hwmgr             673 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	return hwmgr_handle_task(hwmgr, AMD_PP_TASK_COMPLETE_INIT, NULL);
hwmgr             678 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr             681 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en)
hwmgr             684 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_lock(&hwmgr->smu_lock);
hwmgr             685 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr->hardcode_pp_table) {
hwmgr             686 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 		hwmgr->hardcode_pp_table = kmemdup(hwmgr->soft_pp_table,
hwmgr             687 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 						   hwmgr->soft_pp_table_size,
hwmgr             689 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 		if (!hwmgr->hardcode_pp_table)
hwmgr             693 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	memcpy(hwmgr->hardcode_pp_table, buf, size);
hwmgr             695 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	hwmgr->soft_pp_table = hwmgr->hardcode_pp_table;
hwmgr             701 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (hwmgr->hwmgr_func->avfs_control) {
hwmgr             702 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 		ret = hwmgr->hwmgr_func->avfs_control(hwmgr, false);
hwmgr             706 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr             709 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr             716 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr             719 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en)
hwmgr             722 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (hwmgr->hwmgr_func->force_clock_level == NULL) {
hwmgr             727 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
hwmgr             732 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_lock(&hwmgr->smu_lock);
hwmgr             733 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	ret = hwmgr->hwmgr_func->force_clock_level(hwmgr, type, mask);
hwmgr             734 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr             741 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr             744 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en)
hwmgr             747 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (hwmgr->hwmgr_func->print_clock_levels == NULL) {
hwmgr             751 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_lock(&hwmgr->smu_lock);
hwmgr             752 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	ret = hwmgr->hwmgr_func->print_clock_levels(hwmgr, type, buf);
hwmgr             753 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr             759 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr             762 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en)
hwmgr             765 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (hwmgr->hwmgr_func->get_sclk_od == NULL) {
hwmgr             769 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_lock(&hwmgr->smu_lock);
hwmgr             770 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	ret = hwmgr->hwmgr_func->get_sclk_od(hwmgr);
hwmgr             771 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr             777 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr             780 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en)
hwmgr             783 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (hwmgr->hwmgr_func->set_sclk_od == NULL) {
hwmgr             788 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_lock(&hwmgr->smu_lock);
hwmgr             789 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	ret = hwmgr->hwmgr_func->set_sclk_od(hwmgr, value);
hwmgr             790 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr             796 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr             799 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en)
hwmgr             802 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (hwmgr->hwmgr_func->get_mclk_od == NULL) {
hwmgr             806 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_lock(&hwmgr->smu_lock);
hwmgr             807 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	ret = hwmgr->hwmgr_func->get_mclk_od(hwmgr);
hwmgr             808 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr             814 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr             817 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en)
hwmgr             820 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (hwmgr->hwmgr_func->set_mclk_od == NULL) {
hwmgr             824 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_lock(&hwmgr->smu_lock);
hwmgr             825 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	ret = hwmgr->hwmgr_func->set_mclk_od(hwmgr, value);
hwmgr             826 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr             833 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr             836 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en || !value)
hwmgr             841 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 		*((uint32_t *)value) = hwmgr->pstate_sclk;
hwmgr             844 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 		*((uint32_t *)value) = hwmgr->pstate_mclk;
hwmgr             847 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 		*((uint32_t *)value) = hwmgr->thermal_controller.fanInfo.ulMinRPM;
hwmgr             850 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 		*((uint32_t *)value) = hwmgr->thermal_controller.fanInfo.ulMaxRPM;
hwmgr             853 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 		mutex_lock(&hwmgr->smu_lock);
hwmgr             854 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 		ret = hwmgr->hwmgr_func->read_sensor(hwmgr, idx, value, size);
hwmgr             855 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 		mutex_unlock(&hwmgr->smu_lock);
hwmgr             863 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr             865 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en)
hwmgr             868 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (idx < hwmgr->num_vce_state_tables)
hwmgr             869 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 		return &hwmgr->vce_states[idx];
hwmgr             875 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr             877 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en || !buf)
hwmgr             880 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (hwmgr->hwmgr_func->get_power_profile_mode == NULL) {
hwmgr             885 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	return hwmgr->hwmgr_func->get_power_profile_mode(hwmgr, buf);
hwmgr             890 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr             893 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en)
hwmgr             896 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) {
hwmgr             901 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
hwmgr             906 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_lock(&hwmgr->smu_lock);
hwmgr             907 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	ret = hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, input, size);
hwmgr             908 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr             914 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr             916 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en)
hwmgr             919 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (hwmgr->hwmgr_func->odn_edit_dpm_table == NULL) {
hwmgr             924 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	return hwmgr->hwmgr_func->odn_edit_dpm_table(hwmgr, type, input, size);
hwmgr             929 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr             931 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en)
hwmgr             934 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (hwmgr->hwmgr_func->set_mp1_state)
hwmgr             935 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 		return hwmgr->hwmgr_func->set_mp1_state(hwmgr, mp1_state);
hwmgr             943 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr             947 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en)
hwmgr             950 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (hwmgr->hwmgr_func->set_power_profile_mode == NULL) {
hwmgr             958 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_lock(&hwmgr->smu_lock);
hwmgr             961 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 		hwmgr->workload_mask &= ~(1 << hwmgr->workload_prority[type]);
hwmgr             962 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 		index = fls(hwmgr->workload_mask);
hwmgr             964 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 		workload = hwmgr->workload_setting[index];
hwmgr             966 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 		hwmgr->workload_mask |= (1 << hwmgr->workload_prority[type]);
hwmgr             967 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 		index = fls(hwmgr->workload_mask);
hwmgr             969 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 		workload = hwmgr->workload_setting[index];
hwmgr             972 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
hwmgr             973 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 		hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, &workload, 0);
hwmgr             974 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr             981 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr             984 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en)
hwmgr             987 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (hwmgr->hwmgr_func->set_power_limit == NULL) {
hwmgr             993 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 		limit = hwmgr->default_power_limit;
hwmgr             995 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	max_power_limit = hwmgr->default_power_limit;
hwmgr             996 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (hwmgr->od_enabled) {
hwmgr             997 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 		max_power_limit *= (100 + hwmgr->platform_descriptor.TDPODLimit);
hwmgr            1004 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_lock(&hwmgr->smu_lock);
hwmgr            1005 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	hwmgr->hwmgr_func->set_power_limit(hwmgr, limit);
hwmgr            1006 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	hwmgr->power_limit = limit;
hwmgr            1007 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr            1013 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr            1015 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en ||!limit)
hwmgr            1018 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_lock(&hwmgr->smu_lock);
hwmgr            1021 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 		*limit = hwmgr->default_power_limit;
hwmgr            1022 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 		if (hwmgr->od_enabled) {
hwmgr            1023 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 			*limit *= (100 + hwmgr->platform_descriptor.TDPODLimit);
hwmgr            1028 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 		*limit = hwmgr->power_limit;
hwmgr            1030 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr            1038 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr            1040 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en)
hwmgr            1043 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_lock(&hwmgr->smu_lock);
hwmgr            1044 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	phm_store_dal_configuration_data(hwmgr, display_config);
hwmgr            1045 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr            1052 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr            1055 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en ||!output)
hwmgr            1058 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_lock(&hwmgr->smu_lock);
hwmgr            1059 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	ret = phm_get_dal_power_level(hwmgr, output);
hwmgr            1060 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr            1069 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr            1072 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en)
hwmgr            1075 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_lock(&hwmgr->smu_lock);
hwmgr            1077 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	phm_get_dal_power_level(hwmgr, &simple_clocks);
hwmgr            1079 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            1081 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 		ret = phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware,
hwmgr            1084 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 		ret = phm_get_clock_info(hwmgr, &hwmgr->current_ps->hardware,
hwmgr            1089 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 		mutex_unlock(&hwmgr->smu_lock);
hwmgr            1108 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (0 == phm_get_current_shallow_sleep_clocks(hwmgr, &hwmgr->current_ps->hardware, &hw_clocks)) {
hwmgr            1112 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr            1118 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr            1121 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en)
hwmgr            1127 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_lock(&hwmgr->smu_lock);
hwmgr            1128 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	ret = phm_get_clock_by_type(hwmgr, type, clocks);
hwmgr            1129 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr            1137 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr            1140 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en ||!clocks)
hwmgr            1143 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_lock(&hwmgr->smu_lock);
hwmgr            1144 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	ret = phm_get_clock_by_type_with_latency(hwmgr, type, clocks);
hwmgr            1145 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr            1153 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr            1156 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en ||!clocks)
hwmgr            1159 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_lock(&hwmgr->smu_lock);
hwmgr            1161 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	ret = phm_get_clock_by_type_with_voltage(hwmgr, type, clocks);
hwmgr            1163 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr            1170 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr            1173 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en || !clock_ranges)
hwmgr            1176 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_lock(&hwmgr->smu_lock);
hwmgr            1177 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	ret = phm_set_watermarks_for_clocks_ranges(hwmgr,
hwmgr            1179 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr            1187 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr            1190 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en ||!clock)
hwmgr            1193 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_lock(&hwmgr->smu_lock);
hwmgr            1194 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	ret = phm_display_clock_voltage_request(hwmgr, clock);
hwmgr            1195 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr            1203 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr            1206 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en ||!clocks)
hwmgr            1211 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_lock(&hwmgr->smu_lock);
hwmgr            1213 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DynamicPatchPowerState))
hwmgr            1214 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 		ret = phm_get_max_high_clocks(hwmgr, clocks);
hwmgr            1216 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr            1222 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr            1224 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en)
hwmgr            1227 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (hwmgr->hwmgr_func->powergate_mmhub == NULL) {
hwmgr            1232 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	return hwmgr->hwmgr_func->powergate_mmhub(hwmgr);
hwmgr            1237 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr            1239 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en)
hwmgr            1242 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (hwmgr->hwmgr_func->powergate_gfx == NULL) {
hwmgr            1247 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	return hwmgr->hwmgr_func->powergate_gfx(hwmgr, gate);
hwmgr            1252 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr            1254 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en)
hwmgr            1257 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (hwmgr->hwmgr_func->powergate_acp == NULL) {
hwmgr            1262 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	hwmgr->hwmgr_func->powergate_acp(hwmgr, gate);
hwmgr            1267 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr            1269 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr)
hwmgr            1272 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (hwmgr->hwmgr_func->powergate_sdma == NULL) {
hwmgr            1277 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	hwmgr->hwmgr_func->powergate_sdma(hwmgr, gate);
hwmgr            1313 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr            1315 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en)
hwmgr            1318 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (hwmgr->hwmgr_func->smus_notify_pwe == NULL) {
hwmgr            1323 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_lock(&hwmgr->smu_lock);
hwmgr            1324 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	hwmgr->hwmgr_func->smus_notify_pwe(hwmgr);
hwmgr            1325 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr            1332 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr            1334 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr)
hwmgr            1337 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr->pm_en ||
hwmgr            1338 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	     hwmgr->hwmgr_func->enable_mgpu_fan_boost == NULL)
hwmgr            1341 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_lock(&hwmgr->smu_lock);
hwmgr            1342 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	hwmgr->hwmgr_func->enable_mgpu_fan_boost(hwmgr);
hwmgr            1343 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr            1350 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr            1352 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en)
hwmgr            1355 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk == NULL) {
hwmgr            1360 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_lock(&hwmgr->smu_lock);
hwmgr            1361 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk(hwmgr, clock);
hwmgr            1362 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr            1369 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr            1371 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en)
hwmgr            1374 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (hwmgr->hwmgr_func->set_hard_min_dcefclk_by_freq == NULL) {
hwmgr            1379 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_lock(&hwmgr->smu_lock);
hwmgr            1380 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	hwmgr->hwmgr_func->set_hard_min_dcefclk_by_freq(hwmgr, clock);
hwmgr            1381 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr            1388 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr            1390 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en)
hwmgr            1393 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (hwmgr->hwmgr_func->set_hard_min_fclk_by_freq == NULL) {
hwmgr            1398 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_lock(&hwmgr->smu_lock);
hwmgr            1399 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	hwmgr->hwmgr_func->set_hard_min_fclk_by_freq(hwmgr, clock);
hwmgr            1400 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr            1407 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr            1410 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en)
hwmgr            1413 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_lock(&hwmgr->smu_lock);
hwmgr            1414 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	ret = phm_set_active_display_count(hwmgr, count);
hwmgr            1415 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr            1422 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr            1425 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr)
hwmgr            1428 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!(hwmgr->not_vf && amdgpu_dpm) ||
hwmgr            1429 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 		!hwmgr->hwmgr_func->get_asic_baco_capability)
hwmgr            1432 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_lock(&hwmgr->smu_lock);
hwmgr            1433 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	hwmgr->hwmgr_func->get_asic_baco_capability(hwmgr, cap);
hwmgr            1434 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr            1441 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr            1443 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr)
hwmgr            1446 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr->pm_en || !hwmgr->hwmgr_func->get_asic_baco_state)
hwmgr            1449 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_lock(&hwmgr->smu_lock);
hwmgr            1450 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	hwmgr->hwmgr_func->get_asic_baco_state(hwmgr, (enum BACO_STATE *)state);
hwmgr            1451 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr            1458 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr            1460 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr)
hwmgr            1463 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!(hwmgr->not_vf && amdgpu_dpm) ||
hwmgr            1464 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 		!hwmgr->hwmgr_func->set_asic_baco_state)
hwmgr            1467 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_lock(&hwmgr->smu_lock);
hwmgr            1468 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	hwmgr->hwmgr_func->set_asic_baco_state(hwmgr, (enum BACO_STATE)state);
hwmgr            1469 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr            1476 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr            1479 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en || !buf)
hwmgr            1482 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (hwmgr->hwmgr_func->get_ppfeature_status == NULL) {
hwmgr            1487 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_lock(&hwmgr->smu_lock);
hwmgr            1488 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	ret = hwmgr->hwmgr_func->get_ppfeature_status(hwmgr, buf);
hwmgr            1489 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr            1496 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr            1499 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en)
hwmgr            1502 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (hwmgr->hwmgr_func->set_ppfeature_status == NULL) {
hwmgr            1507 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_lock(&hwmgr->smu_lock);
hwmgr            1508 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	ret = hwmgr->hwmgr_func->set_ppfeature_status(hwmgr, ppfeature_masks);
hwmgr            1509 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr            1516 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr            1519 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en)
hwmgr            1522 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (hwmgr->hwmgr_func->asic_reset == NULL) {
hwmgr            1527 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_lock(&hwmgr->smu_lock);
hwmgr            1528 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	ret = hwmgr->hwmgr_func->asic_reset(hwmgr, SMU_ASIC_RESET_MODE_2);
hwmgr            1529 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr            1536 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	struct pp_hwmgr *hwmgr = handle;
hwmgr            1539 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (!hwmgr || !hwmgr->pm_en)
hwmgr            1542 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	if (hwmgr->hwmgr_func->smu_i2c_bus_access == NULL) {
hwmgr            1547 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_lock(&hwmgr->smu_lock);
hwmgr            1548 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	ret = hwmgr->hwmgr_func->smu_i2c_bus_access(hwmgr, acquire);
hwmgr            1549 drivers/gpu/drm/amd/powerplay/amd_powerplay.c 	mutex_unlock(&hwmgr->smu_lock);
hwmgr              27 drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c static bool baco_wait_register(struct pp_hwmgr *hwmgr, u32 reg, u32 mask, u32 value)
hwmgr              29 drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c 	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
hwmgr              44 drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c static bool baco_cmd_handler(struct pp_hwmgr *hwmgr, u32 command, u32 reg, u32 mask,
hwmgr              47 drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c 	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
hwmgr              61 drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c 		ret = baco_wait_register(hwmgr, reg, mask, value);
hwmgr              82 drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c bool soc15_baco_program_registers(struct pp_hwmgr *hwmgr,
hwmgr              86 drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c 	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
hwmgr              95 drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.c 		if (!baco_cmd_handler(hwmgr, entry[i].cmd, reg, entry[i].mask,
hwmgr              47 drivers/gpu/drm/amd/powerplay/hwmgr/common_baco.h extern bool soc15_baco_program_registers(struct pp_hwmgr *hwmgr,
hwmgr              39 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c int phm_setup_asic(struct pp_hwmgr *hwmgr)
hwmgr              41 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	PHM_FUNC_CHECK(hwmgr);
hwmgr              43 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	if (NULL != hwmgr->hwmgr_func->asic_setup)
hwmgr              44 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 		return hwmgr->hwmgr_func->asic_setup(hwmgr);
hwmgr              49 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c int phm_power_down_asic(struct pp_hwmgr *hwmgr)
hwmgr              51 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	PHM_FUNC_CHECK(hwmgr);
hwmgr              53 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	if (NULL != hwmgr->hwmgr_func->power_off_asic)
hwmgr              54 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 		return hwmgr->hwmgr_func->power_off_asic(hwmgr);
hwmgr              59 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c int phm_set_power_state(struct pp_hwmgr *hwmgr,
hwmgr              65 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	PHM_FUNC_CHECK(hwmgr);
hwmgr              70 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	if (NULL != hwmgr->hwmgr_func->power_state_set)
hwmgr              71 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 		return hwmgr->hwmgr_func->power_state_set(hwmgr, &states);
hwmgr              76 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr)
hwmgr              80 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	PHM_FUNC_CHECK(hwmgr);
hwmgr              81 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	adev = hwmgr->adev;
hwmgr              84 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	if (smum_is_dpm_running(hwmgr) && !amdgpu_passthrough(adev)
hwmgr              90 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable)
hwmgr              91 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 		ret = hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr);
hwmgr              96 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c int phm_disable_dynamic_state_management(struct pp_hwmgr *hwmgr)
hwmgr             100 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	PHM_FUNC_CHECK(hwmgr);
hwmgr             102 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	if (!smum_is_dpm_running(hwmgr)) {
hwmgr             107 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	if (hwmgr->hwmgr_func->dynamic_state_management_disable)
hwmgr             108 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 		ret = hwmgr->hwmgr_func->dynamic_state_management_disable(hwmgr);
hwmgr             113 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level)
hwmgr             117 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	PHM_FUNC_CHECK(hwmgr);
hwmgr             119 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	if (hwmgr->hwmgr_func->force_dpm_level != NULL)
hwmgr             120 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 		ret = hwmgr->hwmgr_func->force_dpm_level(hwmgr, level);
hwmgr             125 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
hwmgr             129 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	PHM_FUNC_CHECK(hwmgr);
hwmgr             131 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	if (hwmgr->hwmgr_func->apply_state_adjust_rules != NULL)
hwmgr             132 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 		return hwmgr->hwmgr_func->apply_state_adjust_rules(
hwmgr             133 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 									hwmgr,
hwmgr             139 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c int phm_apply_clock_adjust_rules(struct pp_hwmgr *hwmgr)
hwmgr             141 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	PHM_FUNC_CHECK(hwmgr);
hwmgr             143 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	if (hwmgr->hwmgr_func->apply_clocks_adjust_rules != NULL)
hwmgr             144 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 		return hwmgr->hwmgr_func->apply_clocks_adjust_rules(hwmgr);
hwmgr             148 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c int phm_powerdown_uvd(struct pp_hwmgr *hwmgr)
hwmgr             150 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	PHM_FUNC_CHECK(hwmgr);
hwmgr             152 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	if (hwmgr->hwmgr_func->powerdown_uvd != NULL)
hwmgr             153 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 		return hwmgr->hwmgr_func->powerdown_uvd(hwmgr);
hwmgr             158 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c int phm_disable_clock_power_gatings(struct pp_hwmgr *hwmgr)
hwmgr             160 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	PHM_FUNC_CHECK(hwmgr);
hwmgr             162 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	if (NULL != hwmgr->hwmgr_func->disable_clock_power_gating)
hwmgr             163 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 		return hwmgr->hwmgr_func->disable_clock_power_gating(hwmgr);
hwmgr             168 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c int phm_pre_display_configuration_changed(struct pp_hwmgr *hwmgr)
hwmgr             170 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	PHM_FUNC_CHECK(hwmgr);
hwmgr             172 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	if (NULL != hwmgr->hwmgr_func->pre_display_config_changed)
hwmgr             173 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 		hwmgr->hwmgr_func->pre_display_config_changed(hwmgr);
hwmgr             179 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c int phm_display_configuration_changed(struct pp_hwmgr *hwmgr)
hwmgr             181 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	PHM_FUNC_CHECK(hwmgr);
hwmgr             183 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	if (NULL != hwmgr->hwmgr_func->display_config_changed)
hwmgr             184 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 		hwmgr->hwmgr_func->display_config_changed(hwmgr);
hwmgr             189 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
hwmgr             191 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	PHM_FUNC_CHECK(hwmgr);
hwmgr             193 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	if (NULL != hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment)
hwmgr             194 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 			hwmgr->hwmgr_func->notify_smc_display_config_after_ps_adjustment(hwmgr);
hwmgr             199 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr)
hwmgr             201 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	PHM_FUNC_CHECK(hwmgr);
hwmgr             203 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	if (hwmgr->hwmgr_func->stop_thermal_controller == NULL)
hwmgr             206 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	return hwmgr->hwmgr_func->stop_thermal_controller(hwmgr);
hwmgr             209 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c int phm_register_irq_handlers(struct pp_hwmgr *hwmgr)
hwmgr             211 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	PHM_FUNC_CHECK(hwmgr);
hwmgr             213 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	if (hwmgr->hwmgr_func->register_irq_handlers != NULL)
hwmgr             214 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 		return hwmgr->hwmgr_func->register_irq_handlers(hwmgr);
hwmgr             225 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c int phm_start_thermal_controller(struct pp_hwmgr *hwmgr)
hwmgr             238 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             240 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	if (hwmgr->hwmgr_func->get_thermal_temperature_range)
hwmgr             241 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 		hwmgr->hwmgr_func->get_thermal_temperature_range(
hwmgr             242 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 				hwmgr, &range);
hwmgr             244 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr             246 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 			&& hwmgr->hwmgr_func->start_thermal_controller != NULL)
hwmgr             247 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 		ret = hwmgr->hwmgr_func->start_thermal_controller(hwmgr, &range);
hwmgr             263 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c bool phm_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
hwmgr             265 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	PHM_FUNC_CHECK(hwmgr);
hwmgr             267 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	if (hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration == NULL)
hwmgr             270 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	return hwmgr->hwmgr_func->check_smc_update_required_for_display_configuration(hwmgr);
hwmgr             274 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c int phm_check_states_equal(struct pp_hwmgr *hwmgr,
hwmgr             279 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	PHM_FUNC_CHECK(hwmgr);
hwmgr             281 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	if (hwmgr->hwmgr_func->check_states_equal == NULL)
hwmgr             284 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	return hwmgr->hwmgr_func->check_states_equal(hwmgr, pstate1, pstate2, equal);
hwmgr             287 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
hwmgr             293 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	PHM_FUNC_CHECK(hwmgr);
hwmgr             298 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	if (NULL != hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk)
hwmgr             299 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 		hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk(hwmgr, display_config->min_dcef_deep_sleep_set_clk);
hwmgr             306 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	if (NULL != hwmgr->hwmgr_func->set_active_display_count)
hwmgr             307 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 		hwmgr->hwmgr_func->set_active_display_count(hwmgr, number_of_active_display);
hwmgr             309 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	if (hwmgr->hwmgr_func->store_cc6_data == NULL)
hwmgr             314 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	if (hwmgr->hwmgr_func->store_cc6_data)
hwmgr             315 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 		hwmgr->hwmgr_func->store_cc6_data(hwmgr,
hwmgr             324 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c int phm_get_dal_power_level(struct pp_hwmgr *hwmgr,
hwmgr             327 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	PHM_FUNC_CHECK(hwmgr);
hwmgr             329 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	if (info == NULL || hwmgr->hwmgr_func->get_dal_power_level == NULL)
hwmgr             331 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	return hwmgr->hwmgr_func->get_dal_power_level(hwmgr, info);
hwmgr             334 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr)
hwmgr             336 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	PHM_FUNC_CHECK(hwmgr);
hwmgr             338 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	if (hwmgr->hwmgr_func->set_cpu_power_state != NULL)
hwmgr             339 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 		return hwmgr->hwmgr_func->set_cpu_power_state(hwmgr);
hwmgr             345 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c int phm_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
hwmgr             349 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	PHM_FUNC_CHECK(hwmgr);
hwmgr             350 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	if (hwmgr->hwmgr_func->get_performance_level == NULL)
hwmgr             353 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	return hwmgr->hwmgr_func->get_performance_level(hwmgr, state, designation, index, level);
hwmgr             367 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c int phm_get_clock_info(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, struct pp_clock_info *pclock_info,
hwmgr             373 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	PHM_FUNC_CHECK(hwmgr);
hwmgr             378 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	result = phm_get_performance_level(hwmgr, state, PHM_PerformanceLevelDesignation_Activity, 0, &performance_level);
hwmgr             388 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	result = phm_get_performance_level(hwmgr, state, designation,
hwmgr             389 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 					(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1), &performance_level);
hwmgr             400 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c int phm_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, struct pp_clock_info *clock_info)
hwmgr             402 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	PHM_FUNC_CHECK(hwmgr);
hwmgr             404 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	if (hwmgr->hwmgr_func->get_current_shallow_sleep_clocks == NULL)
hwmgr             407 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	return hwmgr->hwmgr_func->get_current_shallow_sleep_clocks(hwmgr, state, clock_info);
hwmgr             411 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c int phm_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks)
hwmgr             413 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	PHM_FUNC_CHECK(hwmgr);
hwmgr             415 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	if (hwmgr->hwmgr_func->get_clock_by_type == NULL)
hwmgr             418 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	return hwmgr->hwmgr_func->get_clock_by_type(hwmgr, type, clocks);
hwmgr             422 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c int phm_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
hwmgr             426 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	PHM_FUNC_CHECK(hwmgr);
hwmgr             428 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	if (hwmgr->hwmgr_func->get_clock_by_type_with_latency == NULL)
hwmgr             431 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	return hwmgr->hwmgr_func->get_clock_by_type_with_latency(hwmgr, type, clocks);
hwmgr             435 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c int phm_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
hwmgr             439 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	PHM_FUNC_CHECK(hwmgr);
hwmgr             441 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	if (hwmgr->hwmgr_func->get_clock_by_type_with_voltage == NULL)
hwmgr             444 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	return hwmgr->hwmgr_func->get_clock_by_type_with_voltage(hwmgr, type, clocks);
hwmgr             448 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c int phm_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
hwmgr             451 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	PHM_FUNC_CHECK(hwmgr);
hwmgr             453 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	if (!hwmgr->hwmgr_func->set_watermarks_for_clocks_ranges)
hwmgr             456 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	return hwmgr->hwmgr_func->set_watermarks_for_clocks_ranges(hwmgr,
hwmgr             460 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c int phm_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
hwmgr             463 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	PHM_FUNC_CHECK(hwmgr);
hwmgr             465 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	if (!hwmgr->hwmgr_func->display_clock_voltage_request)
hwmgr             468 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	return hwmgr->hwmgr_func->display_clock_voltage_request(hwmgr, clock);
hwmgr             471 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c int phm_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)
hwmgr             473 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	PHM_FUNC_CHECK(hwmgr);
hwmgr             475 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	if (hwmgr->hwmgr_func->get_max_high_clocks == NULL)
hwmgr             478 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	return hwmgr->hwmgr_func->get_max_high_clocks(hwmgr, clocks);
hwmgr             481 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c int phm_disable_smc_firmware_ctf(struct pp_hwmgr *hwmgr)
hwmgr             483 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	PHM_FUNC_CHECK(hwmgr);
hwmgr             485 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	if (hwmgr->hwmgr_func->disable_smc_firmware_ctf == NULL)
hwmgr             488 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	return hwmgr->hwmgr_func->disable_smc_firmware_ctf(hwmgr);
hwmgr             491 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c int phm_set_active_display_count(struct pp_hwmgr *hwmgr, uint32_t count)
hwmgr             493 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	PHM_FUNC_CHECK(hwmgr);
hwmgr             495 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	if (!hwmgr->hwmgr_func->set_active_display_count)
hwmgr             498 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	return hwmgr->hwmgr_func->set_active_display_count(hwmgr, count);
hwmgr             501 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c int phm_set_min_deep_sleep_dcefclk(struct pp_hwmgr *hwmgr, uint32_t clock)
hwmgr             503 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	PHM_FUNC_CHECK(hwmgr);
hwmgr             505 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	if (!hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk)
hwmgr             508 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	return hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk(hwmgr, clock);
hwmgr             511 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c int phm_set_hard_min_dcefclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock)
hwmgr             513 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	PHM_FUNC_CHECK(hwmgr);
hwmgr             515 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	if (!hwmgr->hwmgr_func->set_hard_min_dcefclk_by_freq)
hwmgr             518 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	return hwmgr->hwmgr_func->set_hard_min_dcefclk_by_freq(hwmgr, clock);
hwmgr             521 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c int phm_set_hard_min_fclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock)
hwmgr             523 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	PHM_FUNC_CHECK(hwmgr);
hwmgr             525 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	if (!hwmgr->hwmgr_func->set_hard_min_fclk_by_freq)
hwmgr             528 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 	return hwmgr->hwmgr_func->set_hard_min_fclk_by_freq(hwmgr, clock);
hwmgr              49 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c extern int smu7_init_function_pointers(struct pp_hwmgr *hwmgr);
hwmgr              50 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c extern int smu8_init_function_pointers(struct pp_hwmgr *hwmgr);
hwmgr              51 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c extern int vega10_hwmgr_init(struct pp_hwmgr *hwmgr);
hwmgr              52 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c extern int vega12_hwmgr_init(struct pp_hwmgr *hwmgr);
hwmgr              53 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c extern int vega20_hwmgr_init(struct pp_hwmgr *hwmgr);
hwmgr              54 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c extern int smu10_init_function_pointers(struct pp_hwmgr *hwmgr);
hwmgr              56 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c static int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr);
hwmgr              57 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c static void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr);
hwmgr              58 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c static int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr);
hwmgr              59 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c static int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr);
hwmgr              60 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c static int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr);
hwmgr              61 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c static int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr);
hwmgr              62 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c static int ci_set_asic_special_caps(struct pp_hwmgr *hwmgr);
hwmgr              65 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c static void hwmgr_init_workload_prority(struct pp_hwmgr *hwmgr)
hwmgr              67 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	hwmgr->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
hwmgr              68 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	hwmgr->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
hwmgr              69 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	hwmgr->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
hwmgr              70 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
hwmgr              71 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	hwmgr->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
hwmgr              72 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	hwmgr->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
hwmgr              74 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	hwmgr->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
hwmgr              75 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	hwmgr->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
hwmgr              76 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	hwmgr->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
hwmgr              77 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	hwmgr->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
hwmgr              78 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	hwmgr->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
hwmgr              79 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	hwmgr->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
hwmgr              82 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c int hwmgr_early_init(struct pp_hwmgr *hwmgr)
hwmgr              84 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	if (!hwmgr)
hwmgr              87 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	hwmgr->usec_timeout = AMD_MAX_USEC_TIMEOUT;
hwmgr              88 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	hwmgr->pp_table_version = PP_TABLE_V1;
hwmgr              89 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	hwmgr->dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
hwmgr              90 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	hwmgr->request_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
hwmgr              91 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	hwmgr_init_default_caps(hwmgr);
hwmgr              92 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	hwmgr_set_user_specify_caps(hwmgr);
hwmgr              93 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	hwmgr->fan_ctrl_is_in_default_mode = true;
hwmgr              94 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	hwmgr_init_workload_prority(hwmgr);
hwmgr              95 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	hwmgr->gfxoff_state_changed_by_workload = false;
hwmgr              97 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	switch (hwmgr->chip_family) {
hwmgr              99 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 		hwmgr->smumgr_funcs = &ci_smu_funcs;
hwmgr             100 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 		ci_set_asic_special_caps(hwmgr);
hwmgr             101 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 		hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK |
hwmgr             104 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 		hwmgr->pp_table_version = PP_TABLE_V0;
hwmgr             105 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 		hwmgr->od_enabled = false;
hwmgr             106 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 		smu7_init_function_pointers(hwmgr);
hwmgr             109 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 		hwmgr->od_enabled = false;
hwmgr             110 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 		hwmgr->smumgr_funcs = &smu8_smu_funcs;
hwmgr             111 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 		hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
hwmgr             112 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 		smu8_init_function_pointers(hwmgr);
hwmgr             115 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 		hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
hwmgr             116 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 		switch (hwmgr->chip_id) {
hwmgr             118 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 			hwmgr->smumgr_funcs = &iceland_smu_funcs;
hwmgr             119 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 			topaz_set_asic_special_caps(hwmgr);
hwmgr             120 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 			hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK |
hwmgr             122 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 			hwmgr->pp_table_version = PP_TABLE_V0;
hwmgr             123 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 			hwmgr->od_enabled = false;
hwmgr             126 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 			hwmgr->smumgr_funcs = &tonga_smu_funcs;
hwmgr             127 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 			tonga_set_asic_special_caps(hwmgr);
hwmgr             128 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 			hwmgr->feature_mask &= ~PP_VBI_TIME_SUPPORT_MASK;
hwmgr             131 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 			hwmgr->smumgr_funcs = &fiji_smu_funcs;
hwmgr             132 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 			fiji_set_asic_special_caps(hwmgr);
hwmgr             133 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 			hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK |
hwmgr             139 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 			hwmgr->smumgr_funcs = &polaris10_smu_funcs;
hwmgr             140 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 			polaris_set_asic_special_caps(hwmgr);
hwmgr             141 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 			hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK);
hwmgr             144 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 			hwmgr->smumgr_funcs = &vegam_smu_funcs;
hwmgr             145 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 			polaris_set_asic_special_caps(hwmgr);
hwmgr             146 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 			hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK);
hwmgr             151 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 		smu7_init_function_pointers(hwmgr);
hwmgr             154 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 		switch (hwmgr->chip_id) {
hwmgr             156 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 			hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
hwmgr             157 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 			hwmgr->smumgr_funcs = &vega10_smu_funcs;
hwmgr             158 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 			vega10_hwmgr_init(hwmgr);
hwmgr             161 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 			hwmgr->smumgr_funcs = &vega12_smu_funcs;
hwmgr             162 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 			vega12_hwmgr_init(hwmgr);
hwmgr             165 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 			hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
hwmgr             166 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 			hwmgr->smumgr_funcs = &vega20_smu_funcs;
hwmgr             167 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 			vega20_hwmgr_init(hwmgr);
hwmgr             174 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 		switch (hwmgr->chip_id) {
hwmgr             176 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 			hwmgr->od_enabled = false;
hwmgr             177 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 			hwmgr->smumgr_funcs = &smu10_smu_funcs;
hwmgr             178 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 			smu10_init_function_pointers(hwmgr);
hwmgr             191 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c int hwmgr_sw_init(struct pp_hwmgr *hwmgr)
hwmgr             193 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	if (!hwmgr|| !hwmgr->smumgr_funcs || !hwmgr->smumgr_funcs->smu_init)
hwmgr             196 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	phm_register_irq_handlers(hwmgr);
hwmgr             197 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	pr_info("hwmgr_sw_init smu backed is %s\n", hwmgr->smumgr_funcs->name);
hwmgr             199 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	return hwmgr->smumgr_funcs->smu_init(hwmgr);
hwmgr             203 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c int hwmgr_sw_fini(struct pp_hwmgr *hwmgr)
hwmgr             205 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	if (hwmgr && hwmgr->smumgr_funcs && hwmgr->smumgr_funcs->smu_fini)
hwmgr             206 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 		hwmgr->smumgr_funcs->smu_fini(hwmgr);
hwmgr             211 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c int hwmgr_hw_init(struct pp_hwmgr *hwmgr)
hwmgr             215 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	if (!hwmgr->pm_en)
hwmgr             218 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	if (!hwmgr->pptable_func ||
hwmgr             219 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	    !hwmgr->pptable_func->pptable_init ||
hwmgr             220 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	    !hwmgr->hwmgr_func->backend_init) {
hwmgr             221 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 		hwmgr->pm_en = false;
hwmgr             226 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	ret = hwmgr->pptable_func->pptable_init(hwmgr);
hwmgr             230 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	((struct amdgpu_device *)hwmgr->adev)->pm.no_fan =
hwmgr             231 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 				hwmgr->thermal_controller.fanInfo.bNoFan;
hwmgr             233 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	ret = hwmgr->hwmgr_func->backend_init(hwmgr);
hwmgr             237 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	if ((hwmgr->dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
hwmgr             238 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 			(hwmgr->dyn_state.max_clock_voltage_on_dc.mclk == 0))
hwmgr             239 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 			hwmgr->dyn_state.max_clock_voltage_on_dc =
hwmgr             240 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 					hwmgr->dyn_state.max_clock_voltage_on_ac;
hwmgr             242 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	ret = psm_init_power_state_table(hwmgr);
hwmgr             246 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	ret = phm_setup_asic(hwmgr);
hwmgr             250 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	ret = phm_enable_dynamic_state_management(hwmgr);
hwmgr             253 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	ret = phm_start_thermal_controller(hwmgr);
hwmgr             254 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	ret |= psm_set_performance_states(hwmgr);
hwmgr             258 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	((struct amdgpu_device *)hwmgr->adev)->pm.dpm_enabled = true;
hwmgr             262 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	if (hwmgr->hwmgr_func->backend_fini)
hwmgr             263 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 		hwmgr->hwmgr_func->backend_fini(hwmgr);
hwmgr             265 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	if (hwmgr->pptable_func->pptable_fini)
hwmgr             266 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 		hwmgr->pptable_func->pptable_fini(hwmgr);
hwmgr             271 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c int hwmgr_hw_fini(struct pp_hwmgr *hwmgr)
hwmgr             273 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	if (!hwmgr || !hwmgr->pm_en)
hwmgr             276 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	phm_stop_thermal_controller(hwmgr);
hwmgr             277 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	psm_set_boot_states(hwmgr);
hwmgr             278 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	psm_adjust_power_state_dynamic(hwmgr, true, NULL);
hwmgr             279 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	phm_disable_dynamic_state_management(hwmgr);
hwmgr             280 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	phm_disable_clock_power_gatings(hwmgr);
hwmgr             282 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	if (hwmgr->hwmgr_func->backend_fini)
hwmgr             283 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 		hwmgr->hwmgr_func->backend_fini(hwmgr);
hwmgr             284 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	if (hwmgr->pptable_func->pptable_fini)
hwmgr             285 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 		hwmgr->pptable_func->pptable_fini(hwmgr);
hwmgr             286 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	return psm_fini_power_state_table(hwmgr);
hwmgr             289 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c int hwmgr_suspend(struct pp_hwmgr *hwmgr)
hwmgr             293 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	if (!hwmgr || !hwmgr->pm_en)
hwmgr             296 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	phm_disable_smc_firmware_ctf(hwmgr);
hwmgr             297 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	ret = psm_set_boot_states(hwmgr);
hwmgr             300 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	ret = psm_adjust_power_state_dynamic(hwmgr, true, NULL);
hwmgr             303 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	ret = phm_power_down_asic(hwmgr);
hwmgr             308 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c int hwmgr_resume(struct pp_hwmgr *hwmgr)
hwmgr             312 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	if (!hwmgr)
hwmgr             315 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	if (!hwmgr->pm_en)
hwmgr             318 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	ret = phm_setup_asic(hwmgr);
hwmgr             322 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	ret = phm_enable_dynamic_state_management(hwmgr);
hwmgr             325 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	ret = phm_start_thermal_controller(hwmgr);
hwmgr             326 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	ret |= psm_set_performance_states(hwmgr);
hwmgr             330 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
hwmgr             349 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c int hwmgr_handle_task(struct pp_hwmgr *hwmgr, enum amd_pp_task task_id,
hwmgr             354 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	if (hwmgr == NULL)
hwmgr             359 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 		ret = phm_pre_display_configuration_changed(hwmgr);
hwmgr             362 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 		ret = phm_set_cpu_power_state(hwmgr);
hwmgr             365 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 		ret = psm_set_performance_states(hwmgr);
hwmgr             368 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 		ret = psm_adjust_power_state_dynamic(hwmgr, false, NULL);
hwmgr             381 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 		ret = psm_set_user_performance_state(hwmgr, requested_ui_label, &requested_ps);
hwmgr             384 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 		ret = psm_adjust_power_state_dynamic(hwmgr, true, requested_ps);
hwmgr             389 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 		ret = psm_adjust_power_state_dynamic(hwmgr, true, NULL);
hwmgr             397 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c void hwmgr_init_default_caps(struct pp_hwmgr *hwmgr)
hwmgr             399 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
hwmgr             401 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDDPM);
hwmgr             402 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VCEDPM);
hwmgr             405 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	if (amdgpu_acpi_is_pcie_performance_request_supported(hwmgr->adev))
hwmgr             406 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
hwmgr             409 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             412 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             415 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             418 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             421 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             424 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             429 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c int hwmgr_set_user_specify_caps(struct pp_hwmgr *hwmgr)
hwmgr             431 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	if (hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK)
hwmgr             432 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             435 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             438 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	if (hwmgr->feature_mask & PP_POWER_CONTAINMENT_MASK) {
hwmgr             439 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             441 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             444 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             446 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             450 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	if (hwmgr->feature_mask & PP_OVERDRIVE_MASK)
hwmgr             451 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 		hwmgr->od_enabled = true;
hwmgr             456 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr)
hwmgr             458 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             460 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             462 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             465 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             468 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	if (hwmgr->chip_id != CHIP_POLARIS10)
hwmgr             469 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             472 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	if (hwmgr->chip_id != CHIP_POLARIS11) {
hwmgr             473 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             475 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             477 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             483 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr)
hwmgr             485 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             487 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             489 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             491 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             493 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             498 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr)
hwmgr             500 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             502 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             504 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             506 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             508 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             511 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             513 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             518 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr)
hwmgr             520 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             522 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             524 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             526 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             528 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             533 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c int ci_set_asic_special_caps(struct pp_hwmgr *hwmgr)
hwmgr             535 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             537 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             539 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             541 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             543 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             545 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr              29 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c int psm_init_power_state_table(struct pp_hwmgr *hwmgr)
hwmgr              37 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 	if (hwmgr->hwmgr_func->get_num_of_pp_table_entries == NULL)
hwmgr              40 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 	if (hwmgr->hwmgr_func->get_power_state_size == NULL)
hwmgr              43 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 	hwmgr->num_ps = table_entries = hwmgr->hwmgr_func->get_num_of_pp_table_entries(hwmgr);
hwmgr              45 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 	hwmgr->ps_size = size = hwmgr->hwmgr_func->get_power_state_size(hwmgr) +
hwmgr              53 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 	hwmgr->ps = kcalloc(table_entries, size, GFP_KERNEL);
hwmgr              54 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 	if (hwmgr->ps == NULL)
hwmgr              57 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 	hwmgr->request_ps = kzalloc(size, GFP_KERNEL);
hwmgr              58 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 	if (hwmgr->request_ps == NULL) {
hwmgr              59 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 		kfree(hwmgr->ps);
hwmgr              60 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 		hwmgr->ps = NULL;
hwmgr              64 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 	hwmgr->current_ps = kzalloc(size, GFP_KERNEL);
hwmgr              65 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 	if (hwmgr->current_ps == NULL) {
hwmgr              66 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 		kfree(hwmgr->request_ps);
hwmgr              67 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 		kfree(hwmgr->ps);
hwmgr              68 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 		hwmgr->request_ps = NULL;
hwmgr              69 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 		hwmgr->ps = NULL;
hwmgr              73 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 	state = hwmgr->ps;
hwmgr              76 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 		result = hwmgr->hwmgr_func->get_pp_table_entry(hwmgr, i, state);
hwmgr              79 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 			hwmgr->boot_ps = state;
hwmgr              80 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 			memcpy(hwmgr->current_ps, state, size);
hwmgr              81 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 			memcpy(hwmgr->request_ps, state, size);
hwmgr              87 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 			hwmgr->uvd_ps = state;
hwmgr              94 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c int psm_fini_power_state_table(struct pp_hwmgr *hwmgr)
hwmgr              96 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 	if (hwmgr == NULL)
hwmgr              99 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 	if (!hwmgr->ps)
hwmgr             102 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 	kfree(hwmgr->current_ps);
hwmgr             103 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 	kfree(hwmgr->request_ps);
hwmgr             104 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 	kfree(hwmgr->ps);
hwmgr             105 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 	hwmgr->request_ps = NULL;
hwmgr             106 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 	hwmgr->ps = NULL;
hwmgr             107 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 	hwmgr->current_ps = NULL;
hwmgr             111 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c static int psm_get_ui_state(struct pp_hwmgr *hwmgr,
hwmgr             119 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 	table_entries = hwmgr->num_ps;
hwmgr             120 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 	state = hwmgr->ps;
hwmgr             127 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 		state = (struct pp_power_state *)((unsigned long)state + hwmgr->ps_size);
hwmgr             132 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c static int psm_get_state_by_classification(struct pp_hwmgr *hwmgr,
hwmgr             140 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 	table_entries = hwmgr->num_ps;
hwmgr             141 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 	state = hwmgr->ps;
hwmgr             148 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 		state = (struct pp_power_state *)((unsigned long)state + hwmgr->ps_size);
hwmgr             153 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c static int psm_set_states(struct pp_hwmgr *hwmgr, unsigned long state_id)
hwmgr             159 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 	table_entries = hwmgr->num_ps;
hwmgr             161 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 	state = hwmgr->ps;
hwmgr             165 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 			memcpy(hwmgr->request_ps, state, hwmgr->ps_size);
hwmgr             168 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 		state = (struct pp_power_state *)((unsigned long)state + hwmgr->ps_size);
hwmgr             173 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c int psm_set_boot_states(struct pp_hwmgr *hwmgr)
hwmgr             178 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 	if (!hwmgr->ps)
hwmgr             181 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 	if (!psm_get_state_by_classification(hwmgr, PP_StateClassificationFlag_Boot,
hwmgr             183 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 		ret = psm_set_states(hwmgr, state_id);
hwmgr             188 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c int psm_set_performance_states(struct pp_hwmgr *hwmgr)
hwmgr             193 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 	if (!hwmgr->ps)
hwmgr             196 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 	if (!psm_get_ui_state(hwmgr, PP_StateUILabel_Performance,
hwmgr             198 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 		ret = psm_set_states(hwmgr, state_id);
hwmgr             203 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c int psm_set_user_performance_state(struct pp_hwmgr *hwmgr,
hwmgr             210 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 	if (!hwmgr->ps)
hwmgr             213 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 	table_entries = hwmgr->num_ps;
hwmgr             214 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 	*state = hwmgr->ps;
hwmgr             220 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 		*state = (struct pp_power_state *)((uintptr_t)*state + hwmgr->ps_size);
hwmgr             234 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c static void power_state_management(struct pp_hwmgr *hwmgr,
hwmgr             244 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 		requested = hwmgr->request_ps;
hwmgr             246 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 	pcurrent = hwmgr->current_ps;
hwmgr             248 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 	phm_apply_state_adjust_rules(hwmgr, requested, pcurrent);
hwmgr             249 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 	if (pcurrent == NULL || (0 != phm_check_states_equal(hwmgr,
hwmgr             253 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 	if (!equal || phm_check_smc_update_required_for_display_configuration(hwmgr)) {
hwmgr             254 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 		phm_set_power_state(hwmgr, &pcurrent->hardware, &requested->hardware);
hwmgr             255 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 		memcpy(hwmgr->current_ps, hwmgr->request_ps, hwmgr->ps_size);
hwmgr             259 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c int psm_adjust_power_state_dynamic(struct pp_hwmgr *hwmgr, bool skip_display_settings,
hwmgr             266 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 		phm_display_configuration_changed(hwmgr);
hwmgr             268 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 	if (hwmgr->ps)
hwmgr             269 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 		power_state_management(hwmgr, new_ps);
hwmgr             275 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 		phm_apply_clock_adjust_rules(hwmgr);
hwmgr             278 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 		phm_notify_smc_display_config_after_ps_adjustment(hwmgr);
hwmgr             280 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 	if (!phm_force_dpm_levels(hwmgr, hwmgr->request_dpm_level))
hwmgr             281 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 		hwmgr->dpm_level = hwmgr->request_dpm_level;
hwmgr             283 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 	if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
hwmgr             284 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 		index = fls(hwmgr->workload_mask);
hwmgr             286 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 		workload = hwmgr->workload_setting[index];
hwmgr             288 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 		if (hwmgr->power_profile_mode != workload && hwmgr->hwmgr_func->set_power_profile_mode)
hwmgr             289 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c 			hwmgr->hwmgr_func->set_power_profile_mode(hwmgr, &workload, 0);
hwmgr              29 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.h int psm_init_power_state_table(struct pp_hwmgr *hwmgr);
hwmgr              30 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.h int psm_fini_power_state_table(struct pp_hwmgr *hwmgr);
hwmgr              31 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.h int psm_set_boot_states(struct pp_hwmgr *hwmgr);
hwmgr              32 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.h int psm_set_performance_states(struct pp_hwmgr *hwmgr);
hwmgr              33 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.h int psm_set_user_performance_state(struct pp_hwmgr *hwmgr,
hwmgr              36 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.h int psm_adjust_power_state_dynamic(struct pp_hwmgr *hwmgr,
hwmgr             133 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		struct pp_hwmgr *hwmgr,
hwmgr             144 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		smu_atom_get_data_table(hwmgr->adev,
hwmgr             173 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		struct pp_hwmgr *hwmgr,
hwmgr             177 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             248 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		struct pp_hwmgr *hwmgr,
hwmgr             253 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             298 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c int atomctrl_get_memory_pll_dividers_vi(struct pp_hwmgr *hwmgr,
hwmgr             301 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             318 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c int atomctrl_get_memory_pll_dividers_ai(struct pp_hwmgr *hwmgr,
hwmgr             322 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             348 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c int atomctrl_get_engine_pll_dividers_kong(struct pp_hwmgr *hwmgr,
hwmgr             352 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             371 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		struct pp_hwmgr *hwmgr,
hwmgr             375 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             408 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c int atomctrl_get_engine_pll_dividers_ai(struct pp_hwmgr *hwmgr,
hwmgr             412 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             440 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		struct pp_hwmgr *hwmgr,
hwmgr             444 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             481 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c uint32_t atomctrl_get_reference_clock(struct pp_hwmgr *hwmgr)
hwmgr             489 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		smu_atom_get_data_table(hwmgr->adev,
hwmgr             508 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		struct pp_hwmgr *hwmgr,
hwmgr             513 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *)get_voltage_info_table(hwmgr->adev);
hwmgr             526 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		struct pp_hwmgr *hwmgr,
hwmgr             532 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *)get_voltage_info_table(hwmgr->adev);
hwmgr             623 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		struct pp_hwmgr *hwmgr,
hwmgr             629 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		get_gpio_lookup_table(hwmgr->adev);
hwmgr             641 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		struct pp_hwmgr *hwmgr,
hwmgr             650 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             677 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 			smu_atom_get_data_table(hwmgr->adev,
hwmgr            1085 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		struct pp_hwmgr *hwmgr,
hwmgr            1090 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr            1120 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c int atomctrl_get_voltage_evv(struct pp_hwmgr *hwmgr,
hwmgr            1124 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr            1130 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 	for (entry_id = 0; entry_id < hwmgr->dyn_state.vddc_dependency_on_sclk->count; entry_id++) {
hwmgr            1131 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		if (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[entry_id].v == virtual_voltage_id) {
hwmgr            1137 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 	if (entry_id >= hwmgr->dyn_state.vddc_dependency_on_sclk->count) {
hwmgr            1146 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		cpu_to_le32(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[entry_id].clk);
hwmgr            1164 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c uint32_t atomctrl_get_mpll_reference_clock(struct pp_hwmgr *hwmgr)
hwmgr            1172 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		smu_atom_get_data_table(hwmgr->adev,
hwmgr            1214 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c static int asic_internal_ss_get_ss_asignment(struct pp_hwmgr *hwmgr,
hwmgr            1225 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 	table = asic_internal_ss_get_ss_table(hwmgr->adev);
hwmgr            1278 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		struct pp_hwmgr *hwmgr,
hwmgr            1282 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 	return asic_internal_ss_get_ss_asignment(hwmgr,
hwmgr            1289 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		struct pp_hwmgr *hwmgr,
hwmgr            1293 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 	return asic_internal_ss_get_ss_asignment(hwmgr,
hwmgr            1297 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c int atomctrl_read_efuse(struct pp_hwmgr *hwmgr, uint16_t start_index,
hwmgr            1300 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr            1318 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock,
hwmgr            1321 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr            1338 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c int atomctrl_get_voltage_evv_on_sclk_ai(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
hwmgr            1341 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr            1360 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c int atomctrl_get_smc_sclk_range_table(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl_sclk_range_table *table)
hwmgr            1368 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		(ATOM_SMU_INFO_V2_1 *)smu_atom_get_data_table(hwmgr->adev,
hwmgr            1387 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c int atomctrl_get_avfs_information(struct pp_hwmgr *hwmgr,
hwmgr            1396 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 			smu_atom_get_data_table(hwmgr->adev,
hwmgr            1431 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c int  atomctrl_get_svi2_info(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
hwmgr            1436 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *)get_voltage_info_table(hwmgr->adev);
hwmgr            1453 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c int atomctrl_get_leakage_id_from_efuse(struct pp_hwmgr *hwmgr, uint16_t *virtual_voltage_id)
hwmgr            1455 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr            1472 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c int atomctrl_get_leakage_vddc_base_on_leakage(struct pp_hwmgr *hwmgr,
hwmgr            1488 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 			smu_atom_get_data_table(hwmgr->adev,
hwmgr            1534 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c void atomctrl_get_voltage_range(struct pp_hwmgr *hwmgr, uint32_t *max_vddc,
hwmgr            1539 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 	profile = smu_atom_get_data_table(hwmgr->adev,
hwmgr            1544 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c 		switch (hwmgr->chip_id) {
hwmgr             290 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h extern bool atomctrl_get_pp_assign_pin(struct pp_hwmgr *hwmgr, const uint32_t pinId, pp_atomctrl_gpio_pin_assignment *gpio_pin_assignment);
hwmgr             291 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h extern int atomctrl_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage);
hwmgr             292 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h extern int atomctrl_get_voltage_evv(struct pp_hwmgr *hwmgr, uint16_t virtual_voltage_id, uint16_t *voltage);
hwmgr             293 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h extern uint32_t atomctrl_get_mpll_reference_clock(struct pp_hwmgr *hwmgr);
hwmgr             294 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h extern int atomctrl_get_memory_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t memory_clock, pp_atomctrl_internal_ss_info *ssInfo);
hwmgr             295 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h extern int atomctrl_get_engine_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t engine_clock, pp_atomctrl_internal_ss_info *ssInfo);
hwmgr             296 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h extern int atomctrl_initialize_mc_reg_table(struct pp_hwmgr *hwmgr, uint8_t module_index, pp_atomctrl_mc_reg_table *table);
hwmgr             297 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h extern int atomctrl_set_engine_dram_timings_rv770(struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock);
hwmgr             298 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h extern uint32_t atomctrl_get_reference_clock(struct pp_hwmgr *hwmgr);
hwmgr             299 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h extern int atomctrl_get_memory_pll_dividers_si(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param, bool strobe_mode);
hwmgr             300 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h extern int atomctrl_get_engine_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers);
hwmgr             301 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h extern int atomctrl_get_dfs_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers);
hwmgr             302 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h extern bool atomctrl_is_voltage_controlled_by_gpio_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode);
hwmgr             303 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h extern int atomctrl_get_voltage_table_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode, pp_atomctrl_voltage_table *voltage_table);
hwmgr             304 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h extern int atomctrl_get_memory_pll_dividers_vi(struct pp_hwmgr *hwmgr,
hwmgr             306 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h extern int atomctrl_get_memory_pll_dividers_ai(struct pp_hwmgr *hwmgr,
hwmgr             308 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h extern int atomctrl_get_engine_pll_dividers_kong(struct pp_hwmgr *hwmgr,
hwmgr             311 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h extern int atomctrl_read_efuse(struct pp_hwmgr *hwmgr, uint16_t start_index,
hwmgr             313 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h extern int atomctrl_calculate_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
hwmgr             315 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h extern int atomctrl_get_engine_pll_dividers_ai(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_ai *dividers);
hwmgr             316 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h extern int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock,
hwmgr             318 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h extern int atomctrl_get_voltage_evv_on_sclk_ai(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
hwmgr             320 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h extern int atomctrl_get_smc_sclk_range_table(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl_sclk_range_table *table);
hwmgr             322 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h extern int atomctrl_get_avfs_information(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl__avfs_parameters *param);
hwmgr             324 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h extern int  atomctrl_get_svi2_info(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
hwmgr             328 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h extern int atomctrl_get_leakage_vddc_base_on_leakage(struct pp_hwmgr *hwmgr,
hwmgr             332 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h extern int atomctrl_get_leakage_id_from_efuse(struct pp_hwmgr *hwmgr, uint16_t *virtual_voltage_id);
hwmgr             334 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h extern void atomctrl_get_voltage_range(struct pp_hwmgr *hwmgr, uint32_t *max_vddc,
hwmgr              55 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c 		struct pp_hwmgr *hwmgr)
hwmgr              61 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c 	table_address = smu_atom_get_data_table(hwmgr->adev,
hwmgr              76 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c bool pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(struct pp_hwmgr *hwmgr,
hwmgr              81 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c 			pp_atomfwctrl_get_voltage_info_table(hwmgr);
hwmgr              95 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c int pp_atomfwctrl_get_voltage_table_v4(struct pp_hwmgr *hwmgr,
hwmgr             101 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c 			pp_atomfwctrl_get_voltage_info_table(hwmgr);
hwmgr             163 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c 		struct pp_hwmgr *hwmgr)
hwmgr             169 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c 	table_address =	smu_atom_get_data_table(hwmgr->adev,
hwmgr             208 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c bool pp_atomfwctrl_get_pp_assign_pin(struct pp_hwmgr *hwmgr,
hwmgr             214 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c 			pp_atomfwctrl_get_gpio_lookup_table(hwmgr);
hwmgr             231 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c int pp_atomfwctrl_enter_self_refresh(struct pp_hwmgr *hwmgr)
hwmgr             246 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c int pp_atomfwctrl_get_gpu_pll_dividers_vega10(struct pp_hwmgr *hwmgr,
hwmgr             250 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             276 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c int pp_atomfwctrl_get_avfs_information(struct pp_hwmgr *hwmgr,
hwmgr             287 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c 			smu_atom_get_data_table(hwmgr->adev,
hwmgr             463 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c int pp_atomfwctrl_get_gpio_information(struct pp_hwmgr *hwmgr,
hwmgr             471 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c 		smu_atom_get_data_table(hwmgr->adev,
hwmgr             491 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c int pp_atomfwctrl_get_clk_information_by_clkid(struct pp_hwmgr *hwmgr,
hwmgr             495 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             517 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c static void pp_atomfwctrl_copy_vbios_bootup_values_3_2(struct pp_hwmgr *hwmgr,
hwmgr             534 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c 	if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU11_SYSPLL0_SOCCLK_ID, SMU11_SYSPLL0_ID, &frequency))
hwmgr             537 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c 	if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU11_SYSPLL0_DCEFCLK_ID, SMU11_SYSPLL0_ID, &frequency))
hwmgr             540 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c 	if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU11_SYSPLL0_ECLK_ID, SMU11_SYSPLL0_ID, &frequency))
hwmgr             543 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c 	if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU11_SYSPLL0_VCLK_ID, SMU11_SYSPLL0_ID, &frequency))
hwmgr             546 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c 	if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU11_SYSPLL0_DCLK_ID, SMU11_SYSPLL0_ID, &frequency))
hwmgr             549 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c 	if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU11_SYSPLL1_0_FCLK_ID, SMU11_SYSPLL1_2_ID, &frequency))
hwmgr             553 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c static void pp_atomfwctrl_copy_vbios_bootup_values_3_1(struct pp_hwmgr *hwmgr,
hwmgr             570 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c 	if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU9_SYSPLL0_SOCCLK_ID, 0, &frequency))
hwmgr             573 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c 	if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU9_SYSPLL0_DCEFCLK_ID, 0, &frequency))
hwmgr             576 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c 	if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU9_SYSPLL0_ECLK_ID, 0, &frequency))
hwmgr             579 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c 	if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU9_SYSPLL0_VCLK_ID, 0, &frequency))
hwmgr             582 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c 	if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr, SMU9_SYSPLL0_DCLK_ID, 0, &frequency))
hwmgr             586 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c int pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr,
hwmgr             596 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c 		smu_atom_get_data_table(hwmgr->adev,
hwmgr             606 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c 		pp_atomfwctrl_copy_vbios_bootup_values_3_2(hwmgr,
hwmgr             610 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c 		pp_atomfwctrl_copy_vbios_bootup_values_3_1(hwmgr,
hwmgr             620 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c int pp_atomfwctrl_get_smc_dpm_information(struct pp_hwmgr *hwmgr,
hwmgr             628 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c 		smu_atom_get_data_table(hwmgr->adev,
hwmgr             218 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h int pp_atomfwctrl_get_gpu_pll_dividers_vega10(struct pp_hwmgr *hwmgr,
hwmgr             221 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h int pp_atomfwctrl_enter_self_refresh(struct pp_hwmgr *hwmgr);
hwmgr             222 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h bool pp_atomfwctrl_get_pp_assign_pin(struct pp_hwmgr *hwmgr, const uint32_t pin_id,
hwmgr             225 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h int pp_atomfwctrl_get_voltage_table_v4(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
hwmgr             227 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h bool pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(struct pp_hwmgr *hwmgr,
hwmgr             230 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h int pp_atomfwctrl_get_avfs_information(struct pp_hwmgr *hwmgr,
hwmgr             232 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h int pp_atomfwctrl_get_gpio_information(struct pp_hwmgr *hwmgr,
hwmgr             235 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h int pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr,
hwmgr             237 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h int pp_atomfwctrl_get_smc_dpm_information(struct pp_hwmgr *hwmgr,
hwmgr             239 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h int pp_atomfwctrl_get_clk_information_by_clkid(struct pp_hwmgr *hwmgr,
hwmgr              40 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c static void set_hw_cap(struct pp_hwmgr *hwmgr, bool setIt, enum phm_platform_caps cap)
hwmgr              43 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps, cap);
hwmgr              45 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps, cap);
hwmgr              55 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c static int set_platform_caps(struct pp_hwmgr *hwmgr, uint32_t powerplay_caps)
hwmgr              69 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 			hwmgr,
hwmgr              75 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 			hwmgr,
hwmgr              81 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 			hwmgr,
hwmgr              87 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 			hwmgr,
hwmgr              93 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 			hwmgr,
hwmgr              99 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 			hwmgr,
hwmgr             105 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 			hwmgr,
hwmgr             111 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 			hwmgr,
hwmgr             117 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 			hwmgr,
hwmgr             123 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 			hwmgr,
hwmgr             134 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c static const void *get_powerplay_table(struct pp_hwmgr *hwmgr)
hwmgr             140 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	void *table_address = (void *)hwmgr->soft_pp_table;
hwmgr             144 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 				smu_atom_get_data_table(hwmgr->adev,
hwmgr             146 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		hwmgr->soft_pp_table = table_address;	/*Cache the result in RAM.*/
hwmgr             147 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		hwmgr->soft_pp_table_size = size;
hwmgr             154 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		struct pp_hwmgr	*hwmgr,
hwmgr             204 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		struct pp_hwmgr *hwmgr,
hwmgr             209 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr             247 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		struct pp_hwmgr *hwmgr,
hwmgr             252 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	struct phm_ppt_v1_information *pp_table_information = (struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr             264 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	hwmgr->platform_descriptor.TDPODLimit =
hwmgr             266 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	hwmgr->platform_descriptor.TDPAdjustment = 0;
hwmgr             267 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	hwmgr->platform_descriptor.VidAdjustment = 0;
hwmgr             268 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	hwmgr->platform_descriptor.VidAdjustmentPolarity = 0;
hwmgr             269 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	hwmgr->platform_descriptor.VidMinLimit = 0;
hwmgr             270 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	hwmgr->platform_descriptor.VidMaxLimit = 1500000;
hwmgr             271 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	hwmgr->platform_descriptor.VidStep = 6250;
hwmgr             276 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		if (hwmgr->platform_descriptor.TDPODLimit != 0)
hwmgr             277 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 			phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             286 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		result = get_vddc_lookup_table(hwmgr,
hwmgr             295 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		result = get_vddc_lookup_table(hwmgr,
hwmgr             305 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 			if (get_platform_power_management_table(hwmgr, atom_ppm_table) == 0) {
hwmgr             306 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 				phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             316 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		struct pp_hwmgr *hwmgr,
hwmgr             350 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		struct pp_hwmgr *hwmgr,
hwmgr             368 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		struct pp_hwmgr *hwmgr,
hwmgr             411 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		struct pp_hwmgr *hwmgr,
hwmgr             492 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		struct pp_hwmgr *hwmgr,
hwmgr             500 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr             588 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		struct pp_hwmgr *hwmgr,
hwmgr             602 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	hwmgr->dyn_state.cac_dtp_table = kzalloc(table_size, GFP_KERNEL);
hwmgr             604 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	if (NULL == hwmgr->dyn_state.cac_dtp_table) {
hwmgr             688 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		struct pp_hwmgr *hwmgr,
hwmgr             731 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c static int get_gpio_table(struct pp_hwmgr *hwmgr,
hwmgr             738 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr             764 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		struct pp_hwmgr *hwmgr,
hwmgr             770 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr             801 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		result = get_mm_clock_voltage_table(hwmgr,
hwmgr             805 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		result = get_cac_tdp_table(hwmgr,
hwmgr             809 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		result = get_sclk_voltage_dependency_table(hwmgr,
hwmgr             813 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		result = get_mclk_voltage_dependency_table(hwmgr,
hwmgr             817 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		result = get_pcie_table(hwmgr,
hwmgr             821 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		result = get_hard_limits(hwmgr,
hwmgr             824 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	hwmgr->dyn_state.max_clock_voltage_on_dc.sclk =
hwmgr             826 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	hwmgr->dyn_state.max_clock_voltage_on_dc.mclk =
hwmgr             828 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
hwmgr             830 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	hwmgr->dyn_state.max_clock_voltage_on_dc.vddci =
hwmgr             835 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		result = get_valid_clk(hwmgr, &pp_table_information->valid_mclk_values,
hwmgr             840 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		result = get_valid_clk(hwmgr, &pp_table_information->valid_sclk_values,
hwmgr             844 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		result = get_gpio_table(hwmgr, &pp_table_information->gpio_table,
hwmgr             861 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		struct pp_hwmgr *hwmgr,
hwmgr             864 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	hwmgr->platform_descriptor.overdriveLimit.engineClock =
hwmgr             866 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	hwmgr->platform_descriptor.overdriveLimit.memoryClock =
hwmgr             869 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	hwmgr->platform_descriptor.minOverdriveVDDC = 0;
hwmgr             870 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	hwmgr->platform_descriptor.maxOverdriveVDDC = 0;
hwmgr             871 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	hwmgr->platform_descriptor.overdriveVDDCStep = 0;
hwmgr             884 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		struct pp_hwmgr *hwmgr,
hwmgr             897 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	hwmgr->thermal_controller.ucType = thermal_controller->ucType;
hwmgr             898 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	hwmgr->thermal_controller.ucI2cLine = thermal_controller->ucI2cLine;
hwmgr             899 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	hwmgr->thermal_controller.ucI2cAddress = thermal_controller->ucI2cAddress;
hwmgr             901 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	hwmgr->thermal_controller.fanInfo.bNoFan =
hwmgr             904 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution =
hwmgr             908 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	hwmgr->thermal_controller.fanInfo.ulMinRPM
hwmgr             910 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	hwmgr->thermal_controller.fanInfo.ulMaxRPM
hwmgr             914 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 			hwmgr,
hwmgr             915 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 			ATOM_TONGA_PP_THERMALCONTROLLER_NONE != hwmgr->thermal_controller.ucType,
hwmgr             920 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		hwmgr->thermal_controller.use_hw_fan_control = 1;
hwmgr             933 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	hwmgr->thermal_controller.advanceFanControlParameters.ulCycleDelay
hwmgr             935 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             941 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		hwmgr->thermal_controller.advanceFanControlParameters.ucTHyst
hwmgr             943 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		hwmgr->thermal_controller.advanceFanControlParameters.usTMin
hwmgr             945 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		hwmgr->thermal_controller.advanceFanControlParameters.usTMed
hwmgr             947 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		hwmgr->thermal_controller.advanceFanControlParameters.usTHigh
hwmgr             949 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin
hwmgr             951 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed
hwmgr             953 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh
hwmgr             955 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		hwmgr->thermal_controller.advanceFanControlParameters.usTMax
hwmgr             957 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		hwmgr->thermal_controller.advanceFanControlParameters.usTMax
hwmgr             959 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode
hwmgr             961 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM
hwmgr             963 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity
hwmgr             965 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity
hwmgr             967 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM
hwmgr             969 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit
hwmgr             971 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		hwmgr->thermal_controller.advanceFanControlParameters.ucTargetTemperature
hwmgr             973 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit
hwmgr             978 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		hwmgr->thermal_controller.advanceFanControlParameters.ucTHyst
hwmgr             980 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		hwmgr->thermal_controller.advanceFanControlParameters.usTMin
hwmgr             982 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		hwmgr->thermal_controller.advanceFanControlParameters.usTMed
hwmgr             984 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		hwmgr->thermal_controller.advanceFanControlParameters.usTHigh
hwmgr             986 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin
hwmgr             988 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed
hwmgr             990 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh
hwmgr             992 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		hwmgr->thermal_controller.advanceFanControlParameters.usTMax
hwmgr             994 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode
hwmgr             996 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM
hwmgr             998 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity
hwmgr            1000 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity
hwmgr            1002 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM
hwmgr            1004 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit
hwmgr            1006 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		hwmgr->thermal_controller.advanceFanControlParameters.ucTargetTemperature
hwmgr            1008 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit
hwmgr            1011 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainEdge
hwmgr            1013 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHotspot
hwmgr            1015 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainLiquid
hwmgr            1017 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrVddc
hwmgr            1019 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrMvdd
hwmgr            1021 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainPlx
hwmgr            1023 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHbm
hwmgr            1038 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		struct pp_hwmgr *hwmgr,
hwmgr            1060 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c static int pp_tables_v1_0_initialize(struct pp_hwmgr *hwmgr)
hwmgr            1065 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	hwmgr->pptable = kzalloc(sizeof(struct phm_ppt_v1_information), GFP_KERNEL);
hwmgr            1067 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	PP_ASSERT_WITH_CODE((NULL != hwmgr->pptable),
hwmgr            1070 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	powerplay_table = get_powerplay_table(hwmgr);
hwmgr            1075 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	result = check_powerplay_tables(hwmgr, powerplay_table);
hwmgr            1080 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	result = set_platform_caps(hwmgr,
hwmgr            1086 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	result = init_thermal_controller(hwmgr, powerplay_table);
hwmgr            1091 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	result = init_over_drive_limits(hwmgr, powerplay_table);
hwmgr            1096 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	result = init_clock_voltage_dependency(hwmgr, powerplay_table);
hwmgr            1101 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	result = init_dpm_2_parameters(hwmgr, powerplay_table);
hwmgr            1109 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c static int pp_tables_v1_0_uninitialize(struct pp_hwmgr *hwmgr)
hwmgr            1112 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            1138 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	kfree(hwmgr->dyn_state.cac_dtp_table);
hwmgr            1139 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	hwmgr->dyn_state.cac_dtp_table = NULL;
hwmgr            1150 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	kfree(hwmgr->pptable);
hwmgr            1151 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	hwmgr->pptable = NULL;
hwmgr            1161 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c int get_number_of_powerplay_table_entries_v1_0(struct pp_hwmgr *hwmgr)
hwmgr            1164 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	const ATOM_Tonga_POWERPLAYTABLE *pp_table = get_powerplay_table(hwmgr);
hwmgr            1181 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c static uint32_t make_classification_flags(struct pp_hwmgr *hwmgr,
hwmgr            1210 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c static int ppt_get_num_of_vce_state_table_entries_v1_0(struct pp_hwmgr *hwmgr)
hwmgr            1212 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	const ATOM_Tonga_POWERPLAYTABLE *pp_table = get_powerplay_table(hwmgr);
hwmgr            1225 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c static int ppt_get_vce_state_table_entry_v1_0(struct pp_hwmgr *hwmgr, uint32_t i,
hwmgr            1232 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	const ATOM_Tonga_POWERPLAYTABLE *pptable = get_powerplay_table(hwmgr);
hwmgr            1286 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c int get_powerplay_table_entry_v1_0(struct pp_hwmgr *hwmgr,
hwmgr            1294 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	const ATOM_Tonga_POWERPLAYTABLE *pp_table = get_powerplay_table(hwmgr);
hwmgr            1317 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		result = call_back_func(hwmgr, (void *)state_entry, power_state,
hwmgr            1319 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 				make_classification_flags(hwmgr,
hwmgr            1326 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 		result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(power_state->hardware));
hwmgr            1328 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 	hwmgr->num_vce_state_tables = i = ppt_get_num_of_vce_state_table_entries_v1_0(hwmgr);
hwmgr            1332 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 			ppt_get_vce_state_table_entry_v1_0(hwmgr, j, &(hwmgr->vce_states[j]), NULL, &flags);
hwmgr              29 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.h extern int get_number_of_powerplay_table_entries_v1_0(struct pp_hwmgr *hwmgr);
hwmgr              30 drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.h extern int get_powerplay_table_entry_v1_0(struct pp_hwmgr *hwmgr, uint32_t entry_index,
hwmgr              48 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c static uint16_t get_vce_table_offset(struct pp_hwmgr *hwmgr,
hwmgr              72 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c static uint16_t get_vce_clock_info_array_offset(struct pp_hwmgr *hwmgr,
hwmgr              75 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	uint16_t table_offset = get_vce_table_offset(hwmgr,
hwmgr              84 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c static uint16_t get_vce_clock_info_array_size(struct pp_hwmgr *hwmgr,
hwmgr              87 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	uint16_t table_offset = get_vce_clock_info_array_offset(hwmgr,
hwmgr             100 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c static uint16_t get_vce_clock_voltage_limit_table_offset(struct pp_hwmgr *hwmgr,
hwmgr             103 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	uint16_t table_offset = get_vce_clock_info_array_offset(hwmgr,
hwmgr             107 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		return table_offset + get_vce_clock_info_array_size(hwmgr,
hwmgr             113 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c static uint16_t get_vce_clock_voltage_limit_table_size(struct pp_hwmgr *hwmgr,
hwmgr             116 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	uint16_t table_offset = get_vce_clock_voltage_limit_table_offset(hwmgr, powerplay_table);
hwmgr             128 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c static uint16_t get_vce_state_table_offset(struct pp_hwmgr *hwmgr, const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
hwmgr             130 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	uint16_t table_offset = get_vce_clock_voltage_limit_table_offset(hwmgr, powerplay_table);
hwmgr             133 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		return table_offset + get_vce_clock_voltage_limit_table_size(hwmgr, powerplay_table);
hwmgr             139 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 						struct pp_hwmgr *hwmgr,
hwmgr             142 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	uint16_t table_offset = get_vce_state_table_offset(hwmgr, powerplay_table);
hwmgr             150 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c static uint16_t get_uvd_table_offset(struct pp_hwmgr *hwmgr,
hwmgr             172 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c static uint16_t get_uvd_clock_info_array_offset(struct pp_hwmgr *hwmgr,
hwmgr             175 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	uint16_t table_offset = get_uvd_table_offset(hwmgr,
hwmgr             183 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c static uint16_t get_uvd_clock_info_array_size(struct pp_hwmgr *hwmgr,
hwmgr             186 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	uint16_t table_offset = get_uvd_clock_info_array_offset(hwmgr,
hwmgr             202 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 			struct pp_hwmgr *hwmgr,
hwmgr             205 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	uint16_t table_offset = get_uvd_clock_info_array_offset(hwmgr,
hwmgr             210 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 			get_uvd_clock_info_array_size(hwmgr, powerplay_table);
hwmgr             215 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c static uint16_t get_samu_table_offset(struct pp_hwmgr *hwmgr,
hwmgr             239 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 			struct pp_hwmgr *hwmgr,
hwmgr             242 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	uint16_t table_offset = get_samu_table_offset(hwmgr,
hwmgr             251 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c static uint16_t get_acp_table_offset(struct pp_hwmgr *hwmgr,
hwmgr             275 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 				struct pp_hwmgr *hwmgr,
hwmgr             278 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	uint16_t tableOffset = get_acp_table_offset(hwmgr, powerplay_table);
hwmgr             287 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 				struct pp_hwmgr *hwmgr,
hwmgr             310 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c static int get_cac_tdp_table(struct pp_hwmgr *hwmgr,
hwmgr             338 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c static uint16_t get_sclk_vdd_gfx_table_offset(struct pp_hwmgr *hwmgr,
hwmgr             363 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 			struct pp_hwmgr *hwmgr,
hwmgr             366 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	uint16_t tableOffset = get_sclk_vdd_gfx_table_offset(hwmgr, powerplay_table);
hwmgr             375 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c static int get_clock_voltage_dependency_table(struct pp_hwmgr *hwmgr,
hwmgr             406 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c static int get_valid_clk(struct pp_hwmgr *hwmgr,
hwmgr             428 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c static int get_clock_voltage_limit(struct pp_hwmgr *hwmgr,
hwmgr             443 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c static void set_hw_cap(struct pp_hwmgr *hwmgr, bool enable,
hwmgr             447 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps, cap);
hwmgr             449 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps, cap);
hwmgr             452 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c static int set_platform_caps(struct pp_hwmgr *hwmgr,
hwmgr             456 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		hwmgr,
hwmgr             462 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		hwmgr,
hwmgr             468 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		hwmgr,
hwmgr             474 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		hwmgr,
hwmgr             480 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		hwmgr,
hwmgr             486 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		hwmgr,
hwmgr             492 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		hwmgr,
hwmgr             498 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		hwmgr,
hwmgr             504 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		hwmgr,
hwmgr             510 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		hwmgr,
hwmgr             516 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		hwmgr,
hwmgr             522 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		hwmgr,
hwmgr             528 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		hwmgr,
hwmgr             534 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		hwmgr,
hwmgr             540 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		hwmgr,
hwmgr             546 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		hwmgr,
hwmgr             552 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		hwmgr,
hwmgr             558 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		hwmgr,
hwmgr             564 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		hwmgr,
hwmgr             570 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		hwmgr,
hwmgr             576 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		hwmgr,
hwmgr             582 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		hwmgr,
hwmgr             588 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		hwmgr,
hwmgr             594 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		hwmgr,
hwmgr             600 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		hwmgr,
hwmgr             606 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		hwmgr,
hwmgr             612 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		hwmgr,
hwmgr             621 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 						   struct pp_hwmgr *hwmgr,
hwmgr             678 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c static int init_non_clock_fields(struct pp_hwmgr *hwmgr,
hwmgr             687 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	ps->classification.flags = make_classification_flags(hwmgr,
hwmgr             828 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 				     struct pp_hwmgr *hwmgr)
hwmgr             830 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	const void *table_addr = hwmgr->soft_pp_table;
hwmgr             835 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		if (hwmgr->chip_id == CHIP_RAVEN) {
hwmgr             837 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 			hwmgr->soft_pp_table = &soft_dummy_pp_table[0];
hwmgr             838 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 			hwmgr->soft_pp_table_size = sizeof(soft_dummy_pp_table);
hwmgr             840 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 			table_addr = smu_atom_get_data_table(hwmgr->adev,
hwmgr             843 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 			hwmgr->soft_pp_table = table_addr;
hwmgr             844 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 			hwmgr->soft_pp_table_size = size;
hwmgr             851 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c int pp_tables_get_response_times(struct pp_hwmgr *hwmgr,
hwmgr             854 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	const ATOM_PPLIB_POWERPLAYTABLE *powerplay_tab = get_powerplay_table(hwmgr);
hwmgr             865 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c int pp_tables_get_num_of_entries(struct pp_hwmgr *hwmgr,
hwmgr             869 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table = get_powerplay_table(hwmgr);
hwmgr             885 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c int pp_tables_get_entry(struct pp_hwmgr *hwmgr,
hwmgr             894 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table = get_powerplay_table(hwmgr);
hwmgr             926 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		result = init_non_clock_fields(hwmgr, ps, pnon_clock_arrays->ucEntrySize, pnon_clock_info);
hwmgr             932 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 			res = func(hwmgr, &ps->hardware, i, pclock_info);
hwmgr             949 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		result = init_non_clock_fields(hwmgr, ps,
hwmgr             959 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 			int res = func(hwmgr, &ps->hardware, i, pclock_info);
hwmgr             967 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		if (hwmgr->chip_family < AMDGPU_FAMILY_RV)
hwmgr             968 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 			result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(ps->hardware));
hwmgr             975 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 			struct pp_hwmgr *hwmgr,
hwmgr             984 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 			struct pp_hwmgr *hwmgr,
hwmgr             987 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->thermal_controller.ucType =
hwmgr             989 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->thermal_controller.ucI2cLine =
hwmgr             991 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->thermal_controller.ucI2cAddress =
hwmgr             994 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->thermal_controller.fanInfo.bNoFan =
hwmgr             998 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution =
hwmgr            1002 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->thermal_controller.fanInfo.ulMinRPM
hwmgr            1004 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->thermal_controller.fanInfo.ulMaxRPM
hwmgr            1007 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	set_hw_cap(hwmgr,
hwmgr            1008 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		   ATOM_PP_THERMALCONTROLLER_NONE != hwmgr->thermal_controller.ucType,
hwmgr            1011 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->thermal_controller.use_hw_fan_control = 1;
hwmgr            1016 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c static int init_overdrive_limits_V1_4(struct pp_hwmgr *hwmgr,
hwmgr            1020 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->platform_descriptor.overdriveLimit.engineClock =
hwmgr            1023 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->platform_descriptor.overdriveLimit.memoryClock =
hwmgr            1026 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->platform_descriptor.maxOverdriveVDDC =
hwmgr            1029 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->platform_descriptor.minOverdriveVDDC =
hwmgr            1032 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->platform_descriptor.maxOverdriveVDDC =
hwmgr            1035 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->platform_descriptor.overdriveVDDCStep = 0;
hwmgr            1039 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c static int init_overdrive_limits_V2_1(struct pp_hwmgr *hwmgr,
hwmgr            1058 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->platform_descriptor.overdriveLimit.engineClock = le32_to_cpu(header->ulMaxEngineClock);
hwmgr            1059 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->platform_descriptor.overdriveLimit.memoryClock = le32_to_cpu(header->ulMaxMemoryClock);
hwmgr            1062 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->platform_descriptor.minOverdriveVDDC = 0;
hwmgr            1063 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->platform_descriptor.maxOverdriveVDDC = 0;
hwmgr            1064 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->platform_descriptor.overdriveVDDCStep = 0;
hwmgr            1069 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c static int init_overdrive_limits(struct pp_hwmgr *hwmgr,
hwmgr            1078 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->platform_descriptor.overdriveLimit.engineClock = 0;
hwmgr            1079 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->platform_descriptor.overdriveLimit.memoryClock = 0;
hwmgr            1080 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->platform_descriptor.minOverdriveVDDC = 0;
hwmgr            1081 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->platform_descriptor.maxOverdriveVDDC = 0;
hwmgr            1082 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->platform_descriptor.overdriveVDDCStep = 0;
hwmgr            1084 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	if (hwmgr->chip_id == CHIP_RAVEN)
hwmgr            1088 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	fw_info = smu_atom_get_data_table(hwmgr->adev,
hwmgr            1094 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		result = init_overdrive_limits_V1_4(hwmgr,
hwmgr            1100 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		result = init_overdrive_limits_V2_1(hwmgr,
hwmgr            1107 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c static int get_uvd_clock_voltage_limit_table(struct pp_hwmgr *hwmgr,
hwmgr            1140 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c static int get_vce_clock_voltage_limit_table(struct pp_hwmgr *hwmgr,
hwmgr            1172 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c static int get_samu_clock_voltage_limit_table(struct pp_hwmgr *hwmgr,
hwmgr            1200 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c static int get_acp_clock_voltage_limit_table(struct pp_hwmgr *hwmgr,
hwmgr            1228 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c static int init_clock_voltage_dependency(struct pp_hwmgr *hwmgr,
hwmgr            1239 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->dyn_state.vddc_dependency_on_sclk = NULL;
hwmgr            1240 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->dyn_state.vddci_dependency_on_mclk = NULL;
hwmgr            1241 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->dyn_state.vddc_dependency_on_mclk = NULL;
hwmgr            1242 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
hwmgr            1243 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->dyn_state.mvdd_dependency_on_mclk = NULL;
hwmgr            1244 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->dyn_state.vce_clock_voltage_dependency_table = NULL;
hwmgr            1245 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->dyn_state.uvd_clock_voltage_dependency_table = NULL;
hwmgr            1246 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->dyn_state.samu_clock_voltage_dependency_table = NULL;
hwmgr            1247 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->dyn_state.acp_clock_voltage_dependency_table = NULL;
hwmgr            1248 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->dyn_state.ppm_parameter_table = NULL;
hwmgr            1249 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->dyn_state.vdd_gfx_dependency_on_sclk = NULL;
hwmgr            1252 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 						hwmgr, powerplay_table);
hwmgr            1253 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	table_offset = get_vce_clock_voltage_limit_table_offset(hwmgr,
hwmgr            1262 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		result = get_vce_clock_voltage_limit_table(hwmgr,
hwmgr            1263 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 				&hwmgr->dyn_state.vce_clock_voltage_dependency_table,
hwmgr            1267 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	uvd_clock_info_array_offset = get_uvd_clock_info_array_offset(hwmgr, powerplay_table);
hwmgr            1268 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	table_offset = get_uvd_clock_voltage_limit_table_offset(hwmgr, powerplay_table);
hwmgr            1277 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		result = get_uvd_clock_voltage_limit_table(hwmgr,
hwmgr            1278 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 				&hwmgr->dyn_state.uvd_clock_voltage_dependency_table, ptable, array);
hwmgr            1281 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	table_offset = get_samu_clock_voltage_limit_table_offset(hwmgr,
hwmgr            1288 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		result = get_samu_clock_voltage_limit_table(hwmgr,
hwmgr            1289 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 				&hwmgr->dyn_state.samu_clock_voltage_dependency_table, ptable);
hwmgr            1292 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	table_offset = get_acp_clock_voltage_limit_table_offset(hwmgr,
hwmgr            1299 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		result = get_acp_clock_voltage_limit_table(hwmgr,
hwmgr            1300 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 				&hwmgr->dyn_state.acp_clock_voltage_dependency_table, ptable);
hwmgr            1303 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	table_offset = get_cacp_tdp_table_offset(hwmgr, powerplay_table);
hwmgr            1311 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 			result = get_cac_tdp_table(hwmgr, &hwmgr->dyn_state.cac_dtp_table,
hwmgr            1314 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 			hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp =
hwmgr            1320 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 			result = get_cac_tdp_table(hwmgr,
hwmgr            1321 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 				&hwmgr->dyn_state.cac_dtp_table,
hwmgr            1334 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 			result = get_clock_voltage_dependency_table(hwmgr,
hwmgr            1335 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 				&hwmgr->dyn_state.vddc_dependency_on_sclk, table);
hwmgr            1342 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 			result = get_clock_voltage_dependency_table(hwmgr,
hwmgr            1343 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 				&hwmgr->dyn_state.vddci_dependency_on_mclk, table);
hwmgr            1350 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 			result = get_clock_voltage_dependency_table(hwmgr,
hwmgr            1351 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 				&hwmgr->dyn_state.vddc_dependency_on_mclk, table);
hwmgr            1358 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 			result = get_clock_voltage_limit(hwmgr,
hwmgr            1359 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 				&hwmgr->dyn_state.max_clock_voltage_on_dc, limit_table);
hwmgr            1362 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		if (result == 0 && (NULL != hwmgr->dyn_state.vddc_dependency_on_mclk) &&
hwmgr            1363 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 			(0 != hwmgr->dyn_state.vddc_dependency_on_mclk->count))
hwmgr            1364 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 			result = get_valid_clk(hwmgr, &hwmgr->dyn_state.valid_mclk_values,
hwmgr            1365 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 					hwmgr->dyn_state.vddc_dependency_on_mclk);
hwmgr            1367 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		if(result == 0 && (NULL != hwmgr->dyn_state.vddc_dependency_on_sclk) &&
hwmgr            1368 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 			(0 != hwmgr->dyn_state.vddc_dependency_on_sclk->count))
hwmgr            1369 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 			result = get_valid_clk(hwmgr,
hwmgr            1370 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 				&hwmgr->dyn_state.valid_sclk_values,
hwmgr            1371 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 				hwmgr->dyn_state.vddc_dependency_on_sclk);
hwmgr            1377 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 			result = get_clock_voltage_dependency_table(hwmgr,
hwmgr            1378 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 				&hwmgr->dyn_state.mvdd_dependency_on_mclk, table);
hwmgr            1382 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	table_offset = get_sclk_vdd_gfx_clock_voltage_dependency_table_offset(hwmgr,
hwmgr            1388 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		result = get_clock_voltage_dependency_table(hwmgr,
hwmgr            1389 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 			&hwmgr->dyn_state.vdd_gfx_dependency_on_sclk, table);
hwmgr            1395 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c static int get_cac_leakage_table(struct pp_hwmgr *hwmgr,
hwmgr            1402 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	if (hwmgr == NULL || table == NULL || ptable == NULL)
hwmgr            1416 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            1432 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c static int get_platform_power_management_table(struct pp_hwmgr *hwmgr,
hwmgr            1450 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->dyn_state.ppm_parameter_table = ptr;
hwmgr            1455 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c static int init_dpm2_parameters(struct pp_hwmgr *hwmgr,
hwmgr            1474 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		hwmgr->platform_descriptor.TDPLimit     = le32_to_cpu(ptable5->ulTDPLimit);
hwmgr            1475 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		hwmgr->platform_descriptor.nearTDPLimit = le32_to_cpu(ptable5->ulNearTDPLimit);
hwmgr            1477 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		hwmgr->platform_descriptor.TDPODLimit   = le16_to_cpu(ptable5->usTDPODLimit);
hwmgr            1478 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		hwmgr->platform_descriptor.TDPAdjustment = 0;
hwmgr            1480 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		hwmgr->platform_descriptor.VidAdjustment = 0;
hwmgr            1481 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		hwmgr->platform_descriptor.VidAdjustmentPolarity = 0;
hwmgr            1482 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		hwmgr->platform_descriptor.VidMinLimit     = 0;
hwmgr            1483 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		hwmgr->platform_descriptor.VidMaxLimit     = 1500000;
hwmgr            1484 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		hwmgr->platform_descriptor.VidStep         = 6250;
hwmgr            1486 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		hwmgr->platform_descriptor.nearTDPLimitAdjusted = le32_to_cpu(ptable5->ulNearTDPLimit);
hwmgr            1488 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		if (hwmgr->platform_descriptor.TDPODLimit != 0)
hwmgr            1489 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 			phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr            1492 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		hwmgr->platform_descriptor.SQRampingThreshold = le32_to_cpu(ptable5->ulSQRampingThreshold);
hwmgr            1494 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		hwmgr->platform_descriptor.CACLeakage = le32_to_cpu(ptable5->ulCACLeakage);
hwmgr            1496 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		hwmgr->dyn_state.cac_leakage_table = NULL;
hwmgr            1502 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 			result = get_cac_leakage_table(hwmgr,
hwmgr            1503 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 				&hwmgr->dyn_state.cac_leakage_table, pCAC_leakage_table);
hwmgr            1506 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		hwmgr->platform_descriptor.LoadLineSlope = le16_to_cpu(ptable5->usLoadLineSlope);
hwmgr            1508 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 		hwmgr->dyn_state.ppm_parameter_table = NULL;
hwmgr            1520 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 				if (0 == get_platform_power_management_table(hwmgr, atom_ppm_table))
hwmgr            1521 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 					phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr            1529 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c static int init_phase_shedding_table(struct pp_hwmgr *hwmgr,
hwmgr            1564 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 			hwmgr->dyn_state.vddc_phase_shed_limits_table = table;
hwmgr            1572 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 						  struct pp_hwmgr *hwmgr)
hwmgr            1575 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 					     get_powerplay_table(hwmgr);
hwmgr            1577 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 				    get_vce_state_table(hwmgr, table);
hwmgr            1585 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c static int get_vce_state_table_entry(struct pp_hwmgr *hwmgr,
hwmgr            1591 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table = get_powerplay_table(hwmgr);
hwmgr            1593 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	const ATOM_PPLIB_VCE_State_Table *vce_state_table = get_vce_state_table(hwmgr, powerplay_table);
hwmgr            1595 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	unsigned short vce_clock_info_array_offset = get_vce_clock_info_array_offset(hwmgr, powerplay_table);
hwmgr            1619 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c static int pp_tables_initialize(struct pp_hwmgr *hwmgr)
hwmgr            1624 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	if (hwmgr->chip_id == CHIP_RAVEN)
hwmgr            1627 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->need_pp_table_upload = true;
hwmgr            1629 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	powerplay_table = get_powerplay_table(hwmgr);
hwmgr            1631 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	result = init_powerplay_tables(hwmgr, powerplay_table);
hwmgr            1636 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	result = set_platform_caps(hwmgr,
hwmgr            1642 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	result = init_thermal_controller(hwmgr, powerplay_table);
hwmgr            1647 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	result = init_overdrive_limits(hwmgr, powerplay_table);
hwmgr            1652 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	result = init_clock_voltage_dependency(hwmgr,
hwmgr            1658 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	result = init_dpm2_parameters(hwmgr, powerplay_table);
hwmgr            1663 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	result = init_phase_shedding_table(hwmgr, powerplay_table);
hwmgr            1671 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c static int pp_tables_uninitialize(struct pp_hwmgr *hwmgr)
hwmgr            1673 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	if (hwmgr->chip_id == CHIP_RAVEN)
hwmgr            1676 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	kfree(hwmgr->dyn_state.vddc_dependency_on_sclk);
hwmgr            1677 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->dyn_state.vddc_dependency_on_sclk = NULL;
hwmgr            1679 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	kfree(hwmgr->dyn_state.vddci_dependency_on_mclk);
hwmgr            1680 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->dyn_state.vddci_dependency_on_mclk = NULL;
hwmgr            1682 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	kfree(hwmgr->dyn_state.vddc_dependency_on_mclk);
hwmgr            1683 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->dyn_state.vddc_dependency_on_mclk = NULL;
hwmgr            1685 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	kfree(hwmgr->dyn_state.mvdd_dependency_on_mclk);
hwmgr            1686 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->dyn_state.mvdd_dependency_on_mclk = NULL;
hwmgr            1688 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	kfree(hwmgr->dyn_state.valid_mclk_values);
hwmgr            1689 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->dyn_state.valid_mclk_values = NULL;
hwmgr            1691 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	kfree(hwmgr->dyn_state.valid_sclk_values);
hwmgr            1692 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->dyn_state.valid_sclk_values = NULL;
hwmgr            1694 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	kfree(hwmgr->dyn_state.cac_leakage_table);
hwmgr            1695 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->dyn_state.cac_leakage_table = NULL;
hwmgr            1697 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	kfree(hwmgr->dyn_state.vddc_phase_shed_limits_table);
hwmgr            1698 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->dyn_state.vddc_phase_shed_limits_table = NULL;
hwmgr            1700 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	kfree(hwmgr->dyn_state.vce_clock_voltage_dependency_table);
hwmgr            1701 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->dyn_state.vce_clock_voltage_dependency_table = NULL;
hwmgr            1703 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	kfree(hwmgr->dyn_state.uvd_clock_voltage_dependency_table);
hwmgr            1704 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->dyn_state.uvd_clock_voltage_dependency_table = NULL;
hwmgr            1706 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	kfree(hwmgr->dyn_state.samu_clock_voltage_dependency_table);
hwmgr            1707 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->dyn_state.samu_clock_voltage_dependency_table = NULL;
hwmgr            1709 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	kfree(hwmgr->dyn_state.acp_clock_voltage_dependency_table);
hwmgr            1710 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->dyn_state.acp_clock_voltage_dependency_table = NULL;
hwmgr            1712 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	kfree(hwmgr->dyn_state.cac_dtp_table);
hwmgr            1713 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->dyn_state.cac_dtp_table = NULL;
hwmgr            1715 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	kfree(hwmgr->dyn_state.ppm_parameter_table);
hwmgr            1716 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->dyn_state.ppm_parameter_table = NULL;
hwmgr            1718 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	kfree(hwmgr->dyn_state.vdd_gfx_dependency_on_sclk);
hwmgr            1719 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	hwmgr->dyn_state.vdd_gfx_dependency_on_sclk = NULL;
hwmgr              34 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.h typedef int (*pp_tables_hw_clock_info_callback)(struct pp_hwmgr *hwmgr,
hwmgr              39 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.h int pp_tables_get_num_of_entries(struct pp_hwmgr *hwmgr,
hwmgr              42 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.h int pp_tables_get_entry(struct pp_hwmgr *hwmgr,
hwmgr              47 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.h int pp_tables_get_response_times(struct pp_hwmgr *hwmgr,
hwmgr              56 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
hwmgr              59 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
hwmgr              84 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	smum_send_msg_to_smc_with_parameter(hwmgr, msg, clk_freq);
hwmgr             106 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
hwmgr             108 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
hwmgr             118 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             121 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             124 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             129 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_construct_max_power_limits_table(struct pp_hwmgr *hwmgr,
hwmgr             136 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 							struct pp_hwmgr *hwmgr)
hwmgr             165 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
hwmgr             170 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_get_system_info_data(struct pp_hwmgr *hwmgr)
hwmgr             172 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)hwmgr->backend;
hwmgr             180 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	smu10_construct_max_power_limits_table (hwmgr,
hwmgr             181 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 				    &hwmgr->dyn_state.max_clock_voltage_on_ac);
hwmgr             183 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	smu10_init_dynamic_state_adjustment_rule_settings(hwmgr);
hwmgr             188 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_construct_boot_state(struct pp_hwmgr *hwmgr)
hwmgr             193 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_set_clock_limit(struct pp_hwmgr *hwmgr, const void *input)
hwmgr             198 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
hwmgr             202 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	PP_ASSERT_WITH_CODE(!smu10_display_clock_voltage_request(hwmgr, &clock_req),
hwmgr             208 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_set_min_deep_sleep_dcefclk(struct pp_hwmgr *hwmgr, uint32_t clock)
hwmgr             210 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
hwmgr             215 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             222 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_set_hard_min_dcefclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock)
hwmgr             224 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
hwmgr             229 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             236 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_set_hard_min_fclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock)
hwmgr             238 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
hwmgr             243 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             250 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_set_active_display_count(struct pp_hwmgr *hwmgr, uint32_t count)
hwmgr             252 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
hwmgr             256 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             264 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
hwmgr             266 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	return smu10_set_clock_limit(hwmgr, input);
hwmgr             269 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_init_power_gate_state(struct pp_hwmgr *hwmgr)
hwmgr             271 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
hwmgr             272 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             279 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		return smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             287 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_setup_asic_task(struct pp_hwmgr *hwmgr)
hwmgr             289 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	return smu10_init_power_gate_state(hwmgr);
hwmgr             292 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_reset_cc6_data(struct pp_hwmgr *hwmgr)
hwmgr             294 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
hwmgr             304 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_power_off_asic(struct pp_hwmgr *hwmgr)
hwmgr             306 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	return smu10_reset_cc6_data(hwmgr);
hwmgr             309 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static bool smu10_is_gfx_on(struct pp_hwmgr *hwmgr)
hwmgr             312 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             322 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_disable_gfx_off(struct pp_hwmgr *hwmgr)
hwmgr             324 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             327 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableGfxOff);
hwmgr             330 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		while (!smu10_is_gfx_on(hwmgr))
hwmgr             337 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
hwmgr             342 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_enable_gfx_off(struct pp_hwmgr *hwmgr)
hwmgr             344 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             347 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableGfxOff);
hwmgr             352 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
hwmgr             357 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable)
hwmgr             360 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		return smu10_enable_gfx_off(hwmgr);
hwmgr             362 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		return smu10_disable_gfx_off(hwmgr);
hwmgr             365 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
hwmgr             409 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_get_clock_voltage_dependency_table(struct pp_hwmgr *hwmgr,
hwmgr             436 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_populate_clock_table(struct pp_hwmgr *hwmgr)
hwmgr             440 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
hwmgr             444 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	result = smum_smc_table_manager(hwmgr, (uint8_t *)table, SMU10_CLOCKTABLE, true);
hwmgr             451 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dcefclk,
hwmgr             454 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_socclk,
hwmgr             457 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_fclk,
hwmgr             460 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_mclk,
hwmgr             464 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dcefclk,
hwmgr             467 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_socclk,
hwmgr             470 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_fclk,
hwmgr             474 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dispclk,
hwmgr             477 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dppclk,
hwmgr             479 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_phyclk,
hwmgr             482 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency);
hwmgr             483 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	result = smum_get_argument(hwmgr);
hwmgr             486 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency);
hwmgr             487 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	result = smum_get_argument(hwmgr);
hwmgr             493 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
hwmgr             502 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	hwmgr->backend = data;
hwmgr             504 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	result = smu10_initialize_dpm_defaults(hwmgr);
hwmgr             510 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	smu10_populate_clock_table(hwmgr);
hwmgr             512 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	result = smu10_get_system_info_data(hwmgr);
hwmgr             518 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	smu10_construct_boot_state(hwmgr);
hwmgr             520 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
hwmgr             523 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	hwmgr->platform_descriptor.hardwarePerformanceLevels =
hwmgr             526 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	hwmgr->platform_descriptor.vbiosInterruptId = 0;
hwmgr             528 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	hwmgr->platform_descriptor.clockStep.engineClock = 500;
hwmgr             530 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	hwmgr->platform_descriptor.clockStep.memoryClock = 500;
hwmgr             532 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
hwmgr             534 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	hwmgr->pstate_sclk = SMU10_UMD_PSTATE_GFXCLK * 100;
hwmgr             535 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	hwmgr->pstate_mclk = SMU10_UMD_PSTATE_FCLK * 100;
hwmgr             540 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
hwmgr             542 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
hwmgr             558 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
hwmgr             559 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
hwmgr             561 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	kfree(hwmgr->backend);
hwmgr             562 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	hwmgr->backend = NULL;
hwmgr             567 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
hwmgr             570 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	struct smu10_hwmgr *data = hwmgr->backend;
hwmgr             571 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	uint32_t min_sclk = hwmgr->display_config->min_core_set_clock;
hwmgr             572 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	uint32_t min_mclk = hwmgr->display_config->min_mem_set_clock/100;
hwmgr             574 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	if (hwmgr->smu_version < 0x1E3700) {
hwmgr             589 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             592 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             595 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             598 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             602 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             605 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             608 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             611 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             616 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             619 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             624 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             627 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             632 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             635 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             638 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             641 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             645 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             648 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             651 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             654 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             659 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             662 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             664 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 						hwmgr->display_config->num_display > 3 ?
hwmgr             668 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             671 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             675 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             678 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             681 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             684 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             689 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             692 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             695 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             698 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             710 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static uint32_t smu10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
hwmgr             714 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	if (hwmgr == NULL)
hwmgr             717 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	data = (struct smu10_hwmgr *)(hwmgr->backend);
hwmgr             726 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static uint32_t smu10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
hwmgr             730 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	if (hwmgr == NULL)
hwmgr             733 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	data = (struct smu10_hwmgr *)(hwmgr->backend);
hwmgr             741 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
hwmgr             748 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 						     struct pp_hwmgr *hwmgr,
hwmgr             760 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
hwmgr             768 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_dpm_get_num_of_pp_table_entries(struct pp_hwmgr *hwmgr)
hwmgr             773 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	result = pp_tables_get_num_of_entries(hwmgr, &ret);
hwmgr             778 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr,
hwmgr             788 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	result = pp_tables_get_entry(hwmgr, entry, ps,
hwmgr             797 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_get_power_state_size(struct pp_hwmgr *hwmgr)
hwmgr             802 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_set_cpu_power_state(struct pp_hwmgr *hwmgr)
hwmgr             808 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time,
hwmgr             811 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	struct smu10_hwmgr *data = (struct smu10_hwmgr *)(hwmgr->backend);
hwmgr             824 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_get_dal_power_level(struct pp_hwmgr *hwmgr,
hwmgr             830 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_force_clock_level(struct pp_hwmgr *hwmgr,
hwmgr             833 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	struct smu10_hwmgr *data = hwmgr->backend;
hwmgr             848 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             854 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             865 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             869 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             881 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_print_clock_levels(struct pp_hwmgr *hwmgr,
hwmgr             884 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	struct smu10_hwmgr *data = (struct smu10_hwmgr *)(hwmgr->backend);
hwmgr             891 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency);
hwmgr             892 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		now = smum_get_argument(hwmgr);
hwmgr             913 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency);
hwmgr             914 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		now = smum_get_argument(hwmgr);
hwmgr             930 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
hwmgr             936 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	if (level == NULL || hwmgr == NULL || state == NULL)
hwmgr             939 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	data = (struct smu10_hwmgr *)(hwmgr->backend);
hwmgr             956 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr,
hwmgr             974 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static uint32_t smu10_get_mem_latency(struct pp_hwmgr *hwmgr,
hwmgr             986 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
hwmgr             991 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
hwmgr            1033 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 				smu10_get_mem_latency(hwmgr,
hwmgr            1043 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
hwmgr            1048 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
hwmgr            1095 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)
hwmgr            1101 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_thermal_get_temperature(struct pp_hwmgr *hwmgr)
hwmgr            1103 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr            1116 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
hwmgr            1119 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
hwmgr            1125 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency);
hwmgr            1126 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		sclk = smum_get_argument(hwmgr);
hwmgr            1132 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency);
hwmgr            1133 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		mclk = smum_get_argument(hwmgr);
hwmgr            1139 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		*((uint32_t *)value) = smu10_thermal_get_temperature(hwmgr);
hwmgr            1153 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
hwmgr            1156 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	struct smu10_hwmgr *data = hwmgr->backend;
hwmgr            1162 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	smum_smc_table_manager(hwmgr, (uint8_t *)table, (uint16_t)SMU10_WMTABLE, false);
hwmgr            1167 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_smus_notify_pwe(struct pp_hwmgr *hwmgr)
hwmgr            1170 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SetRccPfcPmeRestoreRegister);
hwmgr            1173 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_powergate_mmhub(struct pp_hwmgr *hwmgr)
hwmgr            1175 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerGateMmHub);
hwmgr            1178 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_powergate_sdma(struct pp_hwmgr *hwmgr, bool gate)
hwmgr            1181 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerDownSdma);
hwmgr            1183 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerUpSdma);
hwmgr            1186 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate)
hwmgr            1188 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
hwmgr            1191 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		amdgpu_device_ip_set_powergating_state(hwmgr->adev,
hwmgr            1194 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            1198 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            1200 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		amdgpu_device_ip_set_powergating_state(hwmgr->adev,
hwmgr            1235 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
hwmgr            1268 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 			i, profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ",
hwmgr            1275 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static bool smu10_is_raven1_refresh(struct pp_hwmgr *hwmgr)
hwmgr            1277 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr            1280 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	    (hwmgr->smu_version >= 0x41e2b))
hwmgr            1286 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
hwmgr            1295 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	if (hwmgr->power_profile_mode == input[size])
hwmgr            1302 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	    smu10_is_raven1_refresh(hwmgr) &&
hwmgr            1303 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	    !hwmgr->gfxoff_state_changed_by_workload) {
hwmgr            1304 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smu10_gfx_off_control(hwmgr, false);
hwmgr            1305 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		hwmgr->gfxoff_state_changed_by_workload = true;
hwmgr            1307 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ActiveProcessNotify,
hwmgr            1310 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		hwmgr->power_profile_mode = input[size];
hwmgr            1311 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	if (workload_type && hwmgr->gfxoff_state_changed_by_workload) {
hwmgr            1312 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		smu10_gfx_off_control(hwmgr, true);
hwmgr            1313 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 		hwmgr->gfxoff_state_changed_by_workload = false;
hwmgr            1319 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c static int smu10_asic_reset(struct pp_hwmgr *hwmgr, enum SMU_ASIC_RESET_MODE mode)
hwmgr            1321 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	return smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            1372 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c int smu10_init_function_pointers(struct pp_hwmgr *hwmgr)
hwmgr            1374 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	hwmgr->hwmgr_func = &smu10_hwmgr_funcs;
hwmgr            1375 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c 	hwmgr->pptable_func = &pptable_funcs;
hwmgr             306 drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h int smu10_init_function_pointers(struct pp_hwmgr *hwmgr);
hwmgr              28 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c static int smu7_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
hwmgr              30 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 	return smum_send_msg_to_smc(hwmgr, enable ?
hwmgr              35 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c static int smu7_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
hwmgr              37 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 	return smum_send_msg_to_smc(hwmgr, enable ?
hwmgr              42 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c static int smu7_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
hwmgr              45 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 		smum_update_smc_table(hwmgr, SMU_UVD_TABLE);
hwmgr              46 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 	return smu7_enable_disable_uvd_dpm(hwmgr, !bgate);
hwmgr              49 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c static int smu7_update_vce_dpm(struct pp_hwmgr *hwmgr, bool bgate)
hwmgr              52 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 		smum_update_smc_table(hwmgr, SMU_VCE_TABLE);
hwmgr              53 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 	return smu7_enable_disable_vce_dpm(hwmgr, !bgate);
hwmgr              56 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c int smu7_powerdown_uvd(struct pp_hwmgr *hwmgr)
hwmgr              58 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 	if (phm_cf_want_uvd_power_gating(hwmgr))
hwmgr              59 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 		return smum_send_msg_to_smc(hwmgr,
hwmgr              64 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c static int smu7_powerup_uvd(struct pp_hwmgr *hwmgr)
hwmgr              66 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 	if (phm_cf_want_uvd_power_gating(hwmgr)) {
hwmgr              67 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr              69 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 			return smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr              72 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 			return smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr              80 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c static int smu7_powerdown_vce(struct pp_hwmgr *hwmgr)
hwmgr              82 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 	if (phm_cf_want_vce_power_gating(hwmgr))
hwmgr              83 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 		return smum_send_msg_to_smc(hwmgr,
hwmgr              88 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c static int smu7_powerup_vce(struct pp_hwmgr *hwmgr)
hwmgr              90 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 	if (phm_cf_want_vce_power_gating(hwmgr))
hwmgr              91 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 		return smum_send_msg_to_smc(hwmgr,
hwmgr              96 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c int smu7_disable_clock_power_gating(struct pp_hwmgr *hwmgr)
hwmgr              98 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             103 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 	smu7_powerup_uvd(hwmgr);
hwmgr             104 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 	smu7_powerup_vce(hwmgr);
hwmgr             109 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c void smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
hwmgr             111 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             116 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 		amdgpu_device_ip_set_powergating_state(hwmgr->adev,
hwmgr             119 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 		amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
hwmgr             122 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 		smu7_update_uvd_dpm(hwmgr, true);
hwmgr             123 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 		smu7_powerdown_uvd(hwmgr);
hwmgr             125 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 		smu7_powerup_uvd(hwmgr);
hwmgr             126 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 		amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
hwmgr             129 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 		amdgpu_device_ip_set_powergating_state(hwmgr->adev,
hwmgr             132 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 		smu7_update_uvd_dpm(hwmgr, false);
hwmgr             137 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c void smu7_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
hwmgr             139 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             144 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 		amdgpu_device_ip_set_powergating_state(hwmgr->adev,
hwmgr             147 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 		amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
hwmgr             150 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 		smu7_update_vce_dpm(hwmgr, true);
hwmgr             151 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 		smu7_powerdown_vce(hwmgr);
hwmgr             153 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 		smu7_powerup_vce(hwmgr);
hwmgr             154 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 		amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
hwmgr             157 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 		amdgpu_device_ip_set_powergating_state(hwmgr->adev,
hwmgr             160 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 		smu7_update_vce_dpm(hwmgr, false);
hwmgr             164 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
hwmgr             170 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 	if (!(hwmgr->feature_mask & PP_ENABLE_GFX_CG_THRU_SMU))
hwmgr             184 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 						hwmgr, msg, value))
hwmgr             194 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 						hwmgr, msg, value))
hwmgr             207 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 						hwmgr, msg, value))
hwmgr             218 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 						hwmgr, msg, value))
hwmgr             231 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 						hwmgr, msg, value))
hwmgr             244 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 						hwmgr, msg, value))
hwmgr             258 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 						hwmgr, msg, value))
hwmgr             278 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 						hwmgr, msg, value))
hwmgr             288 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 						hwmgr, msg, value))
hwmgr             301 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 						hwmgr, msg, value))
hwmgr             312 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 						hwmgr, msg, value))
hwmgr             325 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 						hwmgr, msg, value))
hwmgr             335 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 						hwmgr, msg, value))
hwmgr             348 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 						hwmgr, msg, value))
hwmgr             359 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 						hwmgr, msg, value))
hwmgr             372 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 						hwmgr, msg, value))
hwmgr             383 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 						hwmgr, msg, value))
hwmgr             396 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 						hwmgr, msg, value))
hwmgr             419 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c int smu7_powergate_gfx(struct pp_hwmgr *hwmgr, bool enable)
hwmgr             421 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             424 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 		return smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             428 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.c 		return smum_send_msg_to_smc(hwmgr,
hwmgr              29 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h void smu7_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate);
hwmgr              30 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h void smu7_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate);
hwmgr              31 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h int smu7_powerdown_uvd(struct pp_hwmgr *hwmgr);
hwmgr              32 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h int smu7_powergate_acp(struct pp_hwmgr *hwmgr, bool bgate);
hwmgr              33 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h int smu7_disable_clock_power_gating(struct pp_hwmgr *hwmgr);
hwmgr              34 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h int smu7_update_clock_gatings(struct pp_hwmgr *hwmgr,
hwmgr              36 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_clockpowergating.h int smu7_powergate_gfx(struct pp_hwmgr *hwmgr, bool enable);
hwmgr             109 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
hwmgr             138 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_get_mc_microcode_version(struct pp_hwmgr *hwmgr)
hwmgr             140 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F);
hwmgr             142 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
hwmgr             147 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static uint16_t smu7_get_current_pcie_speed(struct pp_hwmgr *hwmgr)
hwmgr             152 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE,
hwmgr             158 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
hwmgr             163 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
hwmgr             178 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr)
hwmgr             180 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (hwmgr->chip_id == CHIP_VEGAM) {
hwmgr             181 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device,
hwmgr             183 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device,
hwmgr             187 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (hwmgr->feature_mask & PP_SMC_VOLTAGE_CONTROL_MASK)
hwmgr             188 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Voltage_Cntl_Enable);
hwmgr             198 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static bool smu7_voltage_control(const struct pp_hwmgr *hwmgr)
hwmgr             201 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			(const struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             212 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_enable_voltage_control(struct pp_hwmgr *hwmgr)
hwmgr             215 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             250 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_construct_voltage_tables(struct pp_hwmgr *hwmgr)
hwmgr             252 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             254 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			(struct phm_ppt_v1_information *)hwmgr->pptable;
hwmgr             259 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		result = atomctrl_get_voltage_table_v3(hwmgr,
hwmgr             266 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		if (hwmgr->pp_table_version == PP_TABLE_V1)
hwmgr             269 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		else if (hwmgr->pp_table_version == PP_TABLE_V0)
hwmgr             271 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 					hwmgr->dyn_state.mvdd_dependency_on_mclk);
hwmgr             279 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		result = atomctrl_get_voltage_table_v3(hwmgr,
hwmgr             286 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		if (hwmgr->pp_table_version == PP_TABLE_V1)
hwmgr             289 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		else if (hwmgr->pp_table_version == PP_TABLE_V0)
hwmgr             291 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 					hwmgr->dyn_state.vddci_dependency_on_mclk);
hwmgr             307 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		result = atomctrl_get_voltage_table_v3(hwmgr,
hwmgr             314 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		if (hwmgr->pp_table_version == PP_TABLE_V0)
hwmgr             316 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 					hwmgr->dyn_state.vddc_dependency_on_mclk);
hwmgr             317 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		else if (hwmgr->pp_table_version == PP_TABLE_V1)
hwmgr             325 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDC);
hwmgr             332 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDGFX);
hwmgr             339 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDCI);
hwmgr             346 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_MVDD);
hwmgr             363 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 							struct pp_hwmgr *hwmgr)
hwmgr             365 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             368 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             372 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             385 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_enable_display_gap(struct pp_hwmgr *hwmgr)
hwmgr             388 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             397 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             409 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_program_voting_clients(struct pp_hwmgr *hwmgr)
hwmgr             411 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             415 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             417 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             421 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             427 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_clear_voting_clients(struct pp_hwmgr *hwmgr)
hwmgr             432 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             434 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             438 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             447 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr,
hwmgr             457 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
hwmgr             458 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
hwmgr             459 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
hwmgr             462 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		mc_arb_dram_timing  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1);
hwmgr             463 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1);
hwmgr             464 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1);
hwmgr             472 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing);
hwmgr             473 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
hwmgr             474 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time);
hwmgr             477 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
hwmgr             478 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
hwmgr             479 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time);
hwmgr             485 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG);
hwmgr             487 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config);
hwmgr             488 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest);
hwmgr             493 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_reset_to_default(struct pp_hwmgr *hwmgr)
hwmgr             495 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ResetToDefaults);
hwmgr             505 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr)
hwmgr             507 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	return smu7_copy_and_switch_arb_sets(hwmgr,
hwmgr             511 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_force_switch_to_arbf0(struct pp_hwmgr *hwmgr)
hwmgr             515 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp = (cgs_read_ind_register(hwmgr->device,
hwmgr             522 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	return smu7_copy_and_switch_arb_sets(hwmgr,
hwmgr             526 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
hwmgr             528 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             531 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr             553 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_LINK);
hwmgr             572 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		smum_update_smc_table(hwmgr, SMU_BIF_TABLE);
hwmgr             609 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (hwmgr->chip_family == AMDGPU_FAMILY_CI) {
hwmgr             626 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_reset_dpm_tables(struct pp_hwmgr *hwmgr)
hwmgr             628 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             634 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 				smum_get_mac_definition(hwmgr,
hwmgr             639 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			smum_get_mac_definition(hwmgr,
hwmgr             644 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 				smum_get_mac_definition(hwmgr,
hwmgr             649 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			smum_get_mac_definition(hwmgr,
hwmgr             654 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 				smum_get_mac_definition(hwmgr,
hwmgr             668 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_setup_dpm_tables_v0(struct pp_hwmgr *hwmgr)
hwmgr             670 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             672 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		hwmgr->dyn_state.vddc_dependency_on_sclk;
hwmgr             674 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		hwmgr->dyn_state.vddc_dependency_on_mclk;
hwmgr             676 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		hwmgr->dyn_state.cac_leakage_table;
hwmgr             726 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	allowed_vdd_mclk_table = hwmgr->dyn_state.vddci_dependency_on_mclk;
hwmgr             737 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	allowed_vdd_mclk_table = hwmgr->dyn_state.mvdd_dependency_on_mclk;
hwmgr             754 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_setup_dpm_tables_v1(struct pp_hwmgr *hwmgr)
hwmgr             756 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             758 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr             798 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0)
hwmgr             799 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		hwmgr->platform_descriptor.overdriveLimit.engineClock = dep_sclk_table->entries[i-1].clk;
hwmgr             814 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (hwmgr->platform_descriptor.overdriveLimit.memoryClock == 0)
hwmgr             815 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		hwmgr->platform_descriptor.overdriveLimit.memoryClock = dep_mclk_table->entries[i-1].clk;
hwmgr             819 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_odn_initial_default_setting(struct pp_hwmgr *hwmgr)
hwmgr             821 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             824 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr             864 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static void smu7_setup_voltage_range_from_vbios(struct pp_hwmgr *hwmgr)
hwmgr             866 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             869 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr             878 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	atomctrl_get_voltage_range(hwmgr, &max_vddc, &min_vddc);
hwmgr             892 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static void smu7_check_dpm_table_updated(struct pp_hwmgr *hwmgr)
hwmgr             894 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             897 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr             946 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
hwmgr             948 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             950 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	smu7_reset_dpm_tables(hwmgr);
hwmgr             952 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (hwmgr->pp_table_version == PP_TABLE_V1)
hwmgr             953 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		smu7_setup_dpm_tables_v1(hwmgr);
hwmgr             954 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	else if (hwmgr->pp_table_version == PP_TABLE_V0)
hwmgr             955 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		smu7_setup_dpm_tables_v0(hwmgr);
hwmgr             957 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	smu7_setup_default_pcie_table(hwmgr);
hwmgr             964 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (hwmgr->od_enabled) {
hwmgr             966 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			smu7_check_dpm_table_updated(hwmgr);
hwmgr             968 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			smu7_setup_voltage_range_from_vbios(hwmgr);
hwmgr             969 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			smu7_odn_initial_default_setting(hwmgr);
hwmgr             975 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)
hwmgr             978 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr             980 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		return smum_send_msg_to_smc(hwmgr,
hwmgr             986 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_enable_sclk_control(struct pp_hwmgr *hwmgr)
hwmgr             988 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
hwmgr             993 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_enable_ulv(struct pp_hwmgr *hwmgr)
hwmgr             995 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             998 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableULV);
hwmgr            1003 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_disable_ulv(struct pp_hwmgr *hwmgr)
hwmgr            1005 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1008 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableULV);
hwmgr            1013 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
hwmgr            1015 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            1017 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		if (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MASTER_DeepSleep_ON))
hwmgr            1022 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		if (smum_send_msg_to_smc(hwmgr,
hwmgr            1033 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
hwmgr            1035 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            1037 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		if (smum_send_msg_to_smc(hwmgr,
hwmgr            1048 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_disable_sclk_vce_handshake(struct pp_hwmgr *hwmgr)
hwmgr            1050 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1053 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 				+ smum_get_offsetof(hwmgr,
hwmgr            1056 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	soft_register_value = cgs_read_ind_register(hwmgr->device,
hwmgr            1059 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
hwmgr            1064 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_disable_handshake_uvd(struct pp_hwmgr *hwmgr)
hwmgr            1066 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1069 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 				+ smum_get_offsetof(hwmgr,
hwmgr            1072 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	soft_register_value = cgs_read_ind_register(hwmgr->device,
hwmgr            1074 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	soft_register_value |= smum_get_mac_definition(hwmgr,
hwmgr            1076 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
hwmgr            1081 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
hwmgr            1083 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1087 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		if (hwmgr->chip_id == CHIP_VEGAM)
hwmgr            1088 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			smu7_disable_sclk_vce_handshake(hwmgr);
hwmgr            1091 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		(0 == smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DPM_Enable)),
hwmgr            1098 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		if (!(hwmgr->feature_mask & PP_UVD_HANDSHAKE_MASK))
hwmgr            1099 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			smu7_disable_handshake_uvd(hwmgr);
hwmgr            1102 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 				(0 == smum_send_msg_to_smc(hwmgr,
hwmgr            1107 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		if (hwmgr->chip_family != CHIP_VEGAM)
hwmgr            1108 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
hwmgr            1111 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		if (hwmgr->chip_family == AMDGPU_FAMILY_CI) {
hwmgr            1112 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d30, 0x5);
hwmgr            1113 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d3c, 0x5);
hwmgr            1114 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d80, 0x100005);
hwmgr            1116 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d30, 0x400005);
hwmgr            1117 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d3c, 0x400005);
hwmgr            1118 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d80, 0x500005);
hwmgr            1120 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5);
hwmgr            1121 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5);
hwmgr            1122 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005);
hwmgr            1124 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			if (hwmgr->chip_id == CHIP_VEGAM) {
hwmgr            1125 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 				cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400009);
hwmgr            1126 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 				cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400009);
hwmgr            1128 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 				cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005);
hwmgr            1129 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 				cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005);
hwmgr            1131 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005);
hwmgr            1138 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_start_dpm(struct pp_hwmgr *hwmgr)
hwmgr            1140 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1144 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
hwmgr            1149 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
hwmgr            1154 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
hwmgr            1156 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			smum_get_offsetof(hwmgr, SMU_SoftRegisters,
hwmgr            1158 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE,
hwmgr            1161 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (hwmgr->chip_family == AMDGPU_FAMILY_CI)
hwmgr            1162 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		cgs_write_register(hwmgr->device, 0x1488,
hwmgr            1163 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			(cgs_read_register(hwmgr->device, 0x1488) & ~0x1));
hwmgr            1165 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (smu7_enable_sclk_mclk_dpm(hwmgr)) {
hwmgr            1173 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 				(0 == smum_send_msg_to_smc(hwmgr,
hwmgr            1179 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            1181 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr,
hwmgr            1190 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
hwmgr            1192 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1196 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
hwmgr            1199 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DPM_Disable);
hwmgr            1204 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
hwmgr            1207 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_Disable);
hwmgr            1213 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_stop_dpm(struct pp_hwmgr *hwmgr)
hwmgr            1215 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1218 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
hwmgr            1221 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
hwmgr            1227 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 				(smum_send_msg_to_smc(hwmgr,
hwmgr            1233 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	smu7_disable_sclk_mclk_dpm(hwmgr);
hwmgr            1235 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
hwmgr            1239 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Voltage_Cntl_Disable);
hwmgr            1244 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static void smu7_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources)
hwmgr            1273 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL,
hwmgr            1275 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
hwmgr            1277 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 				!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            1280 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT,
hwmgr            1284 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_enable_auto_throttle_source(struct pp_hwmgr *hwmgr,
hwmgr            1287 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1291 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		smu7_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
hwmgr            1296 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
hwmgr            1298 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	return smu7_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
hwmgr            1301 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_disable_auto_throttle_source(struct pp_hwmgr *hwmgr,
hwmgr            1304 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1308 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		smu7_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources);
hwmgr            1313 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_disable_thermal_auto_throttle(struct pp_hwmgr *hwmgr)
hwmgr            1315 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	return smu7_disable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal);
hwmgr            1318 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_pcie_performance_request(struct pp_hwmgr *hwmgr)
hwmgr            1320 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1326 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
hwmgr            1331 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (smu7_voltage_control(hwmgr)) {
hwmgr            1332 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		tmp_result = smu7_enable_voltage_control(hwmgr);
hwmgr            1337 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		tmp_result = smu7_construct_voltage_tables(hwmgr);
hwmgr            1342 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	smum_initialize_mc_reg_table(hwmgr);
hwmgr            1344 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            1346 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr            1349 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            1351 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr            1354 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp_result = smu7_program_static_screen_threshold_parameters(hwmgr);
hwmgr            1359 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp_result = smu7_enable_display_gap(hwmgr);
hwmgr            1363 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp_result = smu7_program_voting_clients(hwmgr);
hwmgr            1367 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp_result = smum_process_firmware_header(hwmgr);
hwmgr            1371 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (hwmgr->chip_id != CHIP_VEGAM) {
hwmgr            1372 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		tmp_result = smu7_initial_switch_from_arbf0_to_f1(hwmgr);
hwmgr            1378 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	result = smu7_setup_default_dpm_tables(hwmgr);
hwmgr            1382 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp_result = smum_init_smc_table(hwmgr);
hwmgr            1386 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp_result = smu7_enable_vrhot_gpio_interrupt(hwmgr);
hwmgr            1390 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	smum_send_msg_to_smc(hwmgr, (PPSMC_Msg)PPSMC_NoDisplay);
hwmgr            1392 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp_result = smu7_enable_sclk_control(hwmgr);
hwmgr            1396 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp_result = smu7_enable_smc_voltage_controller(hwmgr);
hwmgr            1400 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp_result = smu7_enable_ulv(hwmgr);
hwmgr            1404 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp_result = smu7_enable_deep_sleep_master_switch(hwmgr);
hwmgr            1408 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp_result = smu7_enable_didt_config(hwmgr);
hwmgr            1412 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp_result = smu7_start_dpm(hwmgr);
hwmgr            1416 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp_result = smu7_enable_smc_cac(hwmgr);
hwmgr            1420 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp_result = smu7_enable_power_containment(hwmgr);
hwmgr            1424 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp_result = smu7_power_control_set_level(hwmgr);
hwmgr            1428 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp_result = smu7_enable_thermal_auto_throttle(hwmgr);
hwmgr            1432 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp_result = smu7_pcie_performance_request(hwmgr);
hwmgr            1439 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)
hwmgr            1441 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (!hwmgr->avfs_supported)
hwmgr            1445 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		if (!PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
hwmgr            1448 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 					hwmgr, PPSMC_MSG_EnableAvfs),
hwmgr            1452 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	} else if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
hwmgr            1455 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 				hwmgr, PPSMC_MSG_DisableAvfs),
hwmgr            1463 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_update_avfs(struct pp_hwmgr *hwmgr)
hwmgr            1465 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1467 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (!hwmgr->avfs_supported)
hwmgr            1471 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		smu7_avfs_control(hwmgr, false);
hwmgr            1473 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		smu7_avfs_control(hwmgr, false);
hwmgr            1474 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		smu7_avfs_control(hwmgr, true);
hwmgr            1476 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		smu7_avfs_control(hwmgr, true);
hwmgr            1482 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c int smu7_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
hwmgr            1486 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            1488 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr            1491 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp_result = smu7_disable_power_containment(hwmgr);
hwmgr            1495 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp_result = smu7_disable_smc_cac(hwmgr);
hwmgr            1499 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp_result = smu7_disable_didt_config(hwmgr);
hwmgr            1503 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr            1505 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr            1508 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp_result = smu7_disable_thermal_auto_throttle(hwmgr);
hwmgr            1512 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp_result = smu7_avfs_control(hwmgr, false);
hwmgr            1516 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp_result = smu7_stop_dpm(hwmgr);
hwmgr            1520 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp_result = smu7_disable_deep_sleep_master_switch(hwmgr);
hwmgr            1524 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp_result = smu7_disable_ulv(hwmgr);
hwmgr            1528 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp_result = smu7_clear_voting_clients(hwmgr);
hwmgr            1532 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp_result = smu7_reset_to_default(hwmgr);
hwmgr            1536 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp_result = smu7_force_switch_to_arbf0(hwmgr);
hwmgr            1543 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c int smu7_reset_asic_tasks(struct pp_hwmgr *hwmgr)
hwmgr            1549 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
hwmgr            1551 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1553 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            1554 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr            1570 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	data->mclk_dpm_key_disabled = hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true;
hwmgr            1571 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	data->sclk_dpm_key_disabled = hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true;
hwmgr            1572 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	data->pcie_dpm_key_disabled = hwmgr->feature_mask & PP_PCIE_DPM_MASK ? false : true;
hwmgr            1580 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	data->ulv_supported = hwmgr->feature_mask & PP_ULV_MASK ? true : false;
hwmgr            1589 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D];
hwmgr            1590 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
hwmgr            1591 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
hwmgr            1593 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (hwmgr->chip_id == CHIP_POLARIS12 || hwmgr->is_kicker) {
hwmgr            1596 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		atomctrl_get_svi2_info(hwmgr, VOLTAGE_TYPE_VDDC, &tmp1, &tmp2,
hwmgr            1600 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	} else if (hwmgr->chip_family == AMDGPU_FAMILY_CI) {
hwmgr            1606 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (hwmgr->chip_id  == CHIP_HAWAII) {
hwmgr            1617 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
hwmgr            1620 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
hwmgr            1624 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            1626 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
hwmgr            1632 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            1634 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
hwmgr            1637 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
hwmgr            1643 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr            1646 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            1648 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
hwmgr            1651 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
hwmgr            1657 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr            1661 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr            1664 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if ((hwmgr->pp_table_version != PP_TABLE_V0) && (hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK)
hwmgr            1666 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr            1680 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr            1683 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr            1693 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_get_evv_voltages(struct pp_hwmgr *hwmgr)
hwmgr            1695 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1702 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			(struct phm_ppt_v1_information *)hwmgr->pptable;
hwmgr            1710 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			if ((hwmgr->pp_table_version == PP_TABLE_V1)
hwmgr            1711 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			    && !phm_get_sclk_for_voltage_evv(hwmgr,
hwmgr            1713 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 				if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            1726 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 				    (hwmgr, VOLTAGE_TYPE_VDDGFX, sclk,
hwmgr            1742 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			if ((hwmgr->pp_table_version == PP_TABLE_V0)
hwmgr            1743 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 				|| !phm_get_sclk_for_voltage_evv(hwmgr,
hwmgr            1745 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 				if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            1760 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 				if (phm_get_voltage_evv_on_sclk(hwmgr,
hwmgr            1790 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static void smu7_patch_ppt_v1_with_vdd_leakage(struct pp_hwmgr *hwmgr,
hwmgr            1817 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
hwmgr            1824 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		smu7_patch_ppt_v1_with_vdd_leakage(hwmgr,
hwmgr            1831 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		struct pp_hwmgr *hwmgr, struct smu7_leakage_voltage *leakage_table,
hwmgr            1835 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            1836 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	smu7_patch_ppt_v1_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
hwmgr            1837 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
hwmgr            1843 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		struct pp_hwmgr *hwmgr)
hwmgr            1847 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1849 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            1888 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int phm_add_voltage(struct pp_hwmgr *hwmgr,
hwmgr            1899 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	i = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDGFX);
hwmgr            1925 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr)
hwmgr            1929 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1930 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            1948 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			phm_add_voltage(hwmgr, pptable_info->vddc_lookup_table, &v_record);
hwmgr            1961 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			phm_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record);
hwmgr            1967 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr)
hwmgr            1971 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1972 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            1987 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			phm_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record);
hwmgr            1993 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_sort_lookup_table(struct pp_hwmgr *hwmgr,
hwmgr            2018 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_complete_dependency_tables(struct pp_hwmgr *hwmgr)
hwmgr            2022 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            2024 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            2027 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		tmp_result = smu7_patch_lookup_table_with_leakage(hwmgr,
hwmgr            2032 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		smu7_patch_ppt_v1_with_vdd_leakage(hwmgr,
hwmgr            2036 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		tmp_result = smu7_patch_lookup_table_with_leakage(hwmgr,
hwmgr            2041 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		tmp_result = smu7_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
hwmgr            2047 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp_result = smu7_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
hwmgr            2051 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp_result = smu7_calc_voltage_dependency_tables(hwmgr);
hwmgr            2055 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp_result = smu7_calc_mm_voltage_dependency_table(hwmgr);
hwmgr            2059 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp_result = smu7_sort_lookup_table(hwmgr, table_info->vddgfx_lookup_table);
hwmgr            2063 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp_result = smu7_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
hwmgr            2070 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_set_private_data_based_on_pptable_v1(struct pp_hwmgr *hwmgr)
hwmgr            2073 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            2103 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = table_info->max_clock_voltage_on_ac.sclk;
hwmgr            2104 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = table_info->max_clock_voltage_on_ac.mclk;
hwmgr            2105 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = table_info->max_clock_voltage_on_ac.vddc;
hwmgr            2106 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = table_info->max_clock_voltage_on_ac.vddci;
hwmgr            2111 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_patch_voltage_workaround(struct pp_hwmgr *hwmgr)
hwmgr            2114 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		       (struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            2119 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr            2131 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (hwmgr->chip_id == CHIP_POLARIS10 && hw_revision == 0xC7 &&
hwmgr            2148 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_thermal_parameter_init(struct pp_hwmgr *hwmgr)
hwmgr            2153 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            2156 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) {
hwmgr            2157 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		temp_reg = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL);
hwmgr            2177 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL, temp_reg);
hwmgr            2184 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode) {
hwmgr            2185 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit =
hwmgr            2186 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			(uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
hwmgr            2188 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMaxLimit =
hwmgr            2189 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			(uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
hwmgr            2191 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMStep = 1;
hwmgr            2193 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit = 100;
hwmgr            2195 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMinLimit =
hwmgr            2196 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			(uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit;
hwmgr            2198 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMStep = 1;
hwmgr            2207 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM =
hwmgr            2208 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			       hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM;
hwmgr            2210 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
hwmgr            2211 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			       hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM;
hwmgr            2213 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		hwmgr->dyn_state.cac_dtp_table->usOperatingTempMinLimit =
hwmgr            2216 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		hwmgr->dyn_state.cac_dtp_table->usOperatingTempMaxLimit =
hwmgr            2219 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp =
hwmgr            2222 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		hwmgr->dyn_state.cac_dtp_table->usOperatingTempStep =
hwmgr            2225 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp =
hwmgr            2227 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		if (hwmgr->feature_mask & PP_OD_FUZZY_FAN_CONTROL_MASK)
hwmgr            2228 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr            2242 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static void smu7_patch_ppt_v0_with_vdd_leakage(struct pp_hwmgr *hwmgr,
hwmgr            2262 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_patch_vddc(struct pp_hwmgr *hwmgr,
hwmgr            2266 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            2270 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
hwmgr            2276 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_patch_vddci(struct pp_hwmgr *hwmgr,
hwmgr            2280 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            2284 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
hwmgr            2290 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_patch_vce_vddc(struct pp_hwmgr *hwmgr,
hwmgr            2294 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            2298 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
hwmgr            2305 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_patch_uvd_vddc(struct pp_hwmgr *hwmgr,
hwmgr            2309 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            2313 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
hwmgr            2319 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_patch_vddc_shed_limit(struct pp_hwmgr *hwmgr,
hwmgr            2323 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            2327 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].Voltage,
hwmgr            2333 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_patch_samu_vddc(struct pp_hwmgr *hwmgr,
hwmgr            2337 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            2341 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
hwmgr            2347 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_patch_acp_vddc(struct pp_hwmgr *hwmgr,
hwmgr            2351 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            2355 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v,
hwmgr            2361 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_patch_limits_vddc(struct pp_hwmgr *hwmgr,
hwmgr            2365 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            2369 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddc,
hwmgr            2373 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddci,
hwmgr            2381 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_patch_cac_vddc(struct pp_hwmgr *hwmgr, struct phm_cac_leakage_table *tab)
hwmgr            2385 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            2390 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddc, &data->vddc_leakage);
hwmgr            2398 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_patch_dependency_tables_with_leakage(struct pp_hwmgr *hwmgr)
hwmgr            2402 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_sclk);
hwmgr            2406 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_mclk);
hwmgr            2410 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
hwmgr            2414 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp = smu7_patch_vddci(hwmgr, hwmgr->dyn_state.vddci_dependency_on_mclk);
hwmgr            2418 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp = smu7_patch_vce_vddc(hwmgr, hwmgr->dyn_state.vce_clock_voltage_dependency_table);
hwmgr            2422 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp = smu7_patch_uvd_vddc(hwmgr, hwmgr->dyn_state.uvd_clock_voltage_dependency_table);
hwmgr            2426 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp = smu7_patch_samu_vddc(hwmgr, hwmgr->dyn_state.samu_clock_voltage_dependency_table);
hwmgr            2430 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp = smu7_patch_acp_vddc(hwmgr, hwmgr->dyn_state.acp_clock_voltage_dependency_table);
hwmgr            2434 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp = smu7_patch_vddc_shed_limit(hwmgr, hwmgr->dyn_state.vddc_phase_shed_limits_table);
hwmgr            2438 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp = smu7_patch_limits_vddc(hwmgr, &hwmgr->dyn_state.max_clock_voltage_on_ac);
hwmgr            2442 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp = smu7_patch_limits_vddc(hwmgr, &hwmgr->dyn_state.max_clock_voltage_on_dc);
hwmgr            2446 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp = smu7_patch_cac_vddc(hwmgr, hwmgr->dyn_state.cac_leakage_table);
hwmgr            2454 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_set_private_data_based_on_pptable_v0(struct pp_hwmgr *hwmgr)
hwmgr            2456 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            2458 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct phm_clock_voltage_dependency_table *allowed_sclk_vddc_table = hwmgr->dyn_state.vddc_dependency_on_sclk;
hwmgr            2459 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct phm_clock_voltage_dependency_table *allowed_mclk_vddc_table = hwmgr->dyn_state.vddc_dependency_on_mclk;
hwmgr            2460 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct phm_clock_voltage_dependency_table *allowed_mclk_vddci_table = hwmgr->dyn_state.vddci_dependency_on_mclk;
hwmgr            2479 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	hwmgr->dyn_state.max_clock_voltage_on_ac.sclk =
hwmgr            2481 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	hwmgr->dyn_state.max_clock_voltage_on_ac.mclk =
hwmgr            2483 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	hwmgr->dyn_state.max_clock_voltage_on_ac.vddc =
hwmgr            2491 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (hwmgr->dyn_state.vddci_dependency_on_mclk != NULL && hwmgr->dyn_state.vddci_dependency_on_mclk->count >= 1)
hwmgr            2492 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = hwmgr->dyn_state.vddci_dependency_on_mclk->entries[hwmgr->dyn_state.vddci_dependency_on_mclk->count - 1].v;
hwmgr            2497 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
hwmgr            2499 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
hwmgr            2500 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
hwmgr            2501 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	kfree(hwmgr->backend);
hwmgr            2502 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	hwmgr->backend = NULL;
hwmgr            2507 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_get_elb_voltages(struct pp_hwmgr *hwmgr)
hwmgr            2510 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            2513 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (atomctrl_get_leakage_id_from_efuse(hwmgr, &efuse_voltage_id) == 0) {
hwmgr            2516 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			if (atomctrl_get_leakage_vddc_base_on_leakage(hwmgr, &vddc, &vddci,
hwmgr            2535 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
hwmgr            2544 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	hwmgr->backend = data;
hwmgr            2545 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	smu7_patch_voltage_workaround(hwmgr);
hwmgr            2546 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	smu7_init_dpm_defaults(hwmgr);
hwmgr            2549 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            2551 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		result = smu7_get_evv_voltages(hwmgr);
hwmgr            2557 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		smu7_get_elb_voltages(hwmgr);
hwmgr            2560 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (hwmgr->pp_table_version == PP_TABLE_V1) {
hwmgr            2561 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		smu7_complete_dependency_tables(hwmgr);
hwmgr            2562 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		smu7_set_private_data_based_on_pptable_v1(hwmgr);
hwmgr            2563 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	} else if (hwmgr->pp_table_version == PP_TABLE_V0) {
hwmgr            2564 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		smu7_patch_dependency_tables_with_leakage(hwmgr);
hwmgr            2565 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		smu7_set_private_data_based_on_pptable_v0(hwmgr);
hwmgr            2569 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
hwmgr            2572 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		struct amdgpu_device *adev = hwmgr->adev;
hwmgr            2576 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
hwmgr            2578 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
hwmgr            2579 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
hwmgr            2586 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
hwmgr            2588 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		hwmgr->platform_descriptor.clockStep.engineClock = 500;
hwmgr            2589 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		hwmgr->platform_descriptor.clockStep.memoryClock = 500;
hwmgr            2590 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		smu7_thermal_parameter_init(hwmgr);
hwmgr            2593 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		smu7_hwmgr_backend_fini(hwmgr);
hwmgr            2599 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_force_dpm_highest(struct pp_hwmgr *hwmgr)
hwmgr            2601 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            2612 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 				smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            2625 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 				smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            2639 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 				smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            2648 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr)
hwmgr            2650 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            2652 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (hwmgr->pp_table_version == PP_TABLE_V1)
hwmgr            2653 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		phm_apply_dal_min_voltage_request(hwmgr);
hwmgr            2658 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            2665 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            2673 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
hwmgr            2675 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            2677 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (!smum_is_dpm_running(hwmgr))
hwmgr            2681 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		smum_send_msg_to_smc(hwmgr,
hwmgr            2685 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	return smu7_upload_dpm_level_enable_mask(hwmgr);
hwmgr            2688 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_force_dpm_lowest(struct pp_hwmgr *hwmgr)
hwmgr            2691 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			(struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            2696 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			level = phm_get_lowest_enabled_level(hwmgr,
hwmgr            2698 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            2706 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			level = phm_get_lowest_enabled_level(hwmgr,
hwmgr            2708 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            2716 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			level = phm_get_lowest_enabled_level(hwmgr,
hwmgr            2718 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            2727 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_get_profiling_clk(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level,
hwmgr            2731 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            2754 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (hwmgr->pp_table_version == PP_TABLE_V0) {
hwmgr            2755 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		for (count = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1;
hwmgr            2757 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			if (tmp_sclk >= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk) {
hwmgr            2758 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 				tmp_sclk = hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk;
hwmgr            2765 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			tmp_sclk = hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].clk;
hwmgr            2769 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			*sclk_mask = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1;
hwmgr            2770 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	} else if (hwmgr->pp_table_version == PP_TABLE_V1) {
hwmgr            2772 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 				(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            2796 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	hwmgr->pstate_sclk = tmp_sclk;
hwmgr            2797 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	hwmgr->pstate_mclk = tmp_mclk;
hwmgr            2802 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_force_dpm_level(struct pp_hwmgr *hwmgr,
hwmgr            2810 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (hwmgr->pstate_sclk == 0)
hwmgr            2811 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask);
hwmgr            2815 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		ret = smu7_force_dpm_highest(hwmgr);
hwmgr            2818 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		ret = smu7_force_dpm_lowest(hwmgr);
hwmgr            2821 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		ret = smu7_unforce_dpm_levels(hwmgr);
hwmgr            2827 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		ret = smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask);
hwmgr            2830 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		smu7_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask);
hwmgr            2831 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		smu7_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask);
hwmgr            2832 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		smu7_force_clock_level(hwmgr, PP_PCIE, 1<<pcie_mask);
hwmgr            2841 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
hwmgr            2842 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			smu7_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
hwmgr            2843 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
hwmgr            2844 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			smu7_fan_ctrl_reset_fan_speed_to_default(hwmgr);
hwmgr            2849 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_get_power_state_size(struct pp_hwmgr *hwmgr)
hwmgr            2854 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_vblank_too_short(struct pp_hwmgr *hwmgr,
hwmgr            2857 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            2860 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	switch (hwmgr->chip_id) {
hwmgr            2864 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		if (hwmgr->is_kicker)
hwmgr            2883 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
hwmgr            2887 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr            2897 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            2899 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            2911 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			&(hwmgr->dyn_state.max_clock_voltage_on_ac) :
hwmgr            2912 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			&(hwmgr->dyn_state.max_clock_voltage_on_dc);
hwmgr            2924 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock;
hwmgr            2925 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
hwmgr            2927 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            2929 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
hwmgr            2952 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 				    hwmgr->platform_descriptor.platformCaps,
hwmgr            2956 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (hwmgr->display_config->num_display == 0)
hwmgr            2959 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
hwmgr            2960 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 					  !hwmgr->display_config->multi_monitor_in_sync) ||
hwmgr            2962 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			smu7_vblank_too_short(hwmgr, hwmgr->display_config->min_vblank_time);
hwmgr            3001 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            3014 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static uint32_t smu7_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
hwmgr            3019 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (hwmgr == NULL)
hwmgr            3022 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	ps = hwmgr->request_ps;
hwmgr            3036 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static uint32_t smu7_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
hwmgr            3041 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (hwmgr == NULL)
hwmgr            3044 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	ps = hwmgr->request_ps;
hwmgr            3058 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
hwmgr            3061 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            3071 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)smu_atom_get_data_table(hwmgr->adev, index,
hwmgr            3089 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			smu7_get_current_pcie_speed(hwmgr);
hwmgr            3092 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			(uint16_t)smu7_get_current_pcie_lane_number(hwmgr);
hwmgr            3103 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_get_number_of_powerplay_table_entries(struct pp_hwmgr *hwmgr)
hwmgr            3108 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (hwmgr->pp_table_version == PP_TABLE_V0) {
hwmgr            3109 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		result = pp_tables_get_num_of_entries(hwmgr, &ret);
hwmgr            3111 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	} else if (hwmgr->pp_table_version == PP_TABLE_V1) {
hwmgr            3112 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		result = get_number_of_powerplay_table_entries_v1_0(hwmgr);
hwmgr            3118 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_get_pp_table_entry_callback_func_v1(struct pp_hwmgr *hwmgr,
hwmgr            3122 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            3172 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			(smu7_power_state->performance_level_count < smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_GRAPHICS)),
hwmgr            3178 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 					hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
hwmgr            3216 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_get_pp_table_entry_v1(struct pp_hwmgr *hwmgr,
hwmgr            3221 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            3223 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            3231 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	result = get_powerplay_table_entry_v1_0(hwmgr, entry_index, state,
hwmgr            3318 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_get_pp_table_entry_callback_func_v0(struct pp_hwmgr *hwmgr,
hwmgr            3322 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            3336 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			(ps->performance_level_count < smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_GRAPHICS)),
hwmgr            3342 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 					hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
hwmgr            3361 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_get_pp_table_entry_v0(struct pp_hwmgr *hwmgr,
hwmgr            3366 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            3368 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			hwmgr->dyn_state.vddci_dependency_on_mclk;
hwmgr            3376 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	result = pp_tables_get_entry(hwmgr, entry_index, state,
hwmgr            3468 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_get_pp_table_entry(struct pp_hwmgr *hwmgr,
hwmgr            3471 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (hwmgr->pp_table_version == PP_TABLE_V0)
hwmgr            3472 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		return smu7_get_pp_table_entry_v0(hwmgr, entry_index, state);
hwmgr            3473 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	else if (hwmgr->pp_table_version == PP_TABLE_V1)
hwmgr            3474 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		return smu7_get_pp_table_entry_v1(hwmgr, entry_index, state);
hwmgr            3479 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr, u32 *query)
hwmgr            3481 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr            3499 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetCurrPkgPwr, 0);
hwmgr            3500 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		tmp = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
hwmgr            3507 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogStart);
hwmgr            3508 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
hwmgr            3513 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogSample);
hwmgr            3514 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		tmp = cgs_read_ind_register(hwmgr->device,
hwmgr            3525 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_read_sensor(struct pp_hwmgr *hwmgr, int idx,
hwmgr            3530 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            3538 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetSclkFrequency);
hwmgr            3539 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
hwmgr            3544 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetMclkFrequency);
hwmgr            3545 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
hwmgr            3551 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		offset = data->soft_regs_start + smum_get_offsetof(hwmgr,
hwmgr            3557 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset);
hwmgr            3564 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		*((uint32_t *)value) = smu7_thermal_get_temperature(hwmgr);
hwmgr            3576 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		return smu7_get_gpu_power(hwmgr, (uint32_t *)value);
hwmgr            3579 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			val_vid = PHM_READ_INDIRECT_FIELD(hwmgr->device,
hwmgr            3582 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			val_vid = PHM_READ_INDIRECT_FIELD(hwmgr->device,
hwmgr            3592 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
hwmgr            3598 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            3640 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
hwmgr            3646 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static uint16_t smu7_get_maximum_link_speed(struct pp_hwmgr *hwmgr,
hwmgr            3651 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            3672 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		struct pp_hwmgr *hwmgr, const void *input)
hwmgr            3676 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            3682 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	uint16_t target_link_speed = smu7_get_maximum_link_speed(hwmgr, smu7_nps);
hwmgr            3686 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		current_link_speed = smu7_get_maximum_link_speed(hwmgr, polaris10_cps);
hwmgr            3697 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			if (0 == amdgpu_acpi_pcie_performance_request(hwmgr->adev, PCIE_PERF_REQ_GEN3, false))
hwmgr            3704 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			if (0 == amdgpu_acpi_pcie_performance_request(hwmgr->adev, PCIE_PERF_REQ_GEN2, false))
hwmgr            3709 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			data->force_pcie_gen = smu7_get_current_pcie_speed(hwmgr);
hwmgr            3720 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
hwmgr            3722 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            3730 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
hwmgr            3733 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
hwmgr            3742 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
hwmgr            3745 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
hwmgr            3755 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		struct pp_hwmgr *hwmgr, const void *input)
hwmgr            3758 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            3768 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (hwmgr->od_enabled && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
hwmgr            3775 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (hwmgr->od_enabled && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
hwmgr            3784 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		result = smum_populate_all_graphic_levels(hwmgr);
hwmgr            3793 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		result = smum_populate_all_memory_levels(hwmgr);
hwmgr            3802 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
hwmgr            3812 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		if ((!hwmgr->od_enabled || force_trim)
hwmgr            3823 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_trim_dpm_states(struct pp_hwmgr *hwmgr,
hwmgr            3826 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            3835 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	smu7_trim_single_dpm_states(hwmgr,
hwmgr            3840 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	smu7_trim_single_dpm_states(hwmgr,
hwmgr            3849 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		struct pp_hwmgr *hwmgr, const void *input)
hwmgr            3854 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            3859 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	result = smu7_trim_dpm_states(hwmgr, smu7_ps);
hwmgr            3873 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
hwmgr            3875 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            3884 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
hwmgr            3887 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
hwmgr            3896 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr),
hwmgr            3899 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
hwmgr            3911 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		struct pp_hwmgr *hwmgr, const void *input)
hwmgr            3915 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            3918 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	uint16_t target_link_speed = smu7_get_maximum_link_speed(hwmgr, smu7_ps);
hwmgr            3930 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 				smu7_get_current_pcie_speed(hwmgr) > 0)
hwmgr            3934 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		if (amdgpu_acpi_pcie_performance_request(hwmgr->adev, request, false)) {
hwmgr            3946 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_notify_smc_display(struct pp_hwmgr *hwmgr)
hwmgr            3948 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            3950 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (hwmgr->feature_mask & PP_VBI_TIME_SUPPORT_MASK) {
hwmgr            3951 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		if (hwmgr->chip_id == CHIP_VEGAM)
hwmgr            3952 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            3955 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            3958 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	return (smum_send_msg_to_smc(hwmgr, (PPSMC_Msg)PPSMC_HasDisplay) == 0) ?  0 : -EINVAL;
hwmgr            3961 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
hwmgr            3964 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            3966 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp_result = smu7_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
hwmgr            3971 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            3974 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			smu7_request_link_speed_change_before_state_change(hwmgr, input);
hwmgr            3980 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp_result = smu7_freeze_sclk_mclk_dpm(hwmgr);
hwmgr            3984 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp_result = smu7_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
hwmgr            3989 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp_result = smu7_update_avfs(hwmgr);
hwmgr            3994 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp_result = smu7_generate_dpm_level_enable_mask(hwmgr, input);
hwmgr            3999 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp_result = smum_update_sclk_threshold(hwmgr);
hwmgr            4004 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp_result = smu7_notify_smc_display(hwmgr);
hwmgr            4009 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp_result = smu7_unfreeze_sclk_mclk_dpm(hwmgr);
hwmgr            4014 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp_result = smu7_upload_dpm_level_enable_mask(hwmgr);
hwmgr            4019 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            4022 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			smu7_notify_link_speed_change_after_state_change(hwmgr, input);
hwmgr            4031 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm)
hwmgr            4033 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	hwmgr->thermal_controller.
hwmgr            4036 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	return smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            4041 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c smu7_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
hwmgr            4045 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	return (smum_send_msg_to_smc(hwmgr, msg) == 0) ?  0 : -1;
hwmgr            4049 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c smu7_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr)
hwmgr            4051 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (hwmgr->display_config->num_display > 1 &&
hwmgr            4052 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			!hwmgr->display_config->multi_monitor_in_sync)
hwmgr            4053 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		smu7_notify_smc_display_change(hwmgr, false);
hwmgr            4064 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_program_display_gap(struct pp_hwmgr *hwmgr)
hwmgr            4066 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            4067 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL);
hwmgr            4073 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (hwmgr->display_config->num_display > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);
hwmgr            4074 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap);
hwmgr            4076 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	ref_clock =  amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
hwmgr            4077 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	refresh_rate = hwmgr->display_config->vrefresh;
hwmgr            4084 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	pre_vbi_time_in_us = frame_time_in_us - 200 - hwmgr->display_config->min_vblank_time;
hwmgr            4095 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2);
hwmgr            4097 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
hwmgr            4098 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			data->soft_regs_start + smum_get_offsetof(hwmgr,
hwmgr            4102 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
hwmgr            4103 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			data->soft_regs_start + smum_get_offsetof(hwmgr,
hwmgr            4111 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
hwmgr            4113 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	return smu7_program_display_gap(hwmgr);
hwmgr            4123 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_rpm)
hwmgr            4125 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	hwmgr->thermal_controller.
hwmgr            4128 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	return smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            4136 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_register_irq_handlers(struct pp_hwmgr *hwmgr)
hwmgr            4146 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
hwmgr            4150 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
hwmgr            4156 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
hwmgr            4165 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c smu7_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
hwmgr            4167 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            4170 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
hwmgr            4173 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (data->display_timing.vrefresh != hwmgr->display_config->vrefresh)
hwmgr            4176 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
hwmgr            4177 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr &&
hwmgr            4179 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			hwmgr->display_config->min_core_set_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK))
hwmgr            4194 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_check_states_equal(struct pp_hwmgr *hwmgr,
hwmgr            4201 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            4234 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_check_mc_firmware(struct pp_hwmgr *hwmgr)
hwmgr            4236 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            4246 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	smu7_get_mc_microcode_version(hwmgr);
hwmgr            4247 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	vbios_version = hwmgr->microcode_version_info.MC & 0xf;
hwmgr            4251 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX,
hwmgr            4253 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA);
hwmgr            4258 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		if ((hwmgr->chip_id == CHIP_POLARIS10) ||
hwmgr            4259 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		    (hwmgr->chip_id == CHIP_POLARIS11) ||
hwmgr            4260 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		    (hwmgr->chip_id == CHIP_POLARIS12))
hwmgr            4261 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableFFC);
hwmgr            4265 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		if ((hwmgr->chip_id == CHIP_POLARIS10) ||
hwmgr            4266 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		    (hwmgr->chip_id == CHIP_POLARIS11) ||
hwmgr            4267 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		    (hwmgr->chip_id == CHIP_POLARIS12))
hwmgr            4268 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableFFC);
hwmgr            4274 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_read_clock_registers(struct pp_hwmgr *hwmgr)
hwmgr            4276 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            4279 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL);
hwmgr            4281 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2);
hwmgr            4283 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_3);
hwmgr            4285 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4);
hwmgr            4287 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM);
hwmgr            4289 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM_2);
hwmgr            4291 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		cgs_read_register(hwmgr->device, mmDLL_CNTL);
hwmgr            4293 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		cgs_read_register(hwmgr->device, mmMCLK_PWRMGT_CNTL);
hwmgr            4295 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		cgs_read_register(hwmgr->device, mmMPLL_AD_FUNC_CNTL);
hwmgr            4297 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		cgs_read_register(hwmgr->device, mmMPLL_DQ_FUNC_CNTL);
hwmgr            4299 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL);
hwmgr            4301 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_1);
hwmgr            4303 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_2);
hwmgr            4305 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		cgs_read_register(hwmgr->device, mmMPLL_SS1);
hwmgr            4307 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		cgs_read_register(hwmgr->device, mmMPLL_SS2);
hwmgr            4318 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_get_memory_type(struct pp_hwmgr *hwmgr)
hwmgr            4320 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            4321 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr            4334 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
hwmgr            4336 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr            4348 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_init_power_gate_state(struct pp_hwmgr *hwmgr)
hwmgr            4350 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            4358 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_init_sclk_threshold(struct pp_hwmgr *hwmgr)
hwmgr            4360 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            4366 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_setup_asic_task(struct pp_hwmgr *hwmgr)
hwmgr            4370 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	smu7_check_mc_firmware(hwmgr);
hwmgr            4372 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp_result = smu7_read_clock_registers(hwmgr);
hwmgr            4376 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp_result = smu7_get_memory_type(hwmgr);
hwmgr            4380 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp_result = smu7_enable_acpi_power_management(hwmgr);
hwmgr            4384 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp_result = smu7_init_power_gate_state(hwmgr);
hwmgr            4388 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp_result = smu7_get_mc_microcode_version(hwmgr);
hwmgr            4392 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	tmp_result = smu7_init_sclk_threshold(hwmgr);
hwmgr            4399 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
hwmgr            4402 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            4410 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            4416 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            4426 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 				smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PCIeDPM_UnForceLevel);
hwmgr            4428 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 				smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            4441 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr,
hwmgr            4444 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            4456 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetSclkFrequency);
hwmgr            4457 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
hwmgr            4472 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetMclkFrequency);
hwmgr            4473 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
hwmgr            4488 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		pcie_speed = smu7_get_current_pcie_speed(hwmgr);
hwmgr            4504 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		if (hwmgr->od_enabled) {
hwmgr            4513 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		if (hwmgr->od_enabled) {
hwmgr            4522 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		if (hwmgr->od_enabled) {
hwmgr            4526 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 				hwmgr->platform_descriptor.overdriveLimit.engineClock/100);
hwmgr            4529 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 				hwmgr->platform_descriptor.overdriveLimit.memoryClock/100);
hwmgr            4541 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static void smu7_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
hwmgr            4545 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		smu7_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
hwmgr            4548 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            4550 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			smu7_fan_ctrl_stop_smc_fan_control(hwmgr);
hwmgr            4553 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		if (!smu7_fan_ctrl_set_static_mode(hwmgr, mode))
hwmgr            4554 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			smu7_fan_ctrl_start_smc_fan_control(hwmgr);
hwmgr            4561 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static uint32_t smu7_get_fan_control_mode(struct pp_hwmgr *hwmgr)
hwmgr            4563 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	return hwmgr->fan_ctrl_enabled ? AMD_FAN_CTRL_AUTO : AMD_FAN_CTRL_MANUAL;
hwmgr            4566 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_get_sclk_od(struct pp_hwmgr *hwmgr)
hwmgr            4568 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            4582 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
hwmgr            4584 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            4593 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	ps = hwmgr->request_ps;
hwmgr            4608 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_get_mclk_od(struct pp_hwmgr *hwmgr)
hwmgr            4610 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            4624 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
hwmgr            4626 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            4635 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	ps = hwmgr->request_ps;
hwmgr            4651 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_get_sclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks)
hwmgr            4654 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			(struct phm_ppt_v1_information *)hwmgr->pptable;
hwmgr            4659 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (hwmgr->pp_table_version == PP_TABLE_V1) {
hwmgr            4666 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	} else if (hwmgr->pp_table_version == PP_TABLE_V0) {
hwmgr            4667 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		sclk_table = hwmgr->dyn_state.vddc_dependency_on_sclk;
hwmgr            4676 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static uint32_t smu7_get_mem_latency(struct pp_hwmgr *hwmgr, uint32_t clk)
hwmgr            4678 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            4688 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_get_mclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks)
hwmgr            4691 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			(struct phm_ppt_v1_information *)hwmgr->pptable;
hwmgr            4696 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (hwmgr->pp_table_version == PP_TABLE_V1) {
hwmgr            4702 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			clocks->latency[i] = smu7_get_mem_latency(hwmgr,
hwmgr            4706 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	} else if (hwmgr->pp_table_version == PP_TABLE_V0) {
hwmgr            4707 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		mclk_table = hwmgr->dyn_state.vddc_dependency_on_mclk;
hwmgr            4715 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type,
hwmgr            4720 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		smu7_get_sclks(hwmgr, clocks);
hwmgr            4723 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		smu7_get_mclks(hwmgr, clocks);
hwmgr            4732 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
hwmgr            4739 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            4741 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
hwmgr            4743 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 					smum_get_offsetof(hwmgr,
hwmgr            4747 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
hwmgr            4749 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 					smum_get_offsetof(hwmgr,
hwmgr            4753 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
hwmgr            4755 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 					smum_get_offsetof(hwmgr,
hwmgr            4759 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
hwmgr            4761 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 					smum_get_offsetof(hwmgr,
hwmgr            4765 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
hwmgr            4767 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 					smum_get_offsetof(hwmgr,
hwmgr            4773 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_get_max_high_clocks(struct pp_hwmgr *hwmgr,
hwmgr            4776 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            4792 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
hwmgr            4795 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            4797 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			(struct phm_ppt_v1_information *)hwmgr->pptable;
hwmgr            4801 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (hwmgr->pp_table_version == PP_TABLE_V1)
hwmgr            4804 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	else if (hwmgr->pp_table_version == PP_TABLE_V0)
hwmgr            4811 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static bool smu7_check_clk_voltage_valid(struct pp_hwmgr *hwmgr,
hwmgr            4816 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            4827 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			hwmgr->platform_descriptor.overdriveLimit.engineClock < clk) {
hwmgr            4830 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 				hwmgr->platform_descriptor.overdriveLimit.engineClock/100);
hwmgr            4835 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			hwmgr->platform_descriptor.overdriveLimit.memoryClock < clk) {
hwmgr            4838 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 				hwmgr->platform_descriptor.overdriveLimit.memoryClock/100);
hwmgr            4848 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
hwmgr            4855 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            4864 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (!hwmgr->od_enabled) {
hwmgr            4883 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		smu7_odn_initial_default_setting(hwmgr);
hwmgr            4886 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		smu7_check_dpm_table_updated(hwmgr);
hwmgr            4901 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		if (smu7_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) {
hwmgr            4915 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
hwmgr            4917 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            4948 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		if (i == hwmgr->power_profile_mode) {
hwmgr            4981 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static void smu7_patch_compute_profile_mode(struct pp_hwmgr *hwmgr,
hwmgr            4984 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            4994 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 				smu7_force_clock_level(hwmgr, PP_SCLK, 3 << (level-1));
hwmgr            4996 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	} else if (hwmgr->power_profile_mode == PP_SMC_POWER_PROFILE_COMPUTE) {
hwmgr            4997 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		smu7_force_clock_level(hwmgr, PP_SCLK, data->dpm_level_enable_mask.sclk_dpm_enable_mask);
hwmgr            5001 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
hwmgr            5003 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            5034 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		if (!smum_update_dpm_settings(hwmgr, &tmp)) {
hwmgr            5036 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			hwmgr->power_profile_mode = mode;
hwmgr            5044 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		if (mode == hwmgr->power_profile_mode)
hwmgr            5048 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		if (!smum_update_dpm_settings(hwmgr, &tmp)) {
hwmgr            5061 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			smu7_patch_compute_profile_mode(hwmgr, mode);
hwmgr            5062 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 			hwmgr->power_profile_mode = mode;
hwmgr            5072 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
hwmgr            5080 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (level == NULL || hwmgr == NULL || state == NULL)
hwmgr            5083 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	data = hwmgr->backend;
hwmgr            5095 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c static int smu7_power_off_asic(struct pp_hwmgr *hwmgr)
hwmgr            5099 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	result = smu7_disable_dpm_tasks(hwmgr);
hwmgr            5184 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c int smu7_init_function_pointers(struct pp_hwmgr *hwmgr)
hwmgr            5188 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	hwmgr->hwmgr_func = &smu7_hwmgr_funcs;
hwmgr            5189 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	if (hwmgr->pp_table_version == PP_TABLE_V0)
hwmgr            5190 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		hwmgr->pptable_func = &pptable_funcs;
hwmgr            5191 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 	else if (hwmgr->pp_table_version == PP_TABLE_V1)
hwmgr            5192 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 		hwmgr->pptable_func = &pptable_v1_0_funcs;
hwmgr             853 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c static int smu7_enable_didt(struct pp_hwmgr *hwmgr, const bool enable)
hwmgr             860 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 	if (hwmgr->chip_id == CHIP_POLARIS11)
hwmgr             866 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 	CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
hwmgr             872 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 	CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
hwmgr             878 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 	CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
hwmgr             884 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 	CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
hwmgr             890 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 		result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_Didt_Block_Function, didt_block);
hwmgr             895 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c static int smu7_program_pt_config_registers(struct pp_hwmgr *hwmgr,
hwmgr             910 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 				data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, config_regs->offset);
hwmgr             914 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 				data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset);
hwmgr             918 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 				data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset);
hwmgr             922 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 				data = cgs_read_register(hwmgr->device, config_regs->offset);
hwmgr             932 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 				cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, config_regs->offset, data);
hwmgr             936 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 				cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset, data);
hwmgr             940 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 				cgs_write_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset, data);
hwmgr             944 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 				cgs_write_register(hwmgr->device, config_regs->offset, data);
hwmgr             956 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c int smu7_enable_didt_config(struct pp_hwmgr *hwmgr)
hwmgr             961 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             973 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 		value2 = cgs_read_register(hwmgr->device, mmGRBM_GFX_INDEX);
hwmgr             978 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 			cgs_write_register(hwmgr->device, mmGRBM_GFX_INDEX, value);
hwmgr             980 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 			if (hwmgr->chip_id == CHIP_POLARIS10) {
hwmgr             981 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 				result = smu7_program_pt_config_registers(hwmgr, GCCACConfig_Polaris10);
hwmgr             983 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 				result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris10);
hwmgr             985 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 			} else if (hwmgr->chip_id == CHIP_POLARIS11) {
hwmgr             986 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 				result = smu7_program_pt_config_registers(hwmgr, GCCACConfig_Polaris11);
hwmgr             988 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 				if (hwmgr->is_kicker)
hwmgr             989 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 					result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris11_Kicker);
hwmgr             991 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 					result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris11);
hwmgr             993 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 			} else if (hwmgr->chip_id == CHIP_POLARIS12) {
hwmgr             994 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 				result = smu7_program_pt_config_registers(hwmgr, GCCACConfig_Polaris11);
hwmgr             996 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 				result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris12);
hwmgr             998 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 			} else if (hwmgr->chip_id == CHIP_VEGAM) {
hwmgr             999 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 				result = smu7_program_pt_config_registers(hwmgr, GCCACConfig_VegaM);
hwmgr            1001 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 				result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_VegaM);
hwmgr            1005 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 		cgs_write_register(hwmgr->device, mmGRBM_GFX_INDEX, value2);
hwmgr            1007 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 		result = smu7_enable_didt(hwmgr, true);
hwmgr            1010 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 		if (hwmgr->chip_id == CHIP_POLARIS11) {
hwmgr            1011 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 			result = smum_send_msg_to_smc(hwmgr,
hwmgr            1027 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c int smu7_disable_didt_config(struct pp_hwmgr *hwmgr)
hwmgr            1030 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr            1039 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 		result = smu7_enable_didt(hwmgr, false);
hwmgr            1043 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 		if (hwmgr->chip_id == CHIP_POLARIS11) {
hwmgr            1044 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 			result = smum_send_msg_to_smc(hwmgr,
hwmgr            1058 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c int smu7_enable_smc_cac(struct pp_hwmgr *hwmgr)
hwmgr            1060 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1065 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 		smc_result = smum_send_msg_to_smc(hwmgr,
hwmgr            1075 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c int smu7_disable_smc_cac(struct pp_hwmgr *hwmgr)
hwmgr            1077 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1081 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 		int smc_result = smum_send_msg_to_smc(hwmgr,
hwmgr            1091 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c int smu7_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
hwmgr            1093 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1097 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 		return smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            1102 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c static int smu7_set_overdriver_target_tdp(struct pp_hwmgr *hwmgr,
hwmgr            1105 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 	return smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            1109 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c int smu7_enable_power_containment(struct pp_hwmgr *hwmgr)
hwmgr            1111 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1113 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            1119 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 	if (hwmgr->pp_table_version == PP_TABLE_V1)
hwmgr            1122 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 		cac_table = hwmgr->dyn_state.cac_dtp_table;
hwmgr            1126 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 			smc_result = smum_send_msg_to_smc(hwmgr,
hwmgr            1136 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 			smc_result = smum_send_msg_to_smc(hwmgr,
hwmgr            1141 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 				hwmgr->default_power_limit = hwmgr->power_limit =
hwmgr            1146 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 				if (smu7_set_power_limit(hwmgr, hwmgr->power_limit))
hwmgr            1154 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c int smu7_disable_power_containment(struct pp_hwmgr *hwmgr)
hwmgr            1156 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1165 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 			smc_result = smum_send_msg_to_smc(hwmgr,
hwmgr            1174 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 			smc_result = smum_send_msg_to_smc(hwmgr,
hwmgr            1183 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 			smc_result = smum_send_msg_to_smc(hwmgr,
hwmgr            1195 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c int smu7_power_control_set_level(struct pp_hwmgr *hwmgr)
hwmgr            1198 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            1204 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 	if (hwmgr->pp_table_version == PP_TABLE_V1)
hwmgr            1207 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 		cac_table = hwmgr->dyn_state.cac_dtp_table;
hwmgr            1210 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 		adjust_percent = hwmgr->platform_descriptor.TDPAdjustmentPolarity ?
hwmgr            1211 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 				hwmgr->platform_descriptor.TDPAdjustment :
hwmgr            1212 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 				(-1 * hwmgr->platform_descriptor.TDPAdjustment);
hwmgr            1214 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 		if (hwmgr->chip_id > CHIP_TONGA)
hwmgr            1219 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.c 		result = smu7_set_overdriver_target_tdp(hwmgr, (uint32_t)target_tdp);
hwmgr              53 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.h int smu7_enable_smc_cac(struct pp_hwmgr *hwmgr);
hwmgr              54 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.h int smu7_disable_smc_cac(struct pp_hwmgr *hwmgr);
hwmgr              55 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.h int smu7_enable_power_containment(struct pp_hwmgr *hwmgr);
hwmgr              56 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.h int smu7_disable_power_containment(struct pp_hwmgr *hwmgr);
hwmgr              57 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.h int smu7_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n);
hwmgr              58 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.h int smu7_power_control_set_level(struct pp_hwmgr *hwmgr);
hwmgr              59 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.h int smu7_enable_didt_config(struct pp_hwmgr *hwmgr);
hwmgr              60 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_powertune.h int smu7_disable_didt_config(struct pp_hwmgr *hwmgr);
hwmgr              29 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c int smu7_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr,
hwmgr              32 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 	if (hwmgr->thermal_controller.fanInfo.bNoFan)
hwmgr              41 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 	    hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) {
hwmgr              44 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 		fan_speed_info->min_rpm = hwmgr->thermal_controller.fanInfo.ulMinRPM;
hwmgr              45 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 		fan_speed_info->max_rpm = hwmgr->thermal_controller.fanInfo.ulMaxRPM;
hwmgr              54 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c int smu7_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr,
hwmgr              61 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 	if (hwmgr->thermal_controller.fanInfo.bNoFan)
hwmgr              64 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 	duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr              66 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 	duty = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr              83 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c int smu7_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed)
hwmgr              88 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 	if (hwmgr->thermal_controller.fanInfo.bNoFan ||
hwmgr              89 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 	    !hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution)
hwmgr              92 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 	tach_period = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr              98 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 	crystal_clock_freq = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
hwmgr             111 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c int smu7_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
hwmgr             113 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 	if (hwmgr->fan_ctrl_is_in_default_mode) {
hwmgr             114 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 		hwmgr->fan_ctrl_default_mode =
hwmgr             115 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 				PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             117 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 		hwmgr->tmin =
hwmgr             118 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 				PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             120 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 		hwmgr->fan_ctrl_is_in_default_mode = false;
hwmgr             123 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             125 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             136 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c int smu7_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr)
hwmgr             138 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 	if (!hwmgr->fan_ctrl_is_in_default_mode) {
hwmgr             139 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 		PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             140 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 				CG_FDO_CTRL2, FDO_PWM_MODE, hwmgr->fan_ctrl_default_mode);
hwmgr             141 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 		PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             142 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 				CG_FDO_CTRL2, TMIN, hwmgr->tmin);
hwmgr             143 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 		hwmgr->fan_ctrl_is_in_default_mode = true;
hwmgr             149 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c int smu7_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
hwmgr             154 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 		cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, FAN_CONTROL_FUZZY);
hwmgr             155 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 		result = smum_send_msg_to_smc(hwmgr, PPSMC_StartFanControl);
hwmgr             158 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 			hwmgr->hwmgr_func->set_max_fan_rpm_output(hwmgr,
hwmgr             159 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 					hwmgr->thermal_controller.
hwmgr             162 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 			hwmgr->hwmgr_func->set_max_fan_pwm_output(hwmgr,
hwmgr             163 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 					hwmgr->thermal_controller.
hwmgr             167 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 		cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, FAN_CONTROL_TABLE);
hwmgr             168 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 		result = smum_send_msg_to_smc(hwmgr, PPSMC_StartFanControl);
hwmgr             171 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 	if (!result && hwmgr->thermal_controller.
hwmgr             173 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 		result = smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             175 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 				hwmgr->thermal_controller.
hwmgr             177 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 	hwmgr->fan_ctrl_enabled = true;
hwmgr             183 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c int smu7_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr)
hwmgr             185 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 	hwmgr->fan_ctrl_enabled = false;
hwmgr             186 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 	return smum_send_msg_to_smc(hwmgr, PPSMC_StopFanControl);
hwmgr             195 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c int smu7_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
hwmgr             202 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 	if (hwmgr->thermal_controller.fanInfo.bNoFan)
hwmgr             209 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 		smu7_fan_ctrl_stop_smc_fan_control(hwmgr);
hwmgr             211 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 	duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             221 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             224 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 	return smu7_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
hwmgr             232 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c int smu7_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr)
hwmgr             236 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 	if (hwmgr->thermal_controller.fanInfo.bNoFan)
hwmgr             240 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 		result = smu7_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
hwmgr             242 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 			result = smu7_fan_ctrl_start_smc_fan_control(hwmgr);
hwmgr             244 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 		result = smu7_fan_ctrl_set_default_mode(hwmgr);
hwmgr             255 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c int smu7_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed)
hwmgr             260 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 	if (hwmgr->thermal_controller.fanInfo.bNoFan ||
hwmgr             261 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 			(hwmgr->thermal_controller.fanInfo.
hwmgr             264 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 			(speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) ||
hwmgr             265 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 			(speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM))
hwmgr             269 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 		smu7_fan_ctrl_stop_smc_fan_control(hwmgr);
hwmgr             271 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 	crystal_clock_freq = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
hwmgr             275 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             278 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 	return smu7_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC_RPM);
hwmgr             286 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c int smu7_thermal_get_temperature(struct pp_hwmgr *hwmgr)
hwmgr             290 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 	temp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             311 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c static int smu7_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
hwmgr             327 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             330 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             333 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             345 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c static int smu7_thermal_initialize(struct pp_hwmgr *hwmgr)
hwmgr             347 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 	if (hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution)
hwmgr             348 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 		PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             350 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 				hwmgr->thermal_controller.fanInfo.
hwmgr             353 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             364 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c static void smu7_thermal_enable_alert(struct pp_hwmgr *hwmgr)
hwmgr             368 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 	alert = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             371 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             375 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Thermal_Cntl_Enable);
hwmgr             382 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c int smu7_thermal_disable_alert(struct pp_hwmgr *hwmgr)
hwmgr             386 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 	alert = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             389 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             393 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 	return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Thermal_Cntl_Disable);
hwmgr             401 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c int smu7_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr)
hwmgr             403 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 	int result = smu7_thermal_disable_alert(hwmgr);
hwmgr             405 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 	if (!hwmgr->thermal_controller.fanInfo.bNoFan)
hwmgr             406 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 		smu7_fan_ctrl_set_default_mode(hwmgr);
hwmgr             420 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c static int smu7_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr)
hwmgr             428 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 		smu7_fan_ctrl_start_smc_fan_control(hwmgr);
hwmgr             429 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 		smu7_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
hwmgr             435 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c int smu7_start_thermal_controller(struct pp_hwmgr *hwmgr,
hwmgr             443 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 	smu7_thermal_initialize(hwmgr);
hwmgr             444 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 	ret = smu7_thermal_set_temperature_range(hwmgr, range->min, range->max);
hwmgr             447 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 	smu7_thermal_enable_alert(hwmgr);
hwmgr             448 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 	ret = smum_thermal_avfs_enable(hwmgr);
hwmgr             457 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 	smum_thermal_setup_fan_table(hwmgr);
hwmgr             458 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 	smu7_thermal_start_smc_fan_control(hwmgr);
hwmgr             464 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c int smu7_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr)
hwmgr             466 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 	if (!hwmgr->thermal_controller.fanInfo.bNoFan)
hwmgr             467 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c 		smu7_fan_ctrl_set_default_mode(hwmgr);
hwmgr              41 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.h extern int smu7_thermal_get_temperature(struct pp_hwmgr *hwmgr);
hwmgr              42 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.h extern int smu7_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr);
hwmgr              43 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.h extern int smu7_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info);
hwmgr              44 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.h extern int smu7_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t *speed);
hwmgr              45 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.h extern int smu7_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr);
hwmgr              46 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.h extern int smu7_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode);
hwmgr              47 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.h extern int smu7_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t speed);
hwmgr              48 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.h extern int smu7_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr);
hwmgr              49 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.h extern int smu7_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr);
hwmgr              50 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.h extern int smu7_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed);
hwmgr              51 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.h extern int smu7_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed);
hwmgr              52 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.h extern int smu7_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr);
hwmgr              53 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.h extern int smu7_thermal_disable_alert(struct pp_hwmgr *hwmgr);
hwmgr              54 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.h extern int smu7_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr);
hwmgr              55 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.h extern int smu7_start_thermal_controller(struct pp_hwmgr *hwmgr,
hwmgr              68 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static uint32_t smu8_get_eclk_level(struct pp_hwmgr *hwmgr,
hwmgr              73 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		hwmgr->dyn_state.vce_clock_voltage_dependency_table;
hwmgr              99 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static uint32_t smu8_get_sclk_level(struct pp_hwmgr *hwmgr,
hwmgr             104 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 				hwmgr->dyn_state.vddc_dependency_on_sclk;
hwmgr             129 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static uint32_t smu8_get_uvd_level(struct pp_hwmgr *hwmgr,
hwmgr             134 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
hwmgr             160 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static uint32_t smu8_get_max_sclk_level(struct pp_hwmgr *hwmgr)
hwmgr             162 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	struct smu8_hwmgr *data = hwmgr->backend;
hwmgr             165 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxSclkLevel);
hwmgr             166 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		data->max_sclk_level = smum_get_argument(hwmgr) + 1;
hwmgr             172 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
hwmgr             174 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	struct smu8_hwmgr *data = hwmgr->backend;
hwmgr             175 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             197 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             200 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             203 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             208 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             215 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             218 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             220 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             228 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             231 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             233 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             237 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             240 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             249 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 			struct pp_hwmgr *hwmgr, uint16_t voltage)
hwmgr             254 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_construct_max_power_limits_table(struct pp_hwmgr *hwmgr,
hwmgr             257 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	struct smu8_hwmgr *data = hwmgr->backend;
hwmgr             260 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 				hwmgr->dyn_state.vddc_dependency_on_sclk;
hwmgr             264 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		table->vddc = smu8_convert_8Bit_index_to_voltage(hwmgr,
hwmgr             272 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 			struct pp_hwmgr *hwmgr,
hwmgr             302 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
hwmgr             307 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_get_system_info_data(struct pp_hwmgr *hwmgr)
hwmgr             309 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	struct smu8_hwmgr *data = hwmgr->backend;
hwmgr             316 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	info = (ATOM_INTEGRATED_SYSTEM_INFO_V1_9 *)smu_atom_get_data_table(hwmgr->adev,
hwmgr             396 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             402 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	smu8_construct_max_power_limits_table (hwmgr,
hwmgr             403 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 				    &hwmgr->dyn_state.max_clock_voltage_on_ac);
hwmgr             405 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	smu8_init_dynamic_state_adjustment_rule_settings(hwmgr,
hwmgr             411 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_construct_boot_state(struct pp_hwmgr *hwmgr)
hwmgr             413 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	struct smu8_hwmgr *data = hwmgr->backend;
hwmgr             433 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_upload_pptable_to_smu(struct pp_hwmgr *hwmgr)
hwmgr             442 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		hwmgr->dyn_state.vddc_dependency_on_sclk;
hwmgr             444 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		hwmgr->dyn_state.vdd_gfx_dependency_on_sclk;
hwmgr             446 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		hwmgr->dyn_state.acp_clock_voltage_dependency_table;
hwmgr             448 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
hwmgr             450 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		hwmgr->dyn_state.vce_clock_voltage_dependency_table;
hwmgr             452 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	if (!hwmgr->need_pp_table_upload)
hwmgr             455 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	ret = smum_download_powerplay_table(hwmgr, &table);
hwmgr             482 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		atomctrl_get_engine_pll_dividers_kong(hwmgr,
hwmgr             499 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		atomctrl_get_engine_pll_dividers_kong(hwmgr,
hwmgr             513 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		atomctrl_get_engine_pll_dividers_kong(hwmgr,
hwmgr             525 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		atomctrl_get_engine_pll_dividers_kong(hwmgr,
hwmgr             539 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		atomctrl_get_engine_pll_dividers_kong(hwmgr,
hwmgr             547 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	ret = smum_upload_powerplay_table(hwmgr);
hwmgr             552 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_init_sclk_limit(struct pp_hwmgr *hwmgr)
hwmgr             554 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	struct smu8_hwmgr *data = hwmgr->backend;
hwmgr             556 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 					hwmgr->dyn_state.vddc_dependency_on_sclk;
hwmgr             565 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	level = smu8_get_max_sclk_level(hwmgr) - 1;
hwmgr             578 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_init_uvd_limit(struct pp_hwmgr *hwmgr)
hwmgr             580 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	struct smu8_hwmgr *data = hwmgr->backend;
hwmgr             582 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 				hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
hwmgr             591 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxUvdLevel);
hwmgr             592 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	level = smum_get_argument(hwmgr);
hwmgr             605 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_init_vce_limit(struct pp_hwmgr *hwmgr)
hwmgr             607 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	struct smu8_hwmgr *data = hwmgr->backend;
hwmgr             609 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 				hwmgr->dyn_state.vce_clock_voltage_dependency_table;
hwmgr             618 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxEclkLevel);
hwmgr             619 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	level = smum_get_argument(hwmgr);
hwmgr             632 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_init_acp_limit(struct pp_hwmgr *hwmgr)
hwmgr             634 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	struct smu8_hwmgr *data = hwmgr->backend;
hwmgr             636 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 				hwmgr->dyn_state.acp_clock_voltage_dependency_table;
hwmgr             645 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxAclkLevel);
hwmgr             646 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	level = smum_get_argument(hwmgr);
hwmgr             658 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static void smu8_init_power_gate_state(struct pp_hwmgr *hwmgr)
hwmgr             660 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	struct smu8_hwmgr *data = hwmgr->backend;
hwmgr             668 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ACPPowerOFF);
hwmgr             674 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static void smu8_init_sclk_threshold(struct pp_hwmgr *hwmgr)
hwmgr             676 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	struct smu8_hwmgr *data = hwmgr->backend;
hwmgr             681 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_update_sclk_limit(struct pp_hwmgr *hwmgr)
hwmgr             683 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	struct smu8_hwmgr *data = hwmgr->backend;
hwmgr             685 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 					hwmgr->dyn_state.vddc_dependency_on_sclk;
hwmgr             693 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	level = smu8_get_max_sclk_level(hwmgr) - 1;
hwmgr             700 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	clock = hwmgr->display_config->min_core_set_clock;
hwmgr             707 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             709 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 						 smu8_get_sclk_level(hwmgr,
hwmgr             717 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr             721 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		stable_pstate_sclk = (hwmgr->dyn_state.max_clock_voltage_on_ac.mclk *
hwmgr             730 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             732 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 						smu8_get_sclk_level(hwmgr,
hwmgr             737 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr             741 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             743 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 						smu8_get_sclk_level(hwmgr,
hwmgr             751 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_set_deep_sleep_sclk_threshold(struct pp_hwmgr *hwmgr)
hwmgr             753 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr             755 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		uint32_t clks = hwmgr->display_config->min_core_set_clock_in_sr;
hwmgr             761 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             769 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_set_watermark_threshold(struct pp_hwmgr *hwmgr)
hwmgr             772 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 				  hwmgr->backend;
hwmgr             774 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             781 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_nbdpm_pstate_enable_disable(struct pp_hwmgr *hwmgr, bool enable, bool lock)
hwmgr             783 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	struct smu8_hwmgr *hw_data = hwmgr->backend;
hwmgr             789 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 			return smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             795 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 			return smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             804 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_disable_nb_dpm(struct pp_hwmgr *hwmgr)
hwmgr             808 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	struct smu8_hwmgr *data = hwmgr->backend;
hwmgr             812 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		smu8_nbdpm_pstate_enable_disable(hwmgr, true, true);
hwmgr             815 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 							  hwmgr,
hwmgr             825 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_enable_nb_dpm(struct pp_hwmgr *hwmgr)
hwmgr             829 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	struct smu8_hwmgr *data = hwmgr->backend;
hwmgr             836 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 							  hwmgr,
hwmgr             846 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_update_low_mem_pstate(struct pp_hwmgr *hwmgr, const void *input)
hwmgr             850 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	struct smu8_hwmgr *hw_data = hwmgr->backend;
hwmgr             859 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 			smu8_nbdpm_pstate_enable_disable(hwmgr, false, disable_switch);
hwmgr             861 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 			smu8_nbdpm_pstate_enable_disable(hwmgr, true, disable_switch);
hwmgr             863 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 			smu8_nbdpm_pstate_enable_disable(hwmgr, enable_low_mem_state, disable_switch);
hwmgr             868 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
hwmgr             872 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	smu8_update_sclk_limit(hwmgr);
hwmgr             873 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	smu8_set_deep_sleep_sclk_threshold(hwmgr);
hwmgr             874 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	smu8_set_watermark_threshold(hwmgr);
hwmgr             875 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	ret = smu8_enable_nb_dpm(hwmgr);
hwmgr             878 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	smu8_update_low_mem_pstate(hwmgr, input);
hwmgr             884 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_setup_asic_task(struct pp_hwmgr *hwmgr)
hwmgr             888 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	ret = smu8_upload_pptable_to_smu(hwmgr);
hwmgr             891 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	ret = smu8_init_sclk_limit(hwmgr);
hwmgr             894 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	ret = smu8_init_uvd_limit(hwmgr);
hwmgr             897 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	ret = smu8_init_vce_limit(hwmgr);
hwmgr             900 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	ret = smu8_init_acp_limit(hwmgr);
hwmgr             904 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	smu8_init_power_gate_state(hwmgr);
hwmgr             905 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	smu8_init_sclk_threshold(hwmgr);
hwmgr             910 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static void smu8_power_up_display_clock_sys_pll(struct pp_hwmgr *hwmgr)
hwmgr             912 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	struct smu8_hwmgr *hw_data = hwmgr->backend;
hwmgr             918 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static void smu8_clear_nb_dpm_flag(struct pp_hwmgr *hwmgr)
hwmgr             920 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	struct smu8_hwmgr *hw_data = hwmgr->backend;
hwmgr             925 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static void smu8_reset_cc6_data(struct pp_hwmgr *hwmgr)
hwmgr             927 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	struct smu8_hwmgr *hw_data = hwmgr->backend;
hwmgr             935 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static void smu8_program_voting_clients(struct pp_hwmgr *hwmgr)
hwmgr             937 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             942 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static void smu8_clear_voting_clients(struct pp_hwmgr *hwmgr)
hwmgr             944 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             948 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_start_dpm(struct pp_hwmgr *hwmgr)
hwmgr             950 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	struct smu8_hwmgr *data = hwmgr->backend;
hwmgr             954 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	return smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             959 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_stop_dpm(struct pp_hwmgr *hwmgr)
hwmgr             962 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	struct smu8_hwmgr *data = hwmgr->backend;
hwmgr             968 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		ret = smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             975 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_program_bootup_state(struct pp_hwmgr *hwmgr)
hwmgr             977 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	struct smu8_hwmgr *data = hwmgr->backend;
hwmgr             982 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             984 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 				smu8_get_sclk_level(hwmgr,
hwmgr             988 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             990 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 				smu8_get_sclk_level(hwmgr,
hwmgr             997 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static void smu8_reset_acp_boot_level(struct pp_hwmgr *hwmgr)
hwmgr             999 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	struct smu8_hwmgr *data = hwmgr->backend;
hwmgr            1004 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
hwmgr            1006 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	smu8_program_voting_clients(hwmgr);
hwmgr            1007 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	if (smu8_start_dpm(hwmgr))
hwmgr            1009 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	smu8_program_bootup_state(hwmgr);
hwmgr            1010 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	smu8_reset_acp_boot_level(hwmgr);
hwmgr            1015 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
hwmgr            1017 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	smu8_disable_nb_dpm(hwmgr);
hwmgr            1019 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	smu8_clear_voting_clients(hwmgr);
hwmgr            1020 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	if (smu8_stop_dpm(hwmgr))
hwmgr            1026 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_power_off_asic(struct pp_hwmgr *hwmgr)
hwmgr            1028 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	smu8_disable_dpm_tasks(hwmgr);
hwmgr            1029 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	smu8_power_up_display_clock_sys_pll(hwmgr);
hwmgr            1030 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	smu8_clear_nb_dpm_flag(hwmgr);
hwmgr            1031 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	smu8_reset_cc6_data(hwmgr);
hwmgr            1035 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
hwmgr            1045 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	struct smu8_hwmgr *data = hwmgr->backend;
hwmgr            1053 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	clocks.memoryClock = hwmgr->display_config->min_mem_set_clock != 0 ?
hwmgr            1054 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 				hwmgr->display_config->min_mem_set_clock :
hwmgr            1058 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
hwmgr            1059 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		clocks.memoryClock = hwmgr->dyn_state.max_clock_voltage_on_ac.mclk;
hwmgr            1062 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 			|| (hwmgr->display_config->num_display >= 3);
hwmgr            1066 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	if (hwmgr->request_dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
hwmgr            1067 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		smu8_nbdpm_pstate_enable_disable(hwmgr, false, false);
hwmgr            1068 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	else if (hwmgr->request_dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD)
hwmgr            1069 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		smu8_nbdpm_pstate_enable_disable(hwmgr, false, true);
hwmgr            1080 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
hwmgr            1089 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	hwmgr->backend = data;
hwmgr            1091 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	result = smu8_initialize_dpm_defaults(hwmgr);
hwmgr            1097 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	result = smu8_get_system_info_data(hwmgr);
hwmgr            1103 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	smu8_construct_boot_state(hwmgr);
hwmgr            1105 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =  SMU8_MAX_HARDWARE_POWERLEVELS;
hwmgr            1110 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
hwmgr            1112 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	if (hwmgr != NULL) {
hwmgr            1113 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
hwmgr            1114 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
hwmgr            1116 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		kfree(hwmgr->backend);
hwmgr            1117 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		hwmgr->backend = NULL;
hwmgr            1122 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_phm_force_dpm_highest(struct pp_hwmgr *hwmgr)
hwmgr            1124 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	struct smu8_hwmgr *data = hwmgr->backend;
hwmgr            1126 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            1128 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 					smu8_get_sclk_level(hwmgr,
hwmgr            1132 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            1134 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 				smu8_get_sclk_level(hwmgr,
hwmgr            1141 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_phm_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
hwmgr            1143 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	struct smu8_hwmgr *data = hwmgr->backend;
hwmgr            1145 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 				hwmgr->dyn_state.vddc_dependency_on_sclk;
hwmgr            1153 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	hwmgr->pstate_sclk = table->entries[0].clk;
hwmgr            1154 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	hwmgr->pstate_mclk = 0;
hwmgr            1156 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	level = smu8_get_max_sclk_level(hwmgr) - 1;
hwmgr            1166 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            1168 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 				smu8_get_sclk_level(hwmgr,
hwmgr            1172 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            1174 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 				smu8_get_sclk_level(hwmgr,
hwmgr            1181 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_phm_force_dpm_lowest(struct pp_hwmgr *hwmgr)
hwmgr            1183 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	struct smu8_hwmgr *data = hwmgr->backend;
hwmgr            1185 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            1187 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 			smu8_get_sclk_level(hwmgr,
hwmgr            1191 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            1193 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 				smu8_get_sclk_level(hwmgr,
hwmgr            1200 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
hwmgr            1208 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		ret = smu8_phm_force_dpm_highest(hwmgr);
hwmgr            1213 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		ret = smu8_phm_force_dpm_lowest(hwmgr);
hwmgr            1216 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		ret = smu8_phm_unforce_dpm_levels(hwmgr);
hwmgr            1227 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_dpm_powerdown_uvd(struct pp_hwmgr *hwmgr)
hwmgr            1230 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_UVDPowerOFF);
hwmgr            1234 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_dpm_powerup_uvd(struct pp_hwmgr *hwmgr)
hwmgr            1238 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 			hwmgr,
hwmgr            1246 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int  smu8_dpm_update_vce_dpm(struct pp_hwmgr *hwmgr)
hwmgr            1248 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	struct smu8_hwmgr *data = hwmgr->backend;
hwmgr            1250 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		hwmgr->dyn_state.vce_clock_voltage_dependency_table;
hwmgr            1254 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	    hwmgr->en_umd_pstate) {
hwmgr            1258 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            1260 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 			smu8_get_eclk_level(hwmgr,
hwmgr            1265 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            1269 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            1275 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_dpm_powerdown_vce(struct pp_hwmgr *hwmgr)
hwmgr            1278 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		return smum_send_msg_to_smc(hwmgr,
hwmgr            1283 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_dpm_powerup_vce(struct pp_hwmgr *hwmgr)
hwmgr            1286 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		return smum_send_msg_to_smc(hwmgr,
hwmgr            1291 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static uint32_t smu8_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
hwmgr            1293 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	struct smu8_hwmgr *data = hwmgr->backend;
hwmgr            1298 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static uint32_t smu8_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
hwmgr            1303 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	if (hwmgr == NULL)
hwmgr            1306 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	ps = hwmgr->request_ps;
hwmgr            1319 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
hwmgr            1322 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	struct smu8_hwmgr *data = hwmgr->backend;
hwmgr            1334 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 						     struct pp_hwmgr *hwmgr,
hwmgr            1344 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 				    hwmgr->dyn_state.vddc_dependency_on_sclk;
hwmgr            1347 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	if (clock_info_index > (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1))
hwmgr            1348 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		clock_info_index = (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1);
hwmgr            1355 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
hwmgr            1363 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_dpm_get_num_of_pp_table_entries(struct pp_hwmgr *hwmgr)
hwmgr            1368 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	result = pp_tables_get_num_of_entries(hwmgr, &ret);
hwmgr            1373 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr,
hwmgr            1383 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	result = pp_tables_get_entry(hwmgr, entry, ps,
hwmgr            1392 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_get_power_state_size(struct pp_hwmgr *hwmgr)
hwmgr            1412 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c  static int smu8_set_cpu_power_state(struct pp_hwmgr *hwmgr)
hwmgr            1414 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	struct smu8_hwmgr *hw_data = hwmgr->backend;
hwmgr            1436 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            1445 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time,
hwmgr            1448 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	struct smu8_hwmgr *hw_data = hwmgr->backend;
hwmgr            1472 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_get_dal_power_level(struct pp_hwmgr *hwmgr,
hwmgr            1477 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 			hwmgr->dyn_state.vddc_dep_on_dal_pwrl;
hwmgr            1479 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 			&hwmgr->dyn_state.max_clock_voltage_on_ac;
hwmgr            1493 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_force_clock_level(struct pp_hwmgr *hwmgr,
hwmgr            1498 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            1501 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            1512 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_print_clock_levels(struct pp_hwmgr *hwmgr,
hwmgr            1515 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	struct smu8_hwmgr *data = hwmgr->backend;
hwmgr            1517 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 			hwmgr->dyn_state.vddc_dependency_on_sclk;
hwmgr            1522 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		now = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device,
hwmgr            1534 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		now = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device,
hwmgr            1551 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
hwmgr            1560 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	if (level == NULL || hwmgr == NULL || state == NULL)
hwmgr            1563 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	data = hwmgr->backend;
hwmgr            1583 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	level->vddc = (smu8_convert_8Bit_index_to_voltage(hwmgr, ps->levels[level_index].vddcIndex) + 2) / 4;
hwmgr            1590 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr,
hwmgr            1601 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type,
hwmgr            1604 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	struct smu8_hwmgr *data = hwmgr->backend;
hwmgr            1608 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	clocks->count = smu8_get_max_sclk_level(hwmgr);
hwmgr            1615 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		table = hwmgr->dyn_state.vddc_dependency_on_sclk;
hwmgr            1631 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)
hwmgr            1634 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 					hwmgr->dyn_state.vddc_dependency_on_sclk;
hwmgr            1637 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 			&hwmgr->dyn_state.max_clock_voltage_on_ac;
hwmgr            1642 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	level = smu8_get_max_sclk_level(hwmgr) - 1;
hwmgr            1654 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_thermal_get_temperature(struct pp_hwmgr *hwmgr)
hwmgr            1657 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	uint32_t val = cgs_read_ind_register(hwmgr->device,
hwmgr            1669 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_read_sensor(struct pp_hwmgr *hwmgr, int idx,
hwmgr            1672 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	struct smu8_hwmgr *data = hwmgr->backend;
hwmgr            1675 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 				hwmgr->dyn_state.vddc_dependency_on_sclk;
hwmgr            1678 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		hwmgr->dyn_state.vce_clock_voltage_dependency_table;
hwmgr            1681 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
hwmgr            1683 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	uint32_t sclk_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX),
hwmgr            1685 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	uint32_t uvd_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
hwmgr            1687 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	uint32_t vce_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
hwmgr            1708 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_NB_CURRENTVID) &
hwmgr            1710 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		vddnb = smu8_convert_8Bit_index_to_voltage(hwmgr, tmp) / 4;
hwmgr            1714 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMUSVI_GFX_CURRENTVID) &
hwmgr            1716 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		vddgfx = smu8_convert_8Bit_index_to_voltage(hwmgr, (u16)tmp) / 4;
hwmgr            1756 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		result = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetAverageGraphicsActivity);
hwmgr            1758 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 			activity_percent = cgs_read_register(hwmgr->device, mmSMU_MP1_SRBM2P_ARG_0);
hwmgr            1772 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		*((uint32_t *)value) = smu8_thermal_get_temperature(hwmgr);
hwmgr            1779 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
hwmgr            1786 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            1789 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            1792 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            1795 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            1799 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            1805 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
hwmgr            1808 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	struct smu8_hwmgr *data = hwmgr->backend;
hwmgr            1819 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
hwmgr            1821 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	struct smu8_hwmgr *data = hwmgr->backend;
hwmgr            1825 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            1829 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            1834 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            1840 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c int smu8_dpm_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
hwmgr            1842 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	struct smu8_hwmgr *data = hwmgr->backend;
hwmgr            1844 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
hwmgr            1849 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		    hwmgr->en_umd_pstate) {
hwmgr            1853 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 			smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            1855 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 				smu8_get_uvd_level(hwmgr,
hwmgr            1859 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 			smu8_enable_disable_uvd_dpm(hwmgr, true);
hwmgr            1861 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 			smu8_enable_disable_uvd_dpm(hwmgr, true);
hwmgr            1864 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		smu8_enable_disable_uvd_dpm(hwmgr, false);
hwmgr            1870 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static int smu8_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
hwmgr            1872 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	struct smu8_hwmgr *data = hwmgr->backend;
hwmgr            1876 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 				hwmgr->platform_descriptor.platformCaps,
hwmgr            1880 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            1885 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            1893 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static void smu8_dpm_powergate_acp(struct pp_hwmgr *hwmgr, bool bgate)
hwmgr            1895 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	struct smu8_hwmgr *data = hwmgr->backend;
hwmgr            1901 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ACPPowerOFF);
hwmgr            1903 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ACPPowerON);
hwmgr            1906 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static void smu8_dpm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
hwmgr            1908 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	struct smu8_hwmgr *data = hwmgr->backend;
hwmgr            1913 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		amdgpu_device_ip_set_powergating_state(hwmgr->adev,
hwmgr            1916 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
hwmgr            1919 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		smu8_dpm_update_uvd_dpm(hwmgr, true);
hwmgr            1920 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		smu8_dpm_powerdown_uvd(hwmgr);
hwmgr            1922 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		smu8_dpm_powerup_uvd(hwmgr);
hwmgr            1923 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
hwmgr            1926 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		amdgpu_device_ip_set_powergating_state(hwmgr->adev,
hwmgr            1929 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		smu8_dpm_update_uvd_dpm(hwmgr, false);
hwmgr            1934 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c static void smu8_dpm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
hwmgr            1936 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	struct smu8_hwmgr *data = hwmgr->backend;
hwmgr            1939 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		amdgpu_device_ip_set_powergating_state(hwmgr->adev,
hwmgr            1942 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
hwmgr            1945 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		smu8_enable_disable_vce_dpm(hwmgr, false);
hwmgr            1946 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		smu8_dpm_powerdown_vce(hwmgr);
hwmgr            1949 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		smu8_dpm_powerup_vce(hwmgr);
hwmgr            1951 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		amdgpu_device_ip_set_clockgating_state(hwmgr->adev,
hwmgr            1954 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		amdgpu_device_ip_set_powergating_state(hwmgr->adev,
hwmgr            1957 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		smu8_dpm_update_vce_dpm(hwmgr);
hwmgr            1958 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 		smu8_enable_disable_vce_dpm(hwmgr, true);
hwmgr            1997 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c int smu8_init_function_pointers(struct pp_hwmgr *hwmgr)
hwmgr            1999 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	hwmgr->hwmgr_func = &smu8_hwmgr_funcs;
hwmgr            2000 drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c 	hwmgr->pptable_func = &pptable_funcs;
hwmgr              31 drivers/gpu/drm/amd/powerplay/hwmgr/smu9_baco.c int smu9_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)
hwmgr              33 drivers/gpu/drm/amd/powerplay/hwmgr/smu9_baco.c 	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
hwmgr              37 drivers/gpu/drm/amd/powerplay/hwmgr/smu9_baco.c 	if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))
hwmgr              53 drivers/gpu/drm/amd/powerplay/hwmgr/smu9_baco.c int smu9_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)
hwmgr              55 drivers/gpu/drm/amd/powerplay/hwmgr/smu9_baco.c 	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
hwmgr              28 drivers/gpu/drm/amd/powerplay/hwmgr/smu9_baco.h extern int smu9_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap);
hwmgr              29 drivers/gpu/drm/amd/powerplay/hwmgr/smu9_baco.h extern int smu9_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);
hwmgr              46 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	struct pp_hwmgr *hwmgr,
hwmgr              68 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	struct pp_hwmgr *hwmgr,
hwmgr             109 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index,
hwmgr             115 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	if (hwmgr == NULL || hwmgr->device == NULL) {
hwmgr             120 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	for (i = 0; i < hwmgr->usec_timeout; i++) {
hwmgr             121 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 		cur_value = cgs_read_register(hwmgr->device, index);
hwmgr             128 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	if (i == hwmgr->usec_timeout)
hwmgr             139 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c int phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
hwmgr             145 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	if (hwmgr == NULL || hwmgr->device == NULL) {
hwmgr             150 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	cgs_write_register(hwmgr->device, indirect_port, index);
hwmgr             151 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	return phm_wait_on_register(hwmgr, indirect_port + 1, mask, value);
hwmgr             154 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
hwmgr             161 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	if (hwmgr == NULL || hwmgr->device == NULL)
hwmgr             164 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	for (i = 0; i < hwmgr->usec_timeout; i++) {
hwmgr             165 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 		cur_value = cgs_read_register(hwmgr->device,
hwmgr             173 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	if (i == hwmgr->usec_timeout)
hwmgr             178 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c int phm_wait_for_indirect_register_unequal(struct pp_hwmgr *hwmgr,
hwmgr             184 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	if (hwmgr == NULL || hwmgr->device == NULL)
hwmgr             187 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	cgs_write_register(hwmgr->device, indirect_port, index);
hwmgr             188 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	return phm_wait_for_register_unequal(hwmgr, indirect_port + 1,
hwmgr             192 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr)
hwmgr             194 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	return phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDPowerGating);
hwmgr             197 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c bool phm_cf_want_vce_power_gating(struct pp_hwmgr *hwmgr)
hwmgr             199 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	return phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VCEPowerGating);
hwmgr             459 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c int phm_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr,
hwmgr             466 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr             492 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c int phm_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr)
hwmgr             496 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr             517 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 		hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
hwmgr             523 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask)
hwmgr             533 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr)
hwmgr             536 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 			(struct phm_ppt_v1_information *)hwmgr->pptable;
hwmgr             540 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	enum PP_DAL_POWERLEVEL dal_power_level = hwmgr->dal_power_level;
hwmgr             559 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 			smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             568 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
hwmgr             574 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	if (hwmgr->chip_id < CHIP_TONGA) {
hwmgr             575 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 		ret = atomctrl_get_voltage_evv(hwmgr, id, voltage);
hwmgr             576 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	} else if (hwmgr->chip_id < CHIP_POLARIS10) {
hwmgr             577 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 		ret = atomctrl_get_voltage_evv_on_sclk(hwmgr, voltage_type, sclk, id, voltage);
hwmgr             581 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 		ret = atomctrl_get_voltage_evv_on_sclk_ai(hwmgr, voltage_type, sclk, id, &vol);
hwmgr             635 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c int smu9_register_irq_handlers(struct pp_hwmgr *hwmgr)
hwmgr             645 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
hwmgr             649 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
hwmgr             655 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c 	amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev),
hwmgr              51 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h 	struct pp_hwmgr *hwmgr,
hwmgr              57 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h 	struct pp_hwmgr *hwmgr,
hwmgr              62 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h extern int phm_wait_for_register_unequal(struct pp_hwmgr *hwmgr,
hwmgr              66 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h 				struct pp_hwmgr *hwmgr,
hwmgr              71 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h extern bool phm_cf_want_uvd_power_gating(struct pp_hwmgr *hwmgr);
hwmgr              72 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h extern bool phm_cf_want_vce_power_gating(struct pp_hwmgr *hwmgr);
hwmgr              73 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h extern bool phm_cf_want_microcode_fan_ctrl(struct pp_hwmgr *hwmgr);
hwmgr              88 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h extern int phm_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr, phm_ppt_v1_voltage_lookup_table *lookup_table,
hwmgr              90 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h extern int phm_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr);
hwmgr              91 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h extern uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask);
hwmgr              92 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h extern void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr);
hwmgr              94 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h extern int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
hwmgr              99 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h extern int phm_wait_on_register(struct pp_hwmgr *hwmgr, uint32_t index,
hwmgr             102 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h extern int phm_wait_on_indirect_register(struct pp_hwmgr *hwmgr,
hwmgr             112 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h int smu9_register_irq_handlers(struct pp_hwmgr *hwmgr);
hwmgr             163 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h #define PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, index, value, mask)        \
hwmgr             164 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h        phm_wait_on_indirect_register(hwmgr, mm##port##_INDEX, index, value, mask)
hwmgr             167 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h #define PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, value, mask)      \
hwmgr             168 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h        PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
hwmgr             170 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h #define PHM_WAIT_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval)	\
hwmgr             171 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h 	PHM_WAIT_INDIRECT_REGISTER(hwmgr, port, reg, (fieldval)	\
hwmgr             174 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h #define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, index, value, mask)    \
hwmgr             175 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h 		phm_wait_for_indirect_register_unequal(hwmgr,                   \
hwmgr             178 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h #define PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask)    \
hwmgr             179 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h 		PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
hwmgr             181 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h #define PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval)                          \
hwmgr             182 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h 		PHM_WAIT_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, \
hwmgr             187 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h #define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr,	\
hwmgr             189 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h 	phm_wait_for_indirect_register_unequal(hwmgr,			\
hwmgr             192 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h #define PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg, value, mask)     \
hwmgr             193 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h 		PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
hwmgr             195 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h #define PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, port, reg, field, fieldval) \
hwmgr             196 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h 	PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL(hwmgr, port, reg,	\
hwmgr             201 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h #define PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr,		\
hwmgr             203 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h 	phm_wait_on_indirect_register(hwmgr,				\
hwmgr             206 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h #define PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg, value, mask) \
hwmgr             207 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h 	PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
hwmgr             209 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h #define PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, port, reg, field, fieldval) \
hwmgr             210 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h 	PHM_WAIT_VFPF_INDIRECT_REGISTER(hwmgr, port, reg,		\
hwmgr             214 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h #define PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr,         \
hwmgr             216 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h 		phm_wait_for_register_unequal(hwmgr,            \
hwmgr             219 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h #define PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg, value, mask)		\
hwmgr             220 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h 	PHM_WAIT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr,			\
hwmgr             223 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h #define PHM_WAIT_FIELD_UNEQUAL(hwmgr, reg, field, fieldval)		\
hwmgr             224 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h 	PHM_WAIT_REGISTER_UNEQUAL(hwmgr, reg,				\
hwmgr              88 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c int vega10_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
hwmgr              92 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c 	smu9_baco_get_state(hwmgr, &cur_state);
hwmgr              99 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c 		if (soc15_baco_program_registers(hwmgr, pre_baco_tbl,
hwmgr             101 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c 			if (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnterBaco))
hwmgr             104 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c 			if (soc15_baco_program_registers(hwmgr, enter_baco_tbl,
hwmgr             112 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c 		if (soc15_baco_program_registers(hwmgr, exit_baco_tbl,
hwmgr             114 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c 			if (soc15_baco_program_registers(hwmgr, clean_baco_tbl,
hwmgr              27 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.h extern int vega10_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state);
hwmgr             113 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static void vega10_set_default_registry_data(struct pp_hwmgr *hwmgr)
hwmgr             115 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr             118 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true;
hwmgr             120 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			hwmgr->feature_mask & PP_SOCCLK_DPM_MASK ? false : true;
hwmgr             122 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true;
hwmgr             124 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			hwmgr->feature_mask & PP_PCIE_DPM_MASK ? false : true;
hwmgr             127 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			hwmgr->feature_mask & PP_DCEFCLK_DPM_MASK ? false : true;
hwmgr             129 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	if (hwmgr->feature_mask & PP_POWER_CONTAINMENT_MASK) {
hwmgr             136 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK ? true : false;
hwmgr             139 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			hwmgr->feature_mask & PP_ULV_MASK ? true : false;
hwmgr             142 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK ? true : false;
hwmgr             151 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		hwmgr->feature_mask & PP_AVFS_MASK ? true : false;
hwmgr             191 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_set_features_platform_caps(struct pp_hwmgr *hwmgr)
hwmgr             193 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr             195 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			(struct phm_ppt_v2_information *)hwmgr->pptable;
hwmgr             196 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             198 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             201 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             205 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             208 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             212 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             216 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             219 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             222 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             225 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             228 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             231 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             236 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             238 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             240 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             242 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             244 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             246 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             248 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             250 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             252 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             254 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             258 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtSupport);
hwmgr             260 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping);
hwmgr             262 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping);
hwmgr             264 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping);
hwmgr             266 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping);
hwmgr             268 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping);
hwmgr             270 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtEDCEnable);
hwmgr             272 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC);
hwmgr             274 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM);
hwmgr             278 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             280 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             285 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             288 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             290 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             293 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             295 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             301 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_odn_initial_default_setting(struct pp_hwmgr *hwmgr)
hwmgr             303 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr             305 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
hwmgr             315 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	result = pp_atomfwctrl_get_avfs_information(hwmgr, &avfs_params);
hwmgr             345 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	od_table[2]->entries[i].clk = hwmgr->platform_descriptor.overdriveLimit.memoryClock > od_table[2]->entries[i].clk ?
hwmgr             346 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 					hwmgr->platform_descriptor.overdriveLimit.memoryClock :
hwmgr             355 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static void vega10_init_dpm_defaults(struct pp_hwmgr *hwmgr)
hwmgr             357 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr             361 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             363 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	vega10_initialize_power_tune_defaults(hwmgr);
hwmgr             487 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion);
hwmgr             488 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	hwmgr->smu_version = smum_get_argument(hwmgr);
hwmgr             490 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	if ((hwmgr->smu_version & 0xff000000) == 0x5000000)
hwmgr             498 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	if ((hwmgr->chip_id == 0x6862 ||
hwmgr             499 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		hwmgr->chip_id == 0x6861 ||
hwmgr             500 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		hwmgr->chip_id == 0x6868) &&
hwmgr             506 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32);
hwmgr             507 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	top32 = smum_get_argument(hwmgr);
hwmgr             508 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32);
hwmgr             509 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	bottom32 = smum_get_argument(hwmgr);
hwmgr             515 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_get_socclk_for_voltage_evv(struct pp_hwmgr *hwmgr,
hwmgr             522 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
hwmgr             551 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_get_evv_voltages(struct pp_hwmgr *hwmgr)
hwmgr             553 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr             559 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			(struct phm_ppt_v2_information *)hwmgr->pptable;
hwmgr             567 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		if (!vega10_get_socclk_for_voltage_evv(hwmgr,
hwmgr             579 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			PP_ASSERT_WITH_CODE(!atomctrl_get_voltage_evv_on_sclk_ai(hwmgr,
hwmgr             608 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static void vega10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
hwmgr             635 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr,
hwmgr             642 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		vega10_patch_with_vdd_leakage(hwmgr,
hwmgr             649 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		struct pp_hwmgr *hwmgr, struct vega10_leakage_voltage *leakage_table,
hwmgr             652 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	vega10_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table);
hwmgr             659 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		struct pp_hwmgr *hwmgr)
hwmgr             664 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
hwmgr             711 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_sort_lookup_table(struct pp_hwmgr *hwmgr,
hwmgr             737 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_complete_dependency_tables(struct pp_hwmgr *hwmgr)
hwmgr             742 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
hwmgr             744 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr             746 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	tmp_result = vega10_patch_lookup_table_with_leakage(hwmgr,
hwmgr             751 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	tmp_result = vega10_patch_clock_voltage_limits_with_vddc_leakage(hwmgr,
hwmgr             757 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	tmp_result = vega10_patch_voltage_dependency_tables_with_lookup_table(hwmgr);
hwmgr             761 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	tmp_result = vega10_sort_lookup_table(hwmgr, table_info->vddc_lookup_table);
hwmgr             768 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
hwmgr             771 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
hwmgr             796 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	hwmgr->dyn_state.max_clock_voltage_on_ac.sclk =
hwmgr             798 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	hwmgr->dyn_state.max_clock_voltage_on_ac.mclk =
hwmgr             800 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	hwmgr->dyn_state.max_clock_voltage_on_ac.vddc =
hwmgr             802 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	hwmgr->dyn_state.max_clock_voltage_on_ac.vddci =
hwmgr             808 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
hwmgr             810 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
hwmgr             811 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
hwmgr             813 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	kfree(hwmgr->backend);
hwmgr             814 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	hwmgr->backend = NULL;
hwmgr             819 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
hwmgr             825 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             831 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	hwmgr->backend = data;
hwmgr             833 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
hwmgr             834 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
hwmgr             835 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
hwmgr             837 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	vega10_set_default_registry_data(hwmgr);
hwmgr             846 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr,
hwmgr             848 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		if (!pp_atomfwctrl_get_voltage_table_v4(hwmgr,
hwmgr             856 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		kfree(hwmgr->backend);
hwmgr             857 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		hwmgr->backend = NULL;
hwmgr             864 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr,
hwmgr             866 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		if (!pp_atomfwctrl_get_voltage_table_v4(hwmgr,
hwmgr             878 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		if (pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(hwmgr,
hwmgr             885 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	vega10_set_features_platform_caps(hwmgr);
hwmgr             887 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	vega10_init_dpm_defaults(hwmgr);
hwmgr             891 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	PP_ASSERT_WITH_CODE(!vega10_get_evv_voltages(hwmgr),
hwmgr             899 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	vega10_complete_dependency_tables(hwmgr);
hwmgr             902 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	vega10_set_private_data_based_on_pptable(hwmgr);
hwmgr             906 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
hwmgr             908 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
hwmgr             909 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
hwmgr             911 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
hwmgr             913 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	hwmgr->platform_descriptor.clockStep.engineClock = 500;
hwmgr             914 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	hwmgr->platform_descriptor.clockStep.memoryClock = 500;
hwmgr             919 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM;
hwmgr             921 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			hwmgr->thermal_controller.
hwmgr             924 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			hwmgr->thermal_controller.advanceFanControlParameters.
hwmgr             927 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			hwmgr->thermal_controller.
hwmgr             929 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			hwmgr->thermal_controller.fanInfo.ulMaxRPM / 100;
hwmgr             941 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_init_sclk_threshold(struct pp_hwmgr *hwmgr)
hwmgr             943 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr             950 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_setup_dpm_led_config(struct pp_hwmgr *hwmgr)
hwmgr             952 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr             961 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	ret = pp_atomfwctrl_get_voltage_table_v4(hwmgr, VOLTAGE_TYPE_LEDDPM,
hwmgr             982 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_setup_asic_task(struct pp_hwmgr *hwmgr)
hwmgr             984 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	PP_ASSERT_WITH_CODE(!vega10_init_sclk_threshold(hwmgr),
hwmgr             988 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	PP_ASSERT_WITH_CODE(!vega10_setup_dpm_led_config(hwmgr),
hwmgr             992 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_NumOfDisplays, 0);
hwmgr            1005 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_trim_voltage_table(struct pp_hwmgr *hwmgr,
hwmgr            1049 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_get_mvdd_voltage_table(struct pp_hwmgr *hwmgr,
hwmgr            1068 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	PP_ASSERT_WITH_CODE(!vega10_trim_voltage_table(hwmgr,
hwmgr            1076 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_get_vddci_voltage_table(struct pp_hwmgr *hwmgr,
hwmgr            1095 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	PP_ASSERT_WITH_CODE(!vega10_trim_voltage_table(hwmgr, vol_table),
hwmgr            1102 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_get_vdd_voltage_table(struct pp_hwmgr *hwmgr,
hwmgr            1130 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		struct pp_hwmgr *hwmgr,
hwmgr            1153 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_construct_voltage_tables(struct pp_hwmgr *hwmgr)
hwmgr            1155 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            1157 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			(struct phm_ppt_v2_information *)hwmgr->pptable;
hwmgr            1162 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		result = vega10_get_mvdd_voltage_table(hwmgr,
hwmgr            1171 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		result = vega10_get_vddci_voltage_table(hwmgr,
hwmgr            1181 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		result = vega10_get_vdd_voltage_table(hwmgr,
hwmgr            1191 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			vega10_trim_voltage_table_to_fit_state_table(hwmgr,
hwmgr            1196 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			vega10_trim_voltage_table_to_fit_state_table(hwmgr,
hwmgr            1201 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			vega10_trim_voltage_table_to_fit_state_table(hwmgr,
hwmgr            1223 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static void vega10_setup_default_single_dpm_table(struct pp_hwmgr *hwmgr,
hwmgr            1241 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
hwmgr            1243 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            1246 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
hwmgr            1290 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
hwmgr            1292 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            1294 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
hwmgr            1338 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	vega10_setup_default_single_dpm_table(hwmgr,
hwmgr            1345 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	vega10_setup_default_single_dpm_table(hwmgr,
hwmgr            1348 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0)
hwmgr            1349 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		hwmgr->platform_descriptor.overdriveLimit.engineClock =
hwmgr            1356 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	vega10_setup_default_single_dpm_table(hwmgr,
hwmgr            1359 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	if (hwmgr->platform_descriptor.overdriveLimit.memoryClock == 0)
hwmgr            1360 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		hwmgr->platform_descriptor.overdriveLimit.memoryClock =
hwmgr            1411 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	vega10_setup_default_single_dpm_table(hwmgr,
hwmgr            1418 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	vega10_setup_default_single_dpm_table(hwmgr,
hwmgr            1425 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	vega10_setup_default_single_dpm_table(hwmgr,
hwmgr            1432 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	vega10_setup_default_single_dpm_table(hwmgr,
hwmgr            1438 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	vega10_setup_default_pcie_table(hwmgr);
hwmgr            1463 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_populate_ulv_state(struct pp_hwmgr *hwmgr)
hwmgr            1465 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            1467 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
hwmgr            1486 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_populate_single_lclk_level(struct pp_hwmgr *hwmgr,
hwmgr            1492 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			hwmgr,
hwmgr            1503 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_populate_smc_link_levels(struct pp_hwmgr *hwmgr)
hwmgr            1506 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            1516 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		result = vega10_populate_single_lclk_level(hwmgr,
hwmgr            1529 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		result = vega10_populate_single_lclk_level(hwmgr,
hwmgr            1549 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_populate_single_gfx_level(struct pp_hwmgr *hwmgr,
hwmgr            1554 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
hwmgr            1556 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            1559 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			hwmgr->platform_descriptor.overdriveLimit.engineClock;
hwmgr            1562 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	if (hwmgr->od_enabled)
hwmgr            1584 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
hwmgr            1614 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_populate_single_soc_level(struct pp_hwmgr *hwmgr,
hwmgr            1618 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            1620 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
hwmgr            1625 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	if (hwmgr->od_enabled) {
hwmgr            1644 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
hwmgr            1660 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
hwmgr            1662 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            1664 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
hwmgr            1671 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		result = vega10_populate_single_gfx_level(hwmgr,
hwmgr            1681 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		result = vega10_populate_single_gfx_level(hwmgr,
hwmgr            1695 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		result = vega10_populate_single_soc_level(hwmgr,
hwmgr            1705 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		result = vega10_populate_single_soc_level(hwmgr,
hwmgr            1717 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static void vega10_populate_vddc_soc_levels(struct pp_hwmgr *hwmgr)
hwmgr            1719 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            1721 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct phm_ppt_v2_information *table_info = hwmgr->pptable;
hwmgr            1727 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	if (hwmgr->od_enabled)
hwmgr            1750 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
hwmgr            1754 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            1756 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
hwmgr            1760 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			hwmgr->platform_descriptor.overdriveLimit.memoryClock;
hwmgr            1763 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	if (hwmgr->od_enabled)
hwmgr            1786 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			hwmgr, COMPUTE_GPUCLK_INPUT_FLAG_UCLK, mem_clock, &dividers),
hwmgr            1810 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
hwmgr            1812 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            1820 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		result = vega10_populate_single_memory_level(hwmgr,
hwmgr            1831 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		result = vega10_populate_single_memory_level(hwmgr,
hwmgr            1852 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_populate_single_display_type(struct pp_hwmgr *hwmgr,
hwmgr            1855 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            1859 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			(hwmgr->pptable);
hwmgr            1908 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_populate_all_display_clock_levels(struct pp_hwmgr *hwmgr)
hwmgr            1913 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		PP_ASSERT_WITH_CODE(!vega10_populate_single_display_type(hwmgr, i),
hwmgr            1921 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_populate_single_eclock_level(struct pp_hwmgr *hwmgr,
hwmgr            1926 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
hwmgr            1932 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
hwmgr            1948 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_populate_smc_vce_levels(struct pp_hwmgr *hwmgr)
hwmgr            1950 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            1957 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		result = vega10_populate_single_eclock_level(hwmgr,
hwmgr            1967 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		result = vega10_populate_single_eclock_level(hwmgr,
hwmgr            1979 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_populate_single_vclock_level(struct pp_hwmgr *hwmgr,
hwmgr            1984 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
hwmgr            1995 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_populate_single_dclock_level(struct pp_hwmgr *hwmgr,
hwmgr            2000 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	PP_ASSERT_WITH_CODE(!pp_atomfwctrl_get_gpu_pll_dividers_vega10(hwmgr,
hwmgr            2011 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_populate_smc_uvd_levels(struct pp_hwmgr *hwmgr)
hwmgr            2013 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            2020 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
hwmgr            2027 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		result = vega10_populate_single_vclock_level(hwmgr,
hwmgr            2036 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		result = vega10_populate_single_vclock_level(hwmgr,
hwmgr            2045 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		result = vega10_populate_single_dclock_level(hwmgr,
hwmgr            2054 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		result = vega10_populate_single_dclock_level(hwmgr,
hwmgr            2082 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_populate_clock_stretcher_table(struct pp_hwmgr *hwmgr)
hwmgr            2084 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            2087 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
hwmgr            2101 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
hwmgr            2103 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            2106 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
hwmgr            2117 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		result = pp_atomfwctrl_get_avfs_information(hwmgr, &avfs_params);
hwmgr            2292 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_acg_enable(struct pp_hwmgr *hwmgr)
hwmgr            2294 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            2298 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		if (0 == vega10_enable_smc_features(hwmgr, true,
hwmgr            2302 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_InitializeAcg);
hwmgr            2304 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgBtc);
hwmgr            2305 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		agc_btc_response = smum_get_argument(hwmgr);
hwmgr            2309 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 				smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgInClosedLoop);
hwmgr            2311 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 				smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgInOpenLoop);
hwmgr            2312 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			if (0 == vega10_enable_smc_features(hwmgr, true,
hwmgr            2324 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_acg_disable(struct pp_hwmgr *hwmgr)
hwmgr            2326 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            2330 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		if (!vega10_enable_smc_features(hwmgr, false,
hwmgr            2337 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_populate_gpio_parameters(struct pp_hwmgr *hwmgr)
hwmgr            2339 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            2344 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	result = pp_atomfwctrl_get_gpio_information(hwmgr, &gpio_params);
hwmgr            2372 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_avfs_enable(struct pp_hwmgr *hwmgr, bool enable)
hwmgr            2374 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            2382 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
hwmgr            2389 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
hwmgr            2401 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_update_avfs(struct pp_hwmgr *hwmgr)
hwmgr            2403 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            2406 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		vega10_avfs_enable(hwmgr, false);
hwmgr            2408 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		vega10_avfs_enable(hwmgr, false);
hwmgr            2409 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		vega10_avfs_enable(hwmgr, true);
hwmgr            2411 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		vega10_avfs_enable(hwmgr, true);
hwmgr            2417 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_populate_and_upload_avfs_fuse_override(struct pp_hwmgr *hwmgr)
hwmgr            2425 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            2428 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32);
hwmgr            2429 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	top32 = smum_get_argument(hwmgr);
hwmgr            2431 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32);
hwmgr            2432 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	bottom32 = smum_get_argument(hwmgr);
hwmgr            2446 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		result = smum_smc_table_manager(hwmgr,  (uint8_t *)avfs_fuse_table,
hwmgr            2456 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static void vega10_check_dpm_table_updated(struct pp_hwmgr *hwmgr)
hwmgr            2458 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            2460 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct phm_ppt_v2_information *table_info = hwmgr->pptable;
hwmgr            2492 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_init_smc_table(struct pp_hwmgr *hwmgr)
hwmgr            2495 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            2497 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
hwmgr            2503 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	result = vega10_setup_default_dpm_tables(hwmgr);
hwmgr            2509 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	if (hwmgr->od_enabled) {
hwmgr            2512 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			vega10_check_dpm_table_updated(hwmgr);
hwmgr            2514 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			vega10_odn_initial_default_setting(hwmgr);
hwmgr            2518 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	pp_atomfwctrl_get_voltage_table_v4(hwmgr, VOLTAGE_TYPE_VDDC,
hwmgr            2543 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		result = vega10_populate_ulv_state(hwmgr);
hwmgr            2549 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	result = vega10_populate_smc_link_levels(hwmgr);
hwmgr            2554 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	result = vega10_populate_all_graphic_levels(hwmgr);
hwmgr            2559 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	result = vega10_populate_all_memory_levels(hwmgr);
hwmgr            2564 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	vega10_populate_vddc_soc_levels(hwmgr);
hwmgr            2566 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	result = vega10_populate_all_display_clock_levels(hwmgr);
hwmgr            2571 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	result = vega10_populate_smc_vce_levels(hwmgr);
hwmgr            2576 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	result = vega10_populate_smc_uvd_levels(hwmgr);
hwmgr            2582 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		result = vega10_populate_clock_stretcher_table(hwmgr);
hwmgr            2588 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values);
hwmgr            2595 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		pp_atomfwctrl_get_clk_information_by_clkid(hwmgr,
hwmgr            2598 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		pp_atomfwctrl_get_clk_information_by_clkid(hwmgr,
hwmgr            2604 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            2611 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            2616 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	result = vega10_populate_avfs_parameters(hwmgr);
hwmgr            2621 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	result = vega10_populate_gpio_parameters(hwmgr);
hwmgr            2635 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	vega10_populate_and_upload_avfs_fuse_override(hwmgr);
hwmgr            2637 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	result = smum_smc_table_manager(hwmgr, (uint8_t *)pp_table, PPTABLE, false);
hwmgr            2642 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	result = vega10_avfs_enable(hwmgr, true);
hwmgr            2645 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	vega10_acg_enable(hwmgr);
hwmgr            2650 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_enable_thermal_protection(struct pp_hwmgr *hwmgr)
hwmgr            2652 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            2659 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 				!vega10_enable_smc_features(hwmgr,
hwmgr            2670 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_disable_thermal_protection(struct pp_hwmgr *hwmgr)
hwmgr            2672 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            2679 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 				!vega10_enable_smc_features(hwmgr,
hwmgr            2690 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_enable_vrhot_feature(struct pp_hwmgr *hwmgr)
hwmgr            2692 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            2697 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 					!vega10_enable_smc_features(hwmgr,
hwmgr            2706 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 						!vega10_enable_smc_features(hwmgr,
hwmgr            2718 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_enable_ulv(struct pp_hwmgr *hwmgr)
hwmgr            2720 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            2723 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
hwmgr            2733 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_disable_ulv(struct pp_hwmgr *hwmgr)
hwmgr            2735 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            2738 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
hwmgr            2748 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
hwmgr            2750 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            2753 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
hwmgr            2761 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
hwmgr            2769 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
hwmgr            2777 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
hwmgr            2787 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr)
hwmgr            2789 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            2792 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
hwmgr            2800 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
hwmgr            2808 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
hwmgr            2816 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
hwmgr            2826 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_stop_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
hwmgr            2828 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            2833 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
hwmgr            2851 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	vega10_enable_smc_features(hwmgr, false, feature_mask);
hwmgr            2863 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_start_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap)
hwmgr            2865 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            2880 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	if (vega10_enable_smc_features(hwmgr,
hwmgr            2890 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
hwmgr            2897 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            2904 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
hwmgr            2915 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_enable_disable_PCC_limit_feature(struct pp_hwmgr *hwmgr, bool enable)
hwmgr            2917 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            2922 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
hwmgr            2932 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
hwmgr            2934 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            2937 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	vega10_enable_disable_PCC_limit_feature(hwmgr, true);
hwmgr            2939 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            2942 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	tmp_result = vega10_construct_voltage_tables(hwmgr);
hwmgr            2947 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	tmp_result = vega10_init_smc_table(hwmgr);
hwmgr            2953 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		tmp_result = vega10_enable_thermal_protection(hwmgr);
hwmgr            2959 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	tmp_result = vega10_enable_vrhot_feature(hwmgr);
hwmgr            2964 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	tmp_result = vega10_enable_deep_sleep_master_switch(hwmgr);
hwmgr            2969 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	tmp_result = vega10_start_dpm(hwmgr, SMC_DPM_FEATURES);
hwmgr            2974 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	tmp_result = vega10_enable_didt_config(hwmgr);
hwmgr            2978 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	tmp_result = vega10_enable_power_containment(hwmgr);
hwmgr            2983 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	tmp_result = vega10_power_control_set_level(hwmgr);
hwmgr            2988 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	tmp_result = vega10_enable_ulv(hwmgr);
hwmgr            2996 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_get_power_state_size(struct pp_hwmgr *hwmgr)
hwmgr            3001 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr,
hwmgr            3067 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 					hwmgr->platform_descriptor.
hwmgr            3097 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_get_pp_table_entry(struct pp_hwmgr *hwmgr,
hwmgr            3107 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	result = vega10_get_powerplay_table_entry(hwmgr, entry_index, state,
hwmgr            3124 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_patch_boot_state(struct pp_hwmgr *hwmgr,
hwmgr            3130 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
hwmgr            3134 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr            3146 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            3148 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
hwmgr            3161 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			&(hwmgr->dyn_state.max_clock_voltage_on_ac) :
hwmgr            3162 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			&(hwmgr->dyn_state.max_clock_voltage_on_dc);
hwmgr            3179 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock;
hwmgr            3180 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
hwmgr            3191 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac);
hwmgr            3220 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	if (hwmgr->display_config->num_display == 0)
hwmgr            3223 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
hwmgr            3224 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 					  !hwmgr->display_config->multi_monitor_in_sync) ||
hwmgr            3256 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
hwmgr            3283 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input)
hwmgr            3285 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            3322 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
hwmgr            3329 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		struct pp_hwmgr *hwmgr, const void *input)
hwmgr            3332 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            3341 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	if (hwmgr->od_enabled && data->need_update_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
hwmgr            3347 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	if (hwmgr->od_enabled && data->need_update_dpm_table & DPMTABLE_OD_UPDATE_MCLK) {
hwmgr            3354 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		result = vega10_populate_all_graphic_levels(hwmgr);
hwmgr            3362 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		result = vega10_populate_all_memory_levels(hwmgr);
hwmgr            3368 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	vega10_populate_vddc_soc_levels(hwmgr);
hwmgr            3373 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_trim_single_dpm_states(struct pp_hwmgr *hwmgr,
hwmgr            3389 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_trim_single_dpm_states_with_mask(struct pp_hwmgr *hwmgr,
hwmgr            3408 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_trim_dpm_states(struct pp_hwmgr *hwmgr,
hwmgr            3411 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            3420 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	vega10_trim_single_dpm_states(hwmgr,
hwmgr            3425 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	vega10_trim_single_dpm_states_with_mask(hwmgr,
hwmgr            3431 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	vega10_trim_single_dpm_states(hwmgr,
hwmgr            3471 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		struct pp_hwmgr *hwmgr)
hwmgr            3476 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_get_soc_index_for_max_uclk(struct pp_hwmgr *hwmgr)
hwmgr            3480 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
hwmgr            3487 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_upload_dpm_bootup_level(struct pp_hwmgr *hwmgr)
hwmgr            3489 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            3492 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	vega10_apply_dal_minimum_voltage_request(hwmgr);
hwmgr            3497 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            3509 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 				socclk_idx = vega10_get_soc_index_for_max_uclk(hwmgr);
hwmgr            3510 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 				smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            3514 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 				smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            3526 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            3537 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
hwmgr            3539 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            3541 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	vega10_apply_dal_minimum_voltage_request(hwmgr);
hwmgr            3546 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            3557 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            3568 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            3580 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		struct pp_hwmgr *hwmgr, const void *input)
hwmgr            3582 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            3589 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	PP_ASSERT_WITH_CODE(!vega10_trim_dpm_states(hwmgr, vega10_ps),
hwmgr            3606 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
hwmgr            3609 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
hwmgr            3625 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c int vega10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
hwmgr            3627 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            3630 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
hwmgr            3641 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
hwmgr            3643 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            3655 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            3663 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_set_power_state_tasks(struct pp_hwmgr *hwmgr,
hwmgr            3667 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            3670 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	tmp_result = vega10_find_dpm_states_clocks_in_dpm_table(hwmgr, input);
hwmgr            3675 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	tmp_result = vega10_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input);
hwmgr            3680 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	tmp_result = vega10_generate_dpm_level_enable_mask(hwmgr, input);
hwmgr            3685 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	tmp_result = vega10_update_sclk_threshold(hwmgr);
hwmgr            3690 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	result = smum_smc_table_manager(hwmgr, (uint8_t *)pp_table, PPTABLE, false);
hwmgr            3694 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	vega10_update_avfs(hwmgr);
hwmgr            3705 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static uint32_t vega10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
hwmgr            3710 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	if (hwmgr == NULL)
hwmgr            3713 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	ps = hwmgr->request_ps;
hwmgr            3727 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static uint32_t vega10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
hwmgr            3732 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	if (hwmgr == NULL)
hwmgr            3735 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	ps = hwmgr->request_ps;
hwmgr            3749 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_get_gpu_power(struct pp_hwmgr *hwmgr,
hwmgr            3757 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrPkgPwr);
hwmgr            3758 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	value = smum_get_argument(hwmgr);
hwmgr            3766 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
hwmgr            3769 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr            3771 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            3778 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetAverageGfxclkActualFrequency);
hwmgr            3779 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		sclk_mhz = smum_get_argument(hwmgr);
hwmgr            3783 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex);
hwmgr            3784 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		mclk_idx = smum_get_argument(hwmgr);
hwmgr            3793 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetAverageGfxActivity, 0);
hwmgr            3794 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		activity_percent = smum_get_argument(hwmgr);
hwmgr            3799 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		*((uint32_t *)value) = vega10_thermal_get_temperature(hwmgr);
hwmgr            3803 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetTemperatureHotspot);
hwmgr            3804 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		*((uint32_t *)value) = smum_get_argument(hwmgr) *
hwmgr            3809 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetTemperatureHBM);
hwmgr            3810 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		*((uint32_t *)value) = smum_get_argument(hwmgr) *
hwmgr            3823 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		ret = vega10_get_gpu_power(hwmgr, (uint32_t *)value);
hwmgr            3832 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		ret = vega10_get_enabled_smc_features(hwmgr, (uint64_t *)value);
hwmgr            3844 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static void vega10_notify_smc_display_change(struct pp_hwmgr *hwmgr,
hwmgr            3847 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            3852 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c int vega10_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
hwmgr            3882 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            3890 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static uint8_t vega10_get_uclk_index(struct pp_hwmgr *hwmgr,
hwmgr            3911 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		struct pp_hwmgr *hwmgr)
hwmgr            3913 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            3917 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			(struct phm_ppt_v2_information *)hwmgr->pptable;
hwmgr            3924 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	if ((hwmgr->display_config->num_display > 1) &&
hwmgr            3925 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	     !hwmgr->display_config->multi_monitor_in_sync &&
hwmgr            3926 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	     !hwmgr->display_config->nb_pstate_switch_disable)
hwmgr            3927 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		vega10_notify_smc_display_change(hwmgr, false);
hwmgr            3929 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		vega10_notify_smc_display_change(hwmgr, true);
hwmgr            3931 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
hwmgr            3932 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
hwmgr            3933 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
hwmgr            3943 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		if (!vega10_display_clock_voltage_request(hwmgr, &clock_req)) {
hwmgr            3945 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 					hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk,
hwmgr            3955 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		idx = vega10_get_uclk_index(hwmgr, mclk_table, min_clocks.memoryClock);
hwmgr            3956 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetSoftMinUclkByIndex, idx);
hwmgr            3963 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_force_dpm_highest(struct pp_hwmgr *hwmgr)
hwmgr            3965 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            3974 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
hwmgr            3978 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
hwmgr            3985 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_force_dpm_lowest(struct pp_hwmgr *hwmgr)
hwmgr            3987 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            3996 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
hwmgr            4000 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
hwmgr            4008 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
hwmgr            4010 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            4021 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
hwmgr            4025 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
hwmgr            4031 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level,
hwmgr            4035 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
hwmgr            4043 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		hwmgr->pstate_sclk = table_info->vdd_dep_on_sclk->entries[VEGA10_UMD_PSTATE_GFXCLK_LEVEL].clk;
hwmgr            4044 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		hwmgr->pstate_mclk = table_info->vdd_dep_on_mclk->entries[VEGA10_UMD_PSTATE_MCLK_LEVEL].clk;
hwmgr            4059 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static void vega10_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
hwmgr            4063 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		vega10_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
hwmgr            4067 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
hwmgr            4071 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			vega10_fan_ctrl_start_smc_fan_control(hwmgr);
hwmgr            4078 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_force_clock_level(struct pp_hwmgr *hwmgr,
hwmgr            4081 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            4088 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
hwmgr            4092 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
hwmgr            4101 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
hwmgr            4105 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
hwmgr            4115 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		PP_ASSERT_WITH_CODE(!vega10_upload_dpm_bootup_level(hwmgr),
hwmgr            4119 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		PP_ASSERT_WITH_CODE(!vega10_upload_dpm_max_level(hwmgr),
hwmgr            4137 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
hwmgr            4145 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	if (hwmgr->pstate_sclk == 0)
hwmgr            4146 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
hwmgr            4150 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		ret = vega10_force_dpm_highest(hwmgr);
hwmgr            4153 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		ret = vega10_force_dpm_lowest(hwmgr);
hwmgr            4156 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		ret = vega10_unforce_dpm_levels(hwmgr);
hwmgr            4162 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		ret = vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
hwmgr            4165 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		vega10_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask);
hwmgr            4166 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		vega10_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask);
hwmgr            4175 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
hwmgr            4176 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			vega10_set_fan_control_mode(hwmgr, AMD_FAN_CTRL_NONE);
hwmgr            4177 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
hwmgr            4178 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			vega10_set_fan_control_mode(hwmgr, AMD_FAN_CTRL_AUTO);
hwmgr            4184 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static uint32_t vega10_get_fan_control_mode(struct pp_hwmgr *hwmgr)
hwmgr            4186 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            4194 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_get_dal_power_level(struct pp_hwmgr *hwmgr,
hwmgr            4198 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			(struct phm_ppt_v2_information *)hwmgr->pptable;
hwmgr            4208 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static void vega10_get_sclks(struct pp_hwmgr *hwmgr,
hwmgr            4212 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			(struct phm_ppt_v2_information *)hwmgr->pptable;
hwmgr            4228 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static void vega10_get_memclocks(struct pp_hwmgr *hwmgr,
hwmgr            4232 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			(struct phm_ppt_v2_information *)hwmgr->pptable;
hwmgr            4235 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            4254 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static void vega10_get_dcefclocks(struct pp_hwmgr *hwmgr,
hwmgr            4258 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			(struct phm_ppt_v2_information *)hwmgr->pptable;
hwmgr            4270 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static void vega10_get_socclocks(struct pp_hwmgr *hwmgr,
hwmgr            4274 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			(struct phm_ppt_v2_information *)hwmgr->pptable;
hwmgr            4286 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
hwmgr            4292 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		vega10_get_sclks(hwmgr, clocks);
hwmgr            4295 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		vega10_get_memclocks(hwmgr, clocks);
hwmgr            4298 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		vega10_get_dcefclocks(hwmgr, clocks);
hwmgr            4301 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		vega10_get_socclocks(hwmgr, clocks);
hwmgr            4310 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
hwmgr            4315 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			(struct phm_ppt_v2_information *)hwmgr->pptable;
hwmgr            4352 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
hwmgr            4355 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            4368 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf)
hwmgr            4410 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	ret = vega10_get_enabled_smc_features(hwmgr, &features_enabled);
hwmgr            4430 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfeature_masks)
hwmgr            4440 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	ret = vega10_get_enabled_smc_features(hwmgr, &features_enabled);
hwmgr            4453 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		ret = vega10_enable_smc_features(hwmgr, false, features_to_disable);
hwmgr            4459 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		ret = vega10_enable_smc_features(hwmgr, true, features_to_enable);
hwmgr            4467 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_print_clock_levels(struct pp_hwmgr *hwmgr,
hwmgr            4470 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            4485 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex);
hwmgr            4486 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		now = smum_get_argument(hwmgr);
hwmgr            4497 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex);
hwmgr            4498 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		now = smum_get_argument(hwmgr);
hwmgr            4509 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentSocclkIndex);
hwmgr            4510 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		now = smum_get_argument(hwmgr);
hwmgr            4521 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            4523 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		now = smum_get_argument(hwmgr);
hwmgr            4532 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentLinkIndex);
hwmgr            4533 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		now = smum_get_argument(hwmgr);
hwmgr            4543 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		if (hwmgr->od_enabled) {
hwmgr            4553 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		if (hwmgr->od_enabled) {
hwmgr            4563 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		if (hwmgr->od_enabled) {
hwmgr            4567 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 				hwmgr->platform_descriptor.overdriveLimit.engineClock/100);
hwmgr            4570 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 				hwmgr->platform_descriptor.overdriveLimit.memoryClock/100);
hwmgr            4582 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
hwmgr            4584 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            4590 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		result = smum_smc_table_manager(hwmgr, (uint8_t *)wm_table, WMTABLE, false);
hwmgr            4596 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            4597 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			PPSMC_MSG_NumOfDisplays, hwmgr->display_config->num_display);
hwmgr            4603 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c int vega10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
hwmgr            4605 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            4608 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
hwmgr            4618 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static void vega10_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
hwmgr            4620 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            4623 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	vega10_enable_disable_vce_dpm(hwmgr, !bgate);
hwmgr            4626 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static void vega10_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
hwmgr            4628 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            4631 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	vega10_enable_disable_uvd_dpm(hwmgr, !bgate);
hwmgr            4643 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_check_states_equal(struct pp_hwmgr *hwmgr,
hwmgr            4679 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c vega10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
hwmgr            4681 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            4684 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
hwmgr            4688 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr)
hwmgr            4695 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
hwmgr            4700 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		vega10_disable_thermal_protection(hwmgr);
hwmgr            4702 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	tmp_result = vega10_disable_power_containment(hwmgr);
hwmgr            4706 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	tmp_result = vega10_disable_didt_config(hwmgr);
hwmgr            4710 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	tmp_result = vega10_avfs_enable(hwmgr, false);
hwmgr            4714 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	tmp_result = vega10_stop_dpm(hwmgr, SMC_DPM_FEATURES);
hwmgr            4718 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	tmp_result = vega10_disable_deep_sleep_master_switch(hwmgr);
hwmgr            4722 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	tmp_result = vega10_disable_ulv(hwmgr);
hwmgr            4726 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	tmp_result =  vega10_acg_disable(hwmgr);
hwmgr            4730 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	vega10_enable_disable_PCC_limit_feature(hwmgr, false);
hwmgr            4734 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_power_off_asic(struct pp_hwmgr *hwmgr)
hwmgr            4736 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            4739 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	result = vega10_disable_dpm_tasks(hwmgr);
hwmgr            4748 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_get_sclk_od(struct pp_hwmgr *hwmgr)
hwmgr            4750 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            4764 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
hwmgr            4766 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            4772 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	ps = hwmgr->request_ps;
hwmgr            4789 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			hwmgr->platform_descriptor.overdriveLimit.engineClock) {
hwmgr            4792 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 				hwmgr->platform_descriptor.overdriveLimit.engineClock;
hwmgr            4794 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 				hwmgr->platform_descriptor.overdriveLimit.engineClock);
hwmgr            4799 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_get_mclk_od(struct pp_hwmgr *hwmgr)
hwmgr            4801 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            4815 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
hwmgr            4817 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            4823 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	ps = hwmgr->request_ps;
hwmgr            4840 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			hwmgr->platform_descriptor.overdriveLimit.memoryClock) {
hwmgr            4843 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 				hwmgr->platform_descriptor.overdriveLimit.memoryClock;
hwmgr            4845 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 				hwmgr->platform_descriptor.overdriveLimit.memoryClock);
hwmgr            4851 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
hwmgr            4858 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            4861 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            4864 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            4868 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            4872 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            4878 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
hwmgr            4881 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            4902 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
hwmgr            4904 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            4935 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			i, profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ",
hwmgr            4939 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ",
hwmgr            4945 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
hwmgr            4947 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            4973 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            4980 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask,
hwmgr            4982 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	hwmgr->power_profile_mode = power_profile_mode;
hwmgr            4988 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static bool vega10_check_clk_voltage_valid(struct pp_hwmgr *hwmgr,
hwmgr            4993 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            5005 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			hwmgr->platform_descriptor.overdriveLimit.engineClock < clk) {
hwmgr            5008 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 				hwmgr->platform_descriptor.overdriveLimit.engineClock/100);
hwmgr            5014 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 			hwmgr->platform_descriptor.overdriveLimit.memoryClock < clk) {
hwmgr            5017 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 				hwmgr->platform_descriptor.overdriveLimit.memoryClock/100);
hwmgr            5027 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static void vega10_odn_update_power_state(struct pp_hwmgr *hwmgr)
hwmgr            5029 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            5030 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct pp_power_state *ps = hwmgr->request_ps;
hwmgr            5061 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	if (!hwmgr->ps)
hwmgr            5064 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	ps = (struct pp_power_state *)((unsigned long)(hwmgr->ps) + hwmgr->ps_size * (hwmgr->num_ps - 1));
hwmgr            5084 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static void vega10_odn_update_soc_table(struct pp_hwmgr *hwmgr,
hwmgr            5087 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            5088 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct phm_ppt_v2_information *table_info = hwmgr->pptable;
hwmgr            5152 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	vega10_odn_update_power_state(hwmgr);
hwmgr            5155 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
hwmgr            5159 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            5171 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	if (!hwmgr->od_enabled) {
hwmgr            5186 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		vega10_odn_initial_default_setting(hwmgr);
hwmgr            5187 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		vega10_odn_update_power_state(hwmgr);
hwmgr            5194 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		vega10_check_dpm_table_updated(hwmgr);
hwmgr            5209 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		if (vega10_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) {
hwmgr            5217 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	vega10_odn_update_soc_table(hwmgr, type);
hwmgr            5221 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_set_mp1_state(struct pp_hwmgr *hwmgr,
hwmgr            5238 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, msg)) == 0,
hwmgr            5245 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c static int vega10_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
hwmgr            5253 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	if (level == NULL || hwmgr == NULL || state == NULL)
hwmgr            5256 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	data = hwmgr->backend;
hwmgr            5337 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c int vega10_hwmgr_init(struct pp_hwmgr *hwmgr)
hwmgr            5339 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr            5341 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	hwmgr->hwmgr_func = &vega10_hwmgr_funcs;
hwmgr            5342 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 	hwmgr->pptable_func = &vega10_pptable_funcs;
hwmgr            5344 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 		return vega10_baco_set_cap(hwmgr);
hwmgr             435 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h extern int tonga_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr);
hwmgr             436 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h extern int tonga_hwmgr_backend_fini(struct pp_hwmgr *hwmgr);
hwmgr             437 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h extern int tonga_get_mc_microcode_version (struct pp_hwmgr *hwmgr);
hwmgr             438 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h extern int tonga_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr);
hwmgr             439 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h extern int tonga_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display);
hwmgr             440 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h int vega10_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input);
hwmgr             441 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h int vega10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate);
hwmgr             442 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h int vega10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate);
hwmgr             443 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h int vega10_update_acp_dpm(struct pp_hwmgr *hwmgr, bool bgate);
hwmgr             444 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h int vega10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable);
hwmgr             799 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c static int vega10_program_didt_config_registers(struct pp_hwmgr *hwmgr, const struct vega10_didt_config_reg *config_regs, enum vega10_didt_config_reg_type reg_type)
hwmgr             808 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 			data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset);
hwmgr             811 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset, data);
hwmgr             814 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 			data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset);
hwmgr             817 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 			cgs_write_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset, data);
hwmgr             820 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 			data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG_SE_CAC, config_regs->offset);
hwmgr             823 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 			cgs_write_ind_register(hwmgr->device, CGS_IND_REG_SE_CAC, config_regs->offset, data);
hwmgr             835 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c static int vega10_program_gc_didt_config_registers(struct pp_hwmgr *hwmgr, const struct vega10_didt_config_reg *config_regs)
hwmgr             840 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 		data = cgs_read_register(hwmgr->device, config_regs->offset);
hwmgr             843 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 		cgs_write_register(hwmgr->device, config_regs->offset, data);
hwmgr             850 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c static void vega10_didt_set_mask(struct pp_hwmgr *hwmgr, const bool enable)
hwmgr             857 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 		CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
hwmgr             864 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 		CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
hwmgr             871 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 		CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
hwmgr             878 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 		CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
hwmgr             885 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 		CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
hwmgr             891 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 			data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_EDC_CTRL);
hwmgr             894 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_EDC_CTRL, data);
hwmgr             898 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 			data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_EDC_CTRL);
hwmgr             901 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_EDC_CTRL, data);
hwmgr             905 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 			data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_EDC_CTRL);
hwmgr             908 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_EDC_CTRL, data);
hwmgr             912 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 			data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_EDC_CTRL);
hwmgr             915 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_EDC_CTRL, data);
hwmgr             919 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 			data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DBR_EDC_CTRL);
hwmgr             922 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 			cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DBR_EDC_CTRL, data);
hwmgr             928 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 		smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ConfigureGfxDidt, didt_block_info);
hwmgr             932 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c static int vega10_enable_cac_driving_se_didt_config(struct pp_hwmgr *hwmgr)
hwmgr             934 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             947 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 		result =  vega10_program_didt_config_registers(hwmgr, SEDiDtStallCtrlConfig_vega10, VEGA10_CONFIGREG_DIDT);
hwmgr             948 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 		result |= vega10_program_didt_config_registers(hwmgr, SEDiDtStallPatternConfig_vega10, VEGA10_CONFIGREG_DIDT);
hwmgr             949 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 		result |= vega10_program_didt_config_registers(hwmgr, SEDiDtWeightConfig_Vega10, VEGA10_CONFIGREG_DIDT);
hwmgr             950 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 		result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl1Config_Vega10, VEGA10_CONFIGREG_DIDT);
hwmgr             951 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 		result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl2Config_Vega10, VEGA10_CONFIGREG_DIDT);
hwmgr             952 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 		result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl3Config_vega10, VEGA10_CONFIGREG_DIDT);
hwmgr             953 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 		result |= vega10_program_didt_config_registers(hwmgr, SEDiDtTuningCtrlConfig_Vega10, VEGA10_CONFIGREG_DIDT);
hwmgr             954 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 		result |= vega10_program_didt_config_registers(hwmgr, SELCacConfig_Vega10, VEGA10_CONFIGREG_SECAC);
hwmgr             955 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 		result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl0Config_Vega10, VEGA10_CONFIGREG_DIDT);
hwmgr             963 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 	vega10_didt_set_mask(hwmgr, true);
hwmgr             970 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c static int vega10_disable_cac_driving_se_didt_config(struct pp_hwmgr *hwmgr)
hwmgr             972 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             976 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 	vega10_didt_set_mask(hwmgr, false);
hwmgr             983 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c static int vega10_enable_psm_gc_didt_config(struct pp_hwmgr *hwmgr)
hwmgr             985 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             998 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 		result = vega10_program_didt_config_registers(hwmgr, SEDiDtStallCtrlConfig_vega10, VEGA10_CONFIGREG_DIDT);
hwmgr             999 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 		result |= vega10_program_didt_config_registers(hwmgr, SEDiDtStallPatternConfig_vega10, VEGA10_CONFIGREG_DIDT);
hwmgr            1000 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 		result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl3Config_vega10, VEGA10_CONFIGREG_DIDT);
hwmgr            1001 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 		result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl0Config_Vega10, VEGA10_CONFIGREG_DIDT);
hwmgr            1008 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 	vega10_didt_set_mask(hwmgr, true);
hwmgr            1012 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 	vega10_program_gc_didt_config_registers(hwmgr, GCDiDtDroopCtrlConfig_vega10);
hwmgr            1014 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 		vega10_program_gc_didt_config_registers(hwmgr, GCDiDtCtrl0Config_vega10);
hwmgr            1017 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 		vega10_program_gc_didt_config_registers(hwmgr,  AvfsPSMInitConfig_vega10);
hwmgr            1022 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c static int vega10_disable_psm_gc_didt_config(struct pp_hwmgr *hwmgr)
hwmgr            1024 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr            1029 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 	vega10_didt_set_mask(hwmgr, false);
hwmgr            1035 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 		cgs_write_register(hwmgr->device, mmGC_DIDT_CTRL0, data);
hwmgr            1039 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 		vega10_program_gc_didt_config_registers(hwmgr,  AvfsPSMResetConfig_vega10);
hwmgr            1044 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c static int vega10_enable_se_edc_config(struct pp_hwmgr *hwmgr)
hwmgr            1046 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr            1058 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 		result = vega10_program_didt_config_registers(hwmgr, SEDiDtWeightConfig_Vega10, VEGA10_CONFIGREG_DIDT);
hwmgr            1059 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 		result |= vega10_program_didt_config_registers(hwmgr, SEEDCStallPatternConfig_Vega10, VEGA10_CONFIGREG_DIDT);
hwmgr            1060 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 		result |= vega10_program_didt_config_registers(hwmgr, SEEDCStallDelayConfig_Vega10, VEGA10_CONFIGREG_DIDT);
hwmgr            1061 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 		result |= vega10_program_didt_config_registers(hwmgr, SEEDCThresholdConfig_Vega10, VEGA10_CONFIGREG_DIDT);
hwmgr            1062 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 		result |= vega10_program_didt_config_registers(hwmgr, SEEDCCtrlResetConfig_Vega10, VEGA10_CONFIGREG_DIDT);
hwmgr            1063 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 		result |= vega10_program_didt_config_registers(hwmgr, SEEDCCtrlConfig_Vega10, VEGA10_CONFIGREG_DIDT);
hwmgr            1071 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 	vega10_didt_set_mask(hwmgr, true);
hwmgr            1078 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c static int vega10_disable_se_edc_config(struct pp_hwmgr *hwmgr)
hwmgr            1080 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr            1084 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 	vega10_didt_set_mask(hwmgr, false);
hwmgr            1091 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c static int vega10_enable_psm_gc_edc_config(struct pp_hwmgr *hwmgr)
hwmgr            1093 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr            1102 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 	vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMResetConfig_vega10);
hwmgr            1108 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 		result = vega10_program_didt_config_registers(hwmgr, PSMSEEDCStallPatternConfig_Vega10, VEGA10_CONFIGREG_DIDT);
hwmgr            1109 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 		result |= vega10_program_didt_config_registers(hwmgr, PSMSEEDCStallDelayConfig_Vega10, VEGA10_CONFIGREG_DIDT);
hwmgr            1110 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 		result |= vega10_program_didt_config_registers(hwmgr, PSMSEEDCCtrlResetConfig_Vega10, VEGA10_CONFIGREG_DIDT);
hwmgr            1111 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 		result |= vega10_program_didt_config_registers(hwmgr, PSMSEEDCCtrlConfig_Vega10, VEGA10_CONFIGREG_DIDT);
hwmgr            1119 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 	vega10_didt_set_mask(hwmgr, true);
hwmgr            1123 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 	vega10_program_gc_didt_config_registers(hwmgr, PSMGCEDCDroopCtrlConfig_vega10);
hwmgr            1126 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 		vega10_program_gc_didt_config_registers(hwmgr, PSMGCEDCCtrlResetConfig_vega10);
hwmgr            1127 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 		vega10_program_gc_didt_config_registers(hwmgr, PSMGCEDCCtrlConfig_vega10);
hwmgr            1131 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 		vega10_program_gc_didt_config_registers(hwmgr,  AvfsPSMInitConfig_vega10);
hwmgr            1136 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c static int vega10_disable_psm_gc_edc_config(struct pp_hwmgr *hwmgr)
hwmgr            1138 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr            1143 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 	vega10_didt_set_mask(hwmgr, false);
hwmgr            1149 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 		cgs_write_register(hwmgr->device, mmGC_EDC_CTRL, data);
hwmgr            1153 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 		vega10_program_gc_didt_config_registers(hwmgr,  AvfsPSMResetConfig_vega10);
hwmgr            1158 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c static int vega10_enable_se_edc_force_stall_config(struct pp_hwmgr *hwmgr)
hwmgr            1160 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr            1169 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 	result = vega10_program_didt_config_registers(hwmgr, SEEDCForceStallPatternConfig_Vega10, VEGA10_CONFIGREG_DIDT);
hwmgr            1170 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 	result |= vega10_program_didt_config_registers(hwmgr, SEEDCCtrlForceStallConfig_Vega10, VEGA10_CONFIGREG_DIDT);
hwmgr            1174 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 	vega10_didt_set_mask(hwmgr, false);
hwmgr            1181 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c static int vega10_disable_se_edc_force_stall_config(struct pp_hwmgr *hwmgr)
hwmgr            1185 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 	result = vega10_disable_se_edc_config(hwmgr);
hwmgr            1191 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c int vega10_enable_didt_config(struct pp_hwmgr *hwmgr)
hwmgr            1194 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            1202 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 			result = vega10_enable_cac_driving_se_didt_config(hwmgr);
hwmgr            1206 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 			result = vega10_enable_psm_gc_didt_config(hwmgr);
hwmgr            1210 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 			result = vega10_enable_se_edc_config(hwmgr);
hwmgr            1216 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 			result = vega10_enable_psm_gc_edc_config(hwmgr);
hwmgr            1220 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 			result = vega10_enable_se_edc_force_stall_config(hwmgr);
hwmgr            1229 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 			result = vega10_enable_smc_features(hwmgr, true, data->smu_features[GNLD_DIDT].smu_feature_bitmap);
hwmgr            1238 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c int vega10_disable_didt_config(struct pp_hwmgr *hwmgr)
hwmgr            1241 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            1249 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 			result = vega10_disable_cac_driving_se_didt_config(hwmgr);
hwmgr            1253 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 			result = vega10_disable_psm_gc_didt_config(hwmgr);
hwmgr            1257 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 			result = vega10_disable_se_edc_config(hwmgr);
hwmgr            1263 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 			result = vega10_disable_psm_gc_edc_config(hwmgr);
hwmgr            1267 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 			result = vega10_disable_se_edc_force_stall_config(hwmgr);
hwmgr            1276 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 			result = vega10_enable_smc_features(hwmgr, false, data->smu_features[GNLD_DIDT].smu_feature_bitmap);
hwmgr            1285 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c void vega10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
hwmgr            1287 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            1289 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
hwmgr            1306 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 			hwmgr->platform_descriptor.LoadLineSlope * 256;
hwmgr            1324 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c int vega10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
hwmgr            1326 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            1329 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            1335 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c int vega10_enable_power_containment(struct pp_hwmgr *hwmgr)
hwmgr            1337 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            1339 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
hwmgr            1343 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 	hwmgr->default_power_limit = hwmgr->power_limit =
hwmgr            1348 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 			PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
hwmgr            1354 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 			PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
hwmgr            1359 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 		result = vega10_set_power_limit(hwmgr, hwmgr->power_limit);
hwmgr            1368 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c int vega10_disable_power_containment(struct pp_hwmgr *hwmgr)
hwmgr            1370 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr            1374 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 			PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
hwmgr            1380 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 			PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
hwmgr            1389 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c static void vega10_set_overdrive_target_percentage(struct pp_hwmgr *hwmgr,
hwmgr            1392 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 	smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            1396 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c int vega10_power_control_set_level(struct pp_hwmgr *hwmgr)
hwmgr            1402 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 				hwmgr->platform_descriptor.TDPAdjustmentPolarity ?
hwmgr            1403 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 				hwmgr->platform_descriptor.TDPAdjustment :
hwmgr            1404 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 				(-1 * hwmgr->platform_descriptor.TDPAdjustment);
hwmgr            1405 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c 		vega10_set_overdrive_target_percentage(hwmgr,
hwmgr              69 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h void vega10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr);
hwmgr              70 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h int vega10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr);
hwmgr              71 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h int vega10_populate_pm_fuses(struct pp_hwmgr *hwmgr);
hwmgr              72 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h int vega10_enable_smc_cac(struct pp_hwmgr *hwmgr);
hwmgr              73 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h int vega10_enable_power_containment(struct pp_hwmgr *hwmgr);
hwmgr              74 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h int vega10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n);
hwmgr              75 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h int vega10_power_control_set_level(struct pp_hwmgr *hwmgr);
hwmgr              76 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h int vega10_disable_power_containment(struct pp_hwmgr *hwmgr);
hwmgr              78 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h int vega10_enable_didt_config(struct pp_hwmgr *hwmgr);
hwmgr              79 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h int vega10_disable_didt_config(struct pp_hwmgr *hwmgr);
hwmgr              38 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c static void set_hw_cap(struct pp_hwmgr *hwmgr, bool enable,
hwmgr              42 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps, cap);
hwmgr              44 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps, cap);
hwmgr              47 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c static const void *get_powerplay_table(struct pp_hwmgr *hwmgr)
hwmgr              53 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 	const void *table_address = hwmgr->soft_pp_table;
hwmgr              57 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 				smu_atom_get_data_table(hwmgr->adev, index,
hwmgr              60 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->soft_pp_table = table_address;	/*Cache the result in RAM.*/
hwmgr              61 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->soft_pp_table_size = size;
hwmgr              68 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		struct pp_hwmgr *hwmgr,
hwmgr              89 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c static int set_platform_caps(struct pp_hwmgr *hwmgr, uint32_t powerplay_caps)
hwmgr              92 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 			hwmgr,
hwmgr              97 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 			hwmgr,
hwmgr             102 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 			hwmgr,
hwmgr             107 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 			hwmgr,
hwmgr             112 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 			hwmgr,
hwmgr             120 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		struct pp_hwmgr *hwmgr,
hwmgr             136 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 	hwmgr->thermal_controller.ucType = thermal_controller->ucType;
hwmgr             137 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 	hwmgr->thermal_controller.ucI2cLine = thermal_controller->ucI2cLine;
hwmgr             138 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 	hwmgr->thermal_controller.ucI2cAddress = thermal_controller->ucI2cAddress;
hwmgr             140 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 	hwmgr->thermal_controller.fanInfo.bNoFan =
hwmgr             144 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 	hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution =
hwmgr             148 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 	hwmgr->thermal_controller.fanInfo.ulMinRPM =
hwmgr             150 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 	hwmgr->thermal_controller.fanInfo.ulMaxRPM =
hwmgr             153 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 	hwmgr->thermal_controller.advanceFanControlParameters.ulCycleDelay
hwmgr             157 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 			hwmgr,
hwmgr             158 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 			ATOM_VEGA10_PP_THERMALCONTROLLER_NONE != hwmgr->thermal_controller.ucType,
hwmgr             174 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             177 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity =
hwmgr             179 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
hwmgr             181 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit =
hwmgr             183 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit =
hwmgr             185 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.usTMax =
hwmgr             187 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin =
hwmgr             189 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.ulTargetGfxClk =
hwmgr             191 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainEdge =
hwmgr             193 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHotspot =
hwmgr             195 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainLiquid =
hwmgr             197 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrVddc =
hwmgr             199 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrMvdd =
hwmgr             201 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainPlx =
hwmgr             203 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHbm =
hwmgr             206 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.ucEnableZeroRPM =
hwmgr             208 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStopTemperature =
hwmgr             210 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStartTemperature =
hwmgr             215 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution =
hwmgr             217 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.fanInfo.ulMinRPM = fan_table_v2->ucFanMinRPM * 100UL;
hwmgr             218 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.fanInfo.ulMaxRPM = fan_table_v2->ucFanMaxRPM * 100UL;
hwmgr             219 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             221 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity =
hwmgr             223 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
hwmgr             225 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit =
hwmgr             227 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit =
hwmgr             229 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.usTMax =
hwmgr             231 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin =
hwmgr             233 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.ulTargetGfxClk =
hwmgr             235 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainEdge =
hwmgr             237 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHotspot =
hwmgr             239 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainLiquid =
hwmgr             241 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrVddc =
hwmgr             243 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrMvdd =
hwmgr             245 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainPlx =
hwmgr             247 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHbm =
hwmgr             250 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.ucEnableZeroRPM =
hwmgr             252 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStopTemperature =
hwmgr             254 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStartTemperature =
hwmgr             259 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution =
hwmgr             261 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.fanInfo.ulMinRPM = fan_table_v3->ucFanMinRPM * 100UL;
hwmgr             262 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.fanInfo.ulMaxRPM = fan_table_v3->ucFanMaxRPM * 100UL;
hwmgr             263 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             265 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity =
hwmgr             267 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM =
hwmgr             269 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit =
hwmgr             271 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit =
hwmgr             273 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.usTMax =
hwmgr             275 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin =
hwmgr             277 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.ulTargetGfxClk =
hwmgr             279 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainEdge =
hwmgr             281 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHotspot =
hwmgr             283 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainLiquid =
hwmgr             285 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrVddc =
hwmgr             287 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainVrMvdd =
hwmgr             289 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainPlx =
hwmgr             291 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.usFanGainHbm =
hwmgr             294 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.ucEnableZeroRPM =
hwmgr             296 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStopTemperature =
hwmgr             298 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.usZeroRPMStartTemperature =
hwmgr             300 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->thermal_controller.advanceFanControlParameters.usMGpuThrottlingRPMLimit =
hwmgr             308 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		struct pp_hwmgr *hwmgr,
hwmgr             327 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->platform_descriptor.overdriveLimit.engineClock =
hwmgr             330 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->platform_descriptor.overdriveLimit.engineClock =
hwmgr             332 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 	hwmgr->platform_descriptor.overdriveLimit.memoryClock =
hwmgr             335 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 	hwmgr->platform_descriptor.minOverdriveVDDC = 0;
hwmgr             336 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 	hwmgr->platform_descriptor.maxOverdriveVDDC = 0;
hwmgr             337 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 	hwmgr->platform_descriptor.overdriveVDDCStep = 0;
hwmgr             343 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		struct pp_hwmgr *hwmgr,
hwmgr             422 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		struct pp_hwmgr *hwmgr,
hwmgr             474 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->platform_descriptor.LoadLineSlope = le16_to_cpu(power_tune_table->usLoadLineResistance);
hwmgr             519 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->platform_descriptor.LoadLineSlope =
hwmgr             560 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		hwmgr->platform_descriptor.LoadLineSlope =
hwmgr             570 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		struct pp_hwmgr *hwmgr,
hwmgr             604 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		struct pp_hwmgr *hwmgr,
hwmgr             642 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		struct pp_hwmgr *hwmgr,
hwmgr             709 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		struct pp_hwmgr *hwmgr,
hwmgr             745 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		struct pp_hwmgr *hwmgr,
hwmgr             756 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             806 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c static int get_pcie_table(struct pp_hwmgr *hwmgr,
hwmgr             813 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
hwmgr             855 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		struct pp_hwmgr *hwmgr,
hwmgr             874 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		struct pp_hwmgr *hwmgr,
hwmgr             903 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		struct pp_hwmgr *hwmgr,
hwmgr             908 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		(struct phm_ppt_v2_information *)(hwmgr->pptable);
hwmgr             966 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		result = get_mm_clock_voltage_table(hwmgr,
hwmgr             971 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		result = get_tdp_table(hwmgr,
hwmgr             976 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		result = get_socclk_voltage_dependency_table(hwmgr,
hwmgr             981 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		result = get_gfxclk_voltage_dependency_table(hwmgr,
hwmgr             986 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		result = get_pix_clk_voltage_dependency_table(hwmgr,
hwmgr             992 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		result = get_pix_clk_voltage_dependency_table(hwmgr,
hwmgr             998 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		result = get_pix_clk_voltage_dependency_table(hwmgr,
hwmgr            1004 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		result = get_dcefclk_voltage_dependency_table(hwmgr,
hwmgr            1009 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		result = get_mclk_voltage_dependency_table(hwmgr,
hwmgr            1014 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		result = get_pcie_table(hwmgr,
hwmgr            1019 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		result = get_hard_limits(hwmgr,
hwmgr            1023 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 	hwmgr->dyn_state.max_clock_voltage_on_dc.sclk =
hwmgr            1025 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 	hwmgr->dyn_state.max_clock_voltage_on_dc.mclk =
hwmgr            1027 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 	hwmgr->dyn_state.max_clock_voltage_on_dc.vddc =
hwmgr            1029 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 	hwmgr->dyn_state.max_clock_voltage_on_dc.vddci =
hwmgr            1035 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		result = get_valid_clk(hwmgr,
hwmgr            1042 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		result = get_valid_clk(hwmgr,
hwmgr            1049 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		result = get_valid_clk(hwmgr,
hwmgr            1056 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		result = get_valid_clk(hwmgr,
hwmgr            1064 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		struct pp_hwmgr	*hwmgr,
hwmgr            1095 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		struct pp_hwmgr *hwmgr,
hwmgr            1100 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
hwmgr            1135 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 	hwmgr->platform_descriptor.TDPODLimit =
hwmgr            1137 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 	hwmgr->platform_descriptor.TDPAdjustment = 0;
hwmgr            1138 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 	hwmgr->platform_descriptor.VidAdjustment = 0;
hwmgr            1139 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 	hwmgr->platform_descriptor.VidAdjustmentPolarity = 0;
hwmgr            1140 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 	hwmgr->platform_descriptor.VidMinLimit = 0;
hwmgr            1141 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 	hwmgr->platform_descriptor.VidMaxLimit = 1500000;
hwmgr            1142 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 	hwmgr->platform_descriptor.VidStep = 6250;
hwmgr            1147 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		if (hwmgr->platform_descriptor.TDPODLimit)
hwmgr            1148 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 			phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr            1157 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		result = get_vddc_lookup_table(hwmgr,
hwmgr            1166 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		result = get_vddc_lookup_table(hwmgr,
hwmgr            1175 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		result = get_vddc_lookup_table(hwmgr,
hwmgr            1182 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c int vega10_pp_tables_initialize(struct pp_hwmgr *hwmgr)
hwmgr            1187 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 	hwmgr->pptable = kzalloc(sizeof(struct phm_ppt_v2_information), GFP_KERNEL);
hwmgr            1189 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 	PP_ASSERT_WITH_CODE((hwmgr->pptable != NULL),
hwmgr            1192 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 	powerplay_table = get_powerplay_table(hwmgr);
hwmgr            1197 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 	result = check_powerplay_tables(hwmgr, powerplay_table);
hwmgr            1202 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 	result = set_platform_caps(hwmgr,
hwmgr            1208 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 	result = init_thermal_controller(hwmgr, powerplay_table);
hwmgr            1213 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 	result = init_over_drive_limits(hwmgr, powerplay_table);
hwmgr            1218 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 	result = init_powerplay_extended_tables(hwmgr, powerplay_table);
hwmgr            1223 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 	result = init_dpm_2_parameters(hwmgr, powerplay_table);
hwmgr            1231 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c static int vega10_pp_tables_uninitialize(struct pp_hwmgr *hwmgr)
hwmgr            1234 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 			(struct phm_ppt_v2_information *)(hwmgr->pptable);
hwmgr            1266 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 	kfree(hwmgr->dyn_state.cac_dtp_table);
hwmgr            1267 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 	hwmgr->dyn_state.cac_dtp_table = NULL;
hwmgr            1272 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 	kfree(hwmgr->pptable);
hwmgr            1273 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 	hwmgr->pptable = NULL;
hwmgr            1283 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c int vega10_get_number_of_powerplay_table_entries(struct pp_hwmgr *hwmgr)
hwmgr            1286 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 	const ATOM_Vega10_POWERPLAYTABLE *pp_table = get_powerplay_table(hwmgr);
hwmgr            1300 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c static uint32_t make_classification_flags(struct pp_hwmgr *hwmgr,
hwmgr            1329 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c int vega10_get_powerplay_table_entry(struct pp_hwmgr *hwmgr,
hwmgr            1338 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 			get_powerplay_table(hwmgr);
hwmgr            1362 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		result = call_back_func(hwmgr, (void *)state_entry, power_state,
hwmgr            1364 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 				make_classification_flags(hwmgr,
hwmgr            1371 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 		result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(power_state->hardware));
hwmgr            1376 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c int vega10_baco_set_cap(struct pp_hwmgr *hwmgr)
hwmgr            1382 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 	powerplay_table = get_powerplay_table(hwmgr);
hwmgr            1387 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 	result = check_powerplay_tables(hwmgr, powerplay_table);
hwmgr            1393 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c 			hwmgr,
hwmgr              58 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.h extern int vega10_get_number_of_powerplay_table_entries(struct pp_hwmgr *hwmgr);
hwmgr              59 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.h extern int vega10_get_powerplay_table_entry(struct pp_hwmgr *hwmgr, uint32_t entry_index,
hwmgr              62 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.h extern int vega10_baco_set_cap(struct pp_hwmgr *hwmgr);
hwmgr              32 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c static int vega10_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm)
hwmgr              34 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentRpm);
hwmgr              35 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	*current_rpm = smum_get_argument(hwmgr);
hwmgr              39 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c int vega10_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr,
hwmgr              43 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	if (hwmgr->thermal_controller.fanInfo.bNoFan)
hwmgr              52 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 		hwmgr->thermal_controller.fanInfo.
hwmgr              57 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 				hwmgr->thermal_controller.fanInfo.ulMinRPM;
hwmgr              59 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 				hwmgr->thermal_controller.fanInfo.ulMaxRPM;
hwmgr              68 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c int vega10_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr,
hwmgr              74 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	if (hwmgr->thermal_controller.fanInfo.bNoFan)
hwmgr              77 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	if (vega10_get_current_rpm(hwmgr, &current_rpm))
hwmgr              80 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	if (hwmgr->thermal_controller.
hwmgr              83 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 			hwmgr->thermal_controller.
hwmgr              91 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c int vega10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed)
hwmgr              93 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr              94 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr              99 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	if (hwmgr->thermal_controller.fanInfo.bNoFan)
hwmgr             103 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 		result = vega10_get_current_rpm(hwmgr, speed);
hwmgr             113 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 		crystal_clock_freq = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
hwmgr             128 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c int vega10_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
hwmgr             130 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             132 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	if (hwmgr->fan_ctrl_is_in_default_mode) {
hwmgr             133 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 		hwmgr->fan_ctrl_default_mode =
hwmgr             136 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 		hwmgr->tmin =
hwmgr             139 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 		hwmgr->fan_ctrl_is_in_default_mode = false;
hwmgr             157 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c int vega10_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr)
hwmgr             159 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             161 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	if (!hwmgr->fan_ctrl_is_in_default_mode) {
hwmgr             165 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 				hwmgr->fan_ctrl_default_mode));
hwmgr             169 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 				hwmgr->tmin << CG_FDO_CTRL2__TMIN__SHIFT));
hwmgr             170 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 		hwmgr->fan_ctrl_is_in_default_mode = true;
hwmgr             183 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c static int vega10_enable_fan_control_feature(struct pp_hwmgr *hwmgr)
hwmgr             185 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr             189 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 				hwmgr, true,
hwmgr             200 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c static int vega10_disable_fan_control_feature(struct pp_hwmgr *hwmgr)
hwmgr             202 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr             206 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 				hwmgr, false,
hwmgr             217 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c int vega10_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
hwmgr             219 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	if (hwmgr->thermal_controller.fanInfo.bNoFan)
hwmgr             222 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	PP_ASSERT_WITH_CODE(!vega10_enable_fan_control_feature(hwmgr),
hwmgr             230 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c int vega10_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr)
hwmgr             232 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr             234 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	if (hwmgr->thermal_controller.fanInfo.bNoFan)
hwmgr             238 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 		PP_ASSERT_WITH_CODE(!vega10_disable_fan_control_feature(hwmgr),
hwmgr             251 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c int vega10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
hwmgr             254 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             259 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	if (hwmgr->thermal_controller.fanInfo.bNoFan)
hwmgr             266 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 		vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
hwmgr             282 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	return vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
hwmgr             290 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c int vega10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr)
hwmgr             292 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	if (hwmgr->thermal_controller.fanInfo.bNoFan)
hwmgr             296 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 		return vega10_fan_ctrl_start_smc_fan_control(hwmgr);
hwmgr             298 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 		return vega10_fan_ctrl_set_default_mode(hwmgr);
hwmgr             307 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c int vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed)
hwmgr             309 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             314 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	if (hwmgr->thermal_controller.fanInfo.bNoFan ||
hwmgr             316 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	    (speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) ||
hwmgr             317 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	    (speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM))
hwmgr             321 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 		result = vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
hwmgr             324 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 		crystal_clock_freq = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
hwmgr             331 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	return vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC_RPM);
hwmgr             339 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c int vega10_thermal_get_temperature(struct pp_hwmgr *hwmgr)
hwmgr             341 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             364 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c static int vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
hwmgr             367 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             402 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c static int vega10_thermal_initialize(struct pp_hwmgr *hwmgr)
hwmgr             404 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             406 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	if (hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) {
hwmgr             410 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 				hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution - 1));
hwmgr             425 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c static int vega10_thermal_enable_alert(struct pp_hwmgr *hwmgr)
hwmgr             427 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             428 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr             435 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
hwmgr             456 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c int vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr)
hwmgr             458 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             459 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr             466 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 		PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
hwmgr             484 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c int vega10_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr)
hwmgr             486 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	int result = vega10_thermal_disable_alert(hwmgr);
hwmgr             488 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	if (!hwmgr->thermal_controller.fanInfo.bNoFan)
hwmgr             489 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 		vega10_fan_ctrl_set_default_mode(hwmgr);
hwmgr             503 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c int vega10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
hwmgr             506 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr             512 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	table->FanMaximumRpm = (uint16_t)hwmgr->thermal_controller.
hwmgr             514 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	table->FanThrottlingRpm = hwmgr->thermal_controller.
hwmgr             516 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	table->FanAcousticLimitRpm = (uint16_t)(hwmgr->thermal_controller.
hwmgr             518 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	table->FanTargetTemperature = hwmgr->thermal_controller.
hwmgr             521 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             525 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	table->FanPwmMin = hwmgr->thermal_controller.
hwmgr             527 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	table->FanTargetGfxclk = (uint16_t)(hwmgr->thermal_controller.
hwmgr             529 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	table->FanGainEdge = hwmgr->thermal_controller.
hwmgr             531 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	table->FanGainHotspot = hwmgr->thermal_controller.
hwmgr             533 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	table->FanGainLiquid = hwmgr->thermal_controller.
hwmgr             535 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	table->FanGainVrVddc = hwmgr->thermal_controller.
hwmgr             537 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	table->FanGainVrMvdd = hwmgr->thermal_controller.
hwmgr             539 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	table->FanGainPlx = hwmgr->thermal_controller.
hwmgr             541 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	table->FanGainHbm = hwmgr->thermal_controller.
hwmgr             543 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	table->FanZeroRpmEnable = hwmgr->thermal_controller.
hwmgr             545 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	table->FanStopTemp = hwmgr->thermal_controller.
hwmgr             547 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	table->FanStartTemp = hwmgr->thermal_controller.
hwmgr             550 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	ret = smum_smc_table_manager(hwmgr,
hwmgr             559 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c int vega10_enable_mgpu_fan_boost(struct pp_hwmgr *hwmgr)
hwmgr             561 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	struct vega10_hwmgr *data = hwmgr->backend;
hwmgr             568 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	if (!hwmgr->thermal_controller.advanceFanControlParameters.
hwmgr             572 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	table->FanThrottlingRpm = hwmgr->thermal_controller.
hwmgr             575 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	ret = smum_smc_table_manager(hwmgr,
hwmgr             583 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	ret = vega10_disable_fan_control_feature(hwmgr);
hwmgr             589 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	ret = vega10_enable_fan_control_feature(hwmgr);
hwmgr             605 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c int vega10_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr)
hwmgr             613 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 		vega10_fan_ctrl_start_smc_fan_control(hwmgr);
hwmgr             619 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c int vega10_start_thermal_controller(struct pp_hwmgr *hwmgr,
hwmgr             627 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	vega10_thermal_initialize(hwmgr);
hwmgr             628 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	ret = vega10_thermal_set_temperature_range(hwmgr, range);
hwmgr             632 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	vega10_thermal_enable_alert(hwmgr);
hwmgr             638 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	ret = vega10_thermal_setup_fan_table(hwmgr);
hwmgr             642 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	vega10_thermal_start_smc_fan_control(hwmgr);
hwmgr             650 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c int vega10_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr)
hwmgr             652 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 	if (!hwmgr->thermal_controller.fanInfo.bNoFan) {
hwmgr             653 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 		vega10_fan_ctrl_set_default_mode(hwmgr);
hwmgr             654 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c 		vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
hwmgr              53 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h extern int vega10_thermal_get_temperature(struct pp_hwmgr *hwmgr);
hwmgr              54 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h extern int vega10_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr);
hwmgr              55 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h extern int vega10_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr,
hwmgr              57 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h extern int vega10_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr,
hwmgr              59 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h extern int vega10_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr);
hwmgr              60 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h extern int vega10_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr,
hwmgr              62 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h extern int vega10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
hwmgr              64 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h extern int vega10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr);
hwmgr              66 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h 		struct pp_hwmgr *hwmgr);
hwmgr              67 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h extern int vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr,
hwmgr              69 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h extern int vega10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr,
hwmgr              71 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h extern int vega10_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr);
hwmgr              72 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h extern int vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr);
hwmgr              73 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h extern int vega10_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr);
hwmgr              74 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h extern int vega10_start_thermal_controller(struct pp_hwmgr *hwmgr,
hwmgr              76 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h extern int vega10_enable_mgpu_fan_boost(struct pp_hwmgr *hwmgr);
hwmgr              86 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_baco.c int vega12_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
hwmgr              90 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_baco.c 	smu9_baco_get_state(hwmgr, &cur_state);
hwmgr              97 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_baco.c 		if (soc15_baco_program_registers(hwmgr, pre_baco_tbl,
hwmgr              99 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_baco.c 			if (smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_EnterBaco, 0))
hwmgr             102 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_baco.c 			if (soc15_baco_program_registers(hwmgr, enter_baco_tbl,
hwmgr             110 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_baco.c 		if (soc15_baco_program_registers(hwmgr, exit_baco_tbl,
hwmgr             112 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_baco.c 			if (soc15_baco_program_registers(hwmgr, clean_baco_tbl,
hwmgr              27 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_baco.h extern int vega12_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state);
hwmgr              51 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_force_clock_level(struct pp_hwmgr *hwmgr,
hwmgr              53 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_get_clock_ranges(struct pp_hwmgr *hwmgr,
hwmgr              58 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static void vega12_set_default_registry_data(struct pp_hwmgr *hwmgr)
hwmgr              61 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			(struct vega12_hwmgr *)(hwmgr->backend);
hwmgr             131 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_set_features_platform_caps(struct pp_hwmgr *hwmgr)
hwmgr             134 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			(struct vega12_hwmgr *)(hwmgr->backend);
hwmgr             135 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             138 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             141 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             144 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             148 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             150 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             155 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             158 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             162 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             165 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             167 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             171 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             173 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             178 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             181 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             183 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             190 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			&& hwmgr->thermal_controller.advanceFanControlParameters.usTMax)
hwmgr             191 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             194 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             196 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             198 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             202 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             205 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             209 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             214 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             216 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             218 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             220 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             222 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             224 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             226 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             228 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             230 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             232 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             236 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtSupport);
hwmgr             238 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping);
hwmgr             240 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping);
hwmgr             242 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping);
hwmgr             244 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping);
hwmgr             246 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping);
hwmgr             248 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtEDCEnable);
hwmgr             250 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC);
hwmgr             252 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM);
hwmgr             255 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             259 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             261 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             266 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             268 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             270 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             275 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             278 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             283 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             289 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static void vega12_init_dpm_defaults(struct pp_hwmgr *hwmgr)
hwmgr             291 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
hwmgr             292 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             360 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32);
hwmgr             361 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	top32 = smum_get_argument(hwmgr);
hwmgr             362 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32);
hwmgr             363 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	bottom32 = smum_get_argument(hwmgr);
hwmgr             368 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
hwmgr             373 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
hwmgr             375 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	kfree(hwmgr->backend);
hwmgr             376 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	hwmgr->backend = NULL;
hwmgr             381 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
hwmgr             385 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             391 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	hwmgr->backend = data;
hwmgr             393 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	vega12_set_default_registry_data(hwmgr);
hwmgr             406 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	vega12_set_features_platform_caps(hwmgr);
hwmgr             408 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	vega12_init_dpm_defaults(hwmgr);
hwmgr             411 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	vega12_set_private_data_based_on_pptable(hwmgr);
hwmgr             415 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
hwmgr             417 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
hwmgr             418 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
hwmgr             420 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
hwmgr             422 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	hwmgr->platform_descriptor.clockStep.engineClock = 500;
hwmgr             423 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	hwmgr->platform_descriptor.clockStep.memoryClock = 500;
hwmgr             428 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM;
hwmgr             430 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			hwmgr->thermal_controller.advanceFanControlParameters.ucTargetTemperature;
hwmgr             432 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit;
hwmgr             434 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit *
hwmgr             435 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			hwmgr->thermal_controller.fanInfo.ulMaxRPM / 100;
hwmgr             437 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	if (hwmgr->feature_mask & PP_GFXOFF_MASK)
hwmgr             445 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_init_sclk_threshold(struct pp_hwmgr *hwmgr)
hwmgr             448 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			(struct vega12_hwmgr *)(hwmgr->backend);
hwmgr             455 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_setup_asic_task(struct pp_hwmgr *hwmgr)
hwmgr             457 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	PP_ASSERT_WITH_CODE(!vega12_init_sclk_threshold(hwmgr),
hwmgr             479 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_get_number_of_dpm_level(struct pp_hwmgr *hwmgr,
hwmgr             484 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	ret = smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             491 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	*num_of_levels = smum_get_argument(hwmgr);
hwmgr             499 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_get_dpm_frequency_by_index(struct pp_hwmgr *hwmgr,
hwmgr             508 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             513 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	*clock = smum_get_argument(hwmgr);
hwmgr             518 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_setup_single_dpm_table(struct pp_hwmgr *hwmgr,
hwmgr             524 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	ret = vega12_get_number_of_dpm_level(hwmgr, clk_id, &num_of_levels);
hwmgr             532 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		ret = vega12_get_dpm_frequency_by_index(hwmgr, clk_id, i, &clk);
hwmgr             551 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
hwmgr             555 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			(struct vega12_hwmgr *)(hwmgr->backend);
hwmgr             564 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_SOCCLK);
hwmgr             577 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_GFXCLK);
hwmgr             590 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_UCLK);
hwmgr             603 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_ECLK);
hwmgr             616 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_VCLK);
hwmgr             629 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCLK);
hwmgr             642 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCEFCLK);
hwmgr             655 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PIXCLK);
hwmgr             666 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DISPCLK);
hwmgr             677 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PHYCLK);
hwmgr             693 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_save_default_power_profile(struct pp_hwmgr *hwmgr)
hwmgr             695 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
hwmgr             699 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	hwmgr->default_gfx_power_profile.type = AMD_PP_GFX_PROFILE;
hwmgr             700 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	hwmgr->default_compute_power_profile.type = AMD_PP_COMPUTE_PROFILE;
hwmgr             712 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	hwmgr->default_compute_power_profile.min_sclk =
hwmgr             715 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	hwmgr->gfx_power_profile = hwmgr->default_gfx_power_profile;
hwmgr             716 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	hwmgr->compute_power_profile = hwmgr->default_compute_power_profile;
hwmgr             729 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_init_smc_table(struct pp_hwmgr *hwmgr)
hwmgr             733 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			(struct vega12_hwmgr *)(hwmgr->backend);
hwmgr             737 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		(struct phm_ppt_v3_information *)hwmgr->pptable;
hwmgr             739 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values);
hwmgr             752 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             759 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	result = smum_smc_table_manager(hwmgr,
hwmgr             767 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_run_acg_btc(struct pp_hwmgr *hwmgr)
hwmgr             772 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgBtc) == 0,
hwmgr             776 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	result = smum_get_argument(hwmgr);
hwmgr             783 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_set_allowed_featuresmask(struct pp_hwmgr *hwmgr)
hwmgr             786 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			(struct vega12_hwmgr *)(hwmgr->backend);
hwmgr             797 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetAllowedFeaturesMaskHigh, allowed_features_high) == 0,
hwmgr             802 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetAllowedFeaturesMaskLow, allowed_features_low) == 0,
hwmgr             809 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static void vega12_init_powergate_state(struct pp_hwmgr *hwmgr)
hwmgr             812 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			(struct vega12_hwmgr *)(hwmgr->backend);
hwmgr             824 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_enable_all_smu_features(struct pp_hwmgr *hwmgr)
hwmgr             827 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			(struct vega12_hwmgr *)(hwmgr->backend);
hwmgr             833 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAllSmuFeatures) == 0,
hwmgr             837 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	if (vega12_get_enabled_smc_features(hwmgr, &features_enabled) == 0) {
hwmgr             845 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	vega12_init_powergate_state(hwmgr);
hwmgr             850 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_disable_all_smu_features(struct pp_hwmgr *hwmgr)
hwmgr             853 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			(struct vega12_hwmgr *)(hwmgr->backend);
hwmgr             859 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableAllSmuFeatures) == 0,
hwmgr             863 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	if (vega12_get_enabled_smc_features(hwmgr, &features_enabled) == 0) {
hwmgr             875 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		struct pp_hwmgr *hwmgr)
hwmgr             880 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_set_overdrive_target_percentage(struct pp_hwmgr *hwmgr,
hwmgr             883 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	return smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             887 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_power_control_set_level(struct pp_hwmgr *hwmgr)
hwmgr             893 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 				hwmgr->platform_descriptor.TDPAdjustmentPolarity ?
hwmgr             894 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 				hwmgr->platform_descriptor.TDPAdjustment :
hwmgr             895 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 				(-1 * hwmgr->platform_descriptor.TDPAdjustment);
hwmgr             896 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		result = vega12_set_overdrive_target_percentage(hwmgr,
hwmgr             902 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_get_all_clock_ranges_helper(struct pp_hwmgr *hwmgr,
hwmgr             907 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetMaxDpmFreq, (clkid << 16)) == 0,
hwmgr             910 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	clock->ACMax = smum_get_argument(hwmgr);
hwmgr             914 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetMinDpmFreq, (clkid << 16)) == 0,
hwmgr             917 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	clock->ACMin = smum_get_argument(hwmgr);
hwmgr             921 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetDcModeMaxDpmFreq, (clkid << 16)) == 0,
hwmgr             924 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	clock->DCMax = smum_get_argument(hwmgr);
hwmgr             929 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_get_all_clock_ranges(struct pp_hwmgr *hwmgr)
hwmgr             932 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			(struct vega12_hwmgr *)(hwmgr->backend);
hwmgr             936 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		PP_ASSERT_WITH_CODE(!vega12_get_all_clock_ranges_helper(hwmgr,
hwmgr             944 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
hwmgr             948 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             951 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	result = vega12_set_allowed_featuresmask(hwmgr);
hwmgr             956 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	tmp_result = vega12_init_smc_table(hwmgr);
hwmgr             961 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	tmp_result = vega12_run_acg_btc(hwmgr);
hwmgr             966 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	result = vega12_enable_all_smu_features(hwmgr);
hwmgr             971 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	tmp_result = vega12_power_control_set_level(hwmgr);
hwmgr             976 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	result = vega12_get_all_clock_ranges(hwmgr);
hwmgr             981 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	result = vega12_odn_initialize_default_settings(hwmgr);
hwmgr             986 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	result = vega12_setup_default_dpm_tables(hwmgr);
hwmgr             993 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_patch_boot_state(struct pp_hwmgr *hwmgr,
hwmgr            1038 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_upload_dpm_min_level(struct pp_hwmgr *hwmgr)
hwmgr            1040 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	struct vega12_hwmgr *data = hwmgr->backend;
hwmgr            1047 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 					hwmgr, PPSMC_MSG_SetSoftMinByFreq,
hwmgr            1056 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 					hwmgr, PPSMC_MSG_SetSoftMinByFreq,
hwmgr            1063 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 					hwmgr, PPSMC_MSG_SetHardMinByFreq,
hwmgr            1073 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 					hwmgr, PPSMC_MSG_SetSoftMinByFreq,
hwmgr            1081 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 					hwmgr, PPSMC_MSG_SetSoftMinByFreq,
hwmgr            1091 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 					hwmgr, PPSMC_MSG_SetSoftMinByFreq,
hwmgr            1101 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 					hwmgr, PPSMC_MSG_SetSoftMinByFreq,
hwmgr            1111 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 					hwmgr, PPSMC_MSG_SetHardMinByFreq,
hwmgr            1121 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
hwmgr            1123 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	struct vega12_hwmgr *data = hwmgr->backend;
hwmgr            1131 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 					hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
hwmgr            1141 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 					hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
hwmgr            1151 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 					hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
hwmgr            1158 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 					hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
hwmgr            1168 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 					hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
hwmgr            1178 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 					hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
hwmgr            1187 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c int vega12_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
hwmgr            1190 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			(struct vega12_hwmgr *)(hwmgr->backend);
hwmgr            1193 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(hwmgr,
hwmgr            1204 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static uint32_t vega12_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
hwmgr            1207 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			(struct vega12_hwmgr *)(hwmgr->backend);
hwmgr            1215 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			vega12_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, false) == 0,
hwmgr            1220 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			vega12_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, true) == 0,
hwmgr            1227 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static uint32_t vega12_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
hwmgr            1230 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			(struct vega12_hwmgr *)(hwmgr->backend);
hwmgr            1238 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			vega12_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, false) == 0,
hwmgr            1243 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			vega12_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, true) == 0,
hwmgr            1250 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_get_metrics_table(struct pp_hwmgr *hwmgr, SmuMetrics_t *metrics_table)
hwmgr            1253 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			(struct vega12_hwmgr *)(hwmgr->backend);
hwmgr            1257 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		ret = smum_smc_table_manager(hwmgr, (uint8_t *)metrics_table,
hwmgr            1271 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_get_gpu_power(struct pp_hwmgr *hwmgr, uint32_t *query)
hwmgr            1276 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	ret = vega12_get_metrics_table(hwmgr, &metrics_table);
hwmgr            1285 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_get_current_gfx_clk_freq(struct pp_hwmgr *hwmgr, uint32_t *gfx_freq)
hwmgr            1291 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            1295 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	gfx_clk = smum_get_argument(hwmgr);
hwmgr            1302 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_get_current_mclk_freq(struct pp_hwmgr *hwmgr, uint32_t *mclk_freq)
hwmgr            1309 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetDpmClockFreq, (PPCLK_UCLK << 16)) == 0,
hwmgr            1312 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	mem_clk = smum_get_argument(hwmgr);
hwmgr            1320 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		struct pp_hwmgr *hwmgr,
hwmgr            1327 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	ret = vega12_get_metrics_table(hwmgr, &metrics_table);
hwmgr            1346 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_read_sensor(struct pp_hwmgr *hwmgr, int idx,
hwmgr            1349 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
hwmgr            1355 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		ret = vega12_get_current_gfx_clk_freq(hwmgr, (uint32_t *)value);
hwmgr            1360 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		ret = vega12_get_current_mclk_freq(hwmgr, (uint32_t *)value);
hwmgr            1366 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		ret = vega12_get_current_activity_percent(hwmgr, idx, (uint32_t *)value);
hwmgr            1371 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		*((uint32_t *)value) = vega12_thermal_get_temperature(hwmgr);
hwmgr            1375 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		ret = vega12_get_metrics_table(hwmgr, &metrics_table);
hwmgr            1384 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		ret = vega12_get_metrics_table(hwmgr, &metrics_table);
hwmgr            1401 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		ret = vega12_get_gpu_power(hwmgr, (uint32_t *)value);
hwmgr            1406 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		ret = vega12_get_enabled_smc_features(hwmgr, (uint64_t *)value);
hwmgr            1417 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_notify_smc_display_change(struct pp_hwmgr *hwmgr,
hwmgr            1420 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
hwmgr            1423 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		return smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            1430 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c int vega12_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
hwmgr            1434 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
hwmgr            1462 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			result = smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            1472 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		struct pp_hwmgr *hwmgr)
hwmgr            1475 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			(struct vega12_hwmgr *)(hwmgr->backend);
hwmgr            1479 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	if ((hwmgr->display_config->num_display > 1) &&
hwmgr            1480 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	     !hwmgr->display_config->multi_monitor_in_sync &&
hwmgr            1481 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	     !hwmgr->display_config->nb_pstate_switch_disable)
hwmgr            1482 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		vega12_notify_smc_display_change(hwmgr, false);
hwmgr            1484 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		vega12_notify_smc_display_change(hwmgr, true);
hwmgr            1486 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
hwmgr            1487 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
hwmgr            1488 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
hwmgr            1493 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		if (!vega12_display_clock_voltage_request(hwmgr, &clock_req)) {
hwmgr            1497 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 					hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk,
hwmgr            1509 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_force_dpm_highest(struct pp_hwmgr *hwmgr)
hwmgr            1512 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			(struct vega12_hwmgr *)(hwmgr->backend);
hwmgr            1528 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr),
hwmgr            1532 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr),
hwmgr            1539 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_force_dpm_lowest(struct pp_hwmgr *hwmgr)
hwmgr            1542 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			(struct vega12_hwmgr *)(hwmgr->backend);
hwmgr            1557 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr),
hwmgr            1561 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr),
hwmgr            1569 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
hwmgr            1571 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr),
hwmgr            1575 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr),
hwmgr            1582 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level,
hwmgr            1585 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
hwmgr            1615 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static void vega12_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
hwmgr            1622 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			vega12_fan_ctrl_stop_smc_fan_control(hwmgr);
hwmgr            1626 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			vega12_fan_ctrl_start_smc_fan_control(hwmgr);
hwmgr            1633 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
hwmgr            1643 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		ret = vega12_force_dpm_highest(hwmgr);
hwmgr            1646 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		ret = vega12_force_dpm_lowest(hwmgr);
hwmgr            1649 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		ret = vega12_unforce_dpm_levels(hwmgr);
hwmgr            1655 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		ret = vega12_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
hwmgr            1658 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		vega12_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask);
hwmgr            1659 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		vega12_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask);
hwmgr            1670 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static uint32_t vega12_get_fan_control_mode(struct pp_hwmgr *hwmgr)
hwmgr            1672 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
hwmgr            1680 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_get_dal_power_level(struct pp_hwmgr *hwmgr,
hwmgr            1685 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			(struct phm_ppt_v2_information *)hwmgr->pptable;
hwmgr            1695 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_get_clock_ranges(struct pp_hwmgr *hwmgr,
hwmgr            1700 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
hwmgr            1710 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_get_sclks(struct pp_hwmgr *hwmgr,
hwmgr            1713 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
hwmgr            1737 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static uint32_t vega12_get_mem_latency(struct pp_hwmgr *hwmgr,
hwmgr            1743 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_get_memclocks(struct pp_hwmgr *hwmgr,
hwmgr            1746 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
hwmgr            1762 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			vega12_get_mem_latency(hwmgr, dpm_table->dpm_levels[i].value);
hwmgr            1770 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_get_dcefclocks(struct pp_hwmgr *hwmgr,
hwmgr            1773 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
hwmgr            1798 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_get_socclocks(struct pp_hwmgr *hwmgr,
hwmgr            1801 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
hwmgr            1827 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
hwmgr            1835 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		ret = vega12_get_sclks(hwmgr, clocks);
hwmgr            1838 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		ret = vega12_get_memclocks(hwmgr, clocks);
hwmgr            1841 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		ret = vega12_get_dcefclocks(hwmgr, clocks);
hwmgr            1844 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		ret = vega12_get_socclocks(hwmgr, clocks);
hwmgr            1853 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
hwmgr            1862 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
hwmgr            1865 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
hwmgr            1880 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_force_clock_level(struct pp_hwmgr *hwmgr,
hwmgr            1883 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
hwmgr            1897 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		ret = vega12_upload_dpm_min_level(hwmgr);
hwmgr            1902 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		ret = vega12_upload_dpm_max_level(hwmgr);
hwmgr            1917 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		ret = vega12_upload_dpm_min_level(hwmgr);
hwmgr            1922 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		ret = vega12_upload_dpm_max_level(hwmgr);
hwmgr            1945 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		ret = vega12_upload_dpm_min_level(hwmgr);
hwmgr            1950 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		ret = vega12_upload_dpm_max_level(hwmgr);
hwmgr            1970 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		ret = vega12_upload_dpm_min_level(hwmgr);
hwmgr            1989 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf)
hwmgr            2030 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	ret = vega12_get_enabled_smc_features(hwmgr, &features_enabled);
hwmgr            2050 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfeature_masks)
hwmgr            2060 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	ret = vega12_get_enabled_smc_features(hwmgr, &features_enabled);
hwmgr            2073 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		ret = vega12_enable_smc_features(hwmgr, false, features_to_disable);
hwmgr            2079 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		ret = vega12_enable_smc_features(hwmgr, true, features_to_enable);
hwmgr            2087 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_print_clock_levels(struct pp_hwmgr *hwmgr,
hwmgr            2096 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 				vega12_get_current_gfx_clk_freq(hwmgr, &now) == 0,
hwmgr            2101 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 				vega12_get_sclks(hwmgr, &clocks) == 0,
hwmgr            2112 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 				vega12_get_current_mclk_freq(hwmgr, &now) == 0,
hwmgr            2117 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 				vega12_get_memclocks(hwmgr, &clocks) == 0,
hwmgr            2128 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 				smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            2132 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		now = smum_get_argument(hwmgr);
hwmgr            2135 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 				vega12_get_socclocks(hwmgr, &clocks) == 0,
hwmgr            2146 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 				smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            2150 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		now = smum_get_argument(hwmgr);
hwmgr            2153 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 				vega12_get_dcefclocks(hwmgr, &clocks) == 0,
hwmgr            2171 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr)
hwmgr            2173 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
hwmgr            2179 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
hwmgr            2180 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			          !hwmgr->display_config->multi_monitor_in_sync) ||
hwmgr            2182 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
hwmgr            2197 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
hwmgr            2202 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
hwmgr            2221 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
hwmgr            2226 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
hwmgr            2233 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100))
hwmgr            2234 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100;
hwmgr            2241 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 				if (dpm_table->dpm_levels[i].value >= (hwmgr->display_config->min_mem_set_clock / 100)) {
hwmgr            2249 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	if (hwmgr->display_config->nb_pstate_switch_disable)
hwmgr            2265 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
hwmgr            2284 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
hwmgr            2303 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
hwmgr            2322 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
hwmgr            2331 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr,
hwmgr            2334 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
hwmgr            2346 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            2356 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_pre_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
hwmgr            2358 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
hwmgr            2361 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            2364 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	ret = vega12_set_uclk_to_highest_dpm_level(hwmgr,
hwmgr            2370 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
hwmgr            2372 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
hwmgr            2378 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		result = smum_smc_table_manager(hwmgr,
hwmgr            2387 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            2388 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			PPSMC_MSG_NumOfDisplays, hwmgr->display_config->num_display);
hwmgr            2393 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c int vega12_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
hwmgr            2396 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			(struct vega12_hwmgr *)(hwmgr->backend);
hwmgr            2399 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(hwmgr,
hwmgr            2410 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static void vega12_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
hwmgr            2412 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
hwmgr            2418 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	vega12_enable_disable_vce_dpm(hwmgr, !bgate);
hwmgr            2421 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static void vega12_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
hwmgr            2423 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
hwmgr            2429 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	vega12_enable_disable_uvd_dpm(hwmgr, !bgate);
hwmgr            2433 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c vega12_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
hwmgr            2435 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
hwmgr            2438 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
hwmgr            2442 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr)
hwmgr            2449 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
hwmgr            2453 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	tmp_result = vega12_disable_all_smu_features(hwmgr);
hwmgr            2460 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_power_off_asic(struct pp_hwmgr *hwmgr)
hwmgr            2462 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
hwmgr            2465 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	result = vega12_disable_dpm_tasks(hwmgr);
hwmgr            2475 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static void vega12_find_min_clock_index(struct pp_hwmgr *hwmgr,
hwmgr            2479 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
hwmgr            2502 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_set_power_profile_state(struct pp_hwmgr *hwmgr,
hwmgr            2508 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_get_sclk_od(struct pp_hwmgr *hwmgr)
hwmgr            2510 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
hwmgr            2524 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
hwmgr            2529 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_get_mclk_od(struct pp_hwmgr *hwmgr)
hwmgr            2531 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
hwmgr            2545 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
hwmgr            2551 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
hwmgr            2558 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            2561 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            2564 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            2568 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            2572 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            2578 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
hwmgr            2582 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			(struct vega12_hwmgr *)(hwmgr->backend);
hwmgr            2603 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_enable_gfx_off(struct pp_hwmgr *hwmgr)
hwmgr            2606 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			(struct vega12_hwmgr *)(hwmgr->backend);
hwmgr            2610 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_AllowGfxOff);
hwmgr            2615 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_disable_gfx_off(struct pp_hwmgr *hwmgr)
hwmgr            2618 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 			(struct vega12_hwmgr *)(hwmgr->backend);
hwmgr            2622 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisallowGfxOff);
hwmgr            2627 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable)
hwmgr            2630 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		return vega12_enable_gfx_off(hwmgr);
hwmgr            2632 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 		return vega12_disable_gfx_off(hwmgr);
hwmgr            2635 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
hwmgr            2642 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c static int vega12_set_mp1_state(struct pp_hwmgr *hwmgr,
hwmgr            2659 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, msg)) == 0,
hwmgr            2725 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c int vega12_hwmgr_init(struct pp_hwmgr *hwmgr)
hwmgr            2727 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	hwmgr->hwmgr_func = &vega12_hwmgr_funcs;
hwmgr            2728 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 	hwmgr->pptable_func = &vega12_pptable_funcs;
hwmgr             455 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h int vega12_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable);
hwmgr              35 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c static void set_hw_cap(struct pp_hwmgr *hwmgr, bool enable,
hwmgr              39 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps, cap);
hwmgr              41 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps, cap);
hwmgr              44 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c static const void *get_powerplay_table(struct pp_hwmgr *hwmgr)
hwmgr              50 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c 	const void *table_address = hwmgr->soft_pp_table;
hwmgr              54 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c 				smu_atom_get_data_table(hwmgr->adev, index,
hwmgr              57 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c 		hwmgr->soft_pp_table = table_address;	/*Cache the result in RAM.*/
hwmgr              58 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c 		hwmgr->soft_pp_table_size = size;
hwmgr              65 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c 		struct pp_hwmgr *hwmgr,
hwmgr              77 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c static int set_platform_caps(struct pp_hwmgr *hwmgr, uint32_t powerplay_caps)
hwmgr              80 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c 			hwmgr,
hwmgr              85 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c 			hwmgr,
hwmgr              90 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c 			hwmgr,
hwmgr              95 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c 			hwmgr,
hwmgr             102 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c static int append_vbios_pptable(struct pp_hwmgr *hwmgr, PPTable_t *ppsmc_pptable)
hwmgr             107 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c 		pp_atomfwctrl_get_smc_dpm_information(hwmgr, &smc_dpm_table) == 0,
hwmgr             192 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c 		struct pp_hwmgr *hwmgr,
hwmgr             196 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c 		(struct phm_ppt_v3_information *)hwmgr->pptable;
hwmgr             200 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c 	hwmgr->thermal_controller.ucType = powerplay_table->ucThermalControllerType;
hwmgr             203 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c 	set_hw_cap(hwmgr,
hwmgr             204 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c 		ATOM_VEGA12_PP_THERMALCONTROLLER_NONE != hwmgr->thermal_controller.ucType,
hwmgr             207 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl);
hwmgr             210 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c 		hwmgr->platform_descriptor.overdriveLimit.engineClock = VEGA12_ENGINECLOCK_HARDMAX;
hwmgr             212 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c 		hwmgr->platform_descriptor.overdriveLimit.engineClock =
hwmgr             214 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c 	hwmgr->platform_descriptor.overdriveLimit.memoryClock =
hwmgr             217 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c 	phm_copy_overdrive_settings_limits_array(hwmgr,
hwmgr             221 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c 	phm_copy_overdrive_settings_limits_array(hwmgr,
hwmgr             230 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c 	if (hwmgr->platform_descriptor.overdriveLimit.engineClock > 0
hwmgr             231 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c 		&& hwmgr->platform_descriptor.overdriveLimit.memoryClock > 0)
hwmgr             232 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ACOverdriveSupport);
hwmgr             242 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c 	hwmgr->platform_descriptor.TDPODLimit = le32_to_cpu(powerplay_table->ODSettingsMax[ATOM_VEGA12_ODSETTING_POWERPERCENTAGE]);
hwmgr             247 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c 		if (hwmgr->platform_descriptor.TDPODLimit)
hwmgr             248 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c 			phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             252 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c 	phm_copy_clock_limits_array(hwmgr, &pptable_information->power_saving_clock_max, powerplay_table->PowerSavingClockMax, ATOM_VEGA12_PPCLOCK_COUNT);
hwmgr             253 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c 	phm_copy_clock_limits_array(hwmgr, &pptable_information->power_saving_clock_min, powerplay_table->PowerSavingClockMin, ATOM_VEGA12_PPCLOCK_COUNT);
hwmgr             261 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c 	result = append_vbios_pptable(hwmgr, (pptable_information->smc_pptable));
hwmgr             266 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c int vega12_pp_tables_initialize(struct pp_hwmgr *hwmgr)
hwmgr             271 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c 	hwmgr->pptable = kzalloc(sizeof(struct phm_ppt_v3_information), GFP_KERNEL);
hwmgr             272 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c 	PP_ASSERT_WITH_CODE((hwmgr->pptable != NULL),
hwmgr             275 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c 	powerplay_table = get_powerplay_table(hwmgr);
hwmgr             279 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c 	result = check_powerplay_tables(hwmgr, powerplay_table);
hwmgr             283 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c 	result = set_platform_caps(hwmgr,
hwmgr             288 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c 	result = init_powerplay_table_information(hwmgr, powerplay_table);
hwmgr             295 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c static int vega12_pp_tables_uninitialize(struct pp_hwmgr *hwmgr)
hwmgr             298 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c 			(struct phm_ppt_v3_information *)(hwmgr->pptable);
hwmgr             315 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c 	kfree(hwmgr->pptable);
hwmgr             316 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c 	hwmgr->pptable = NULL;
hwmgr             327 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c static uint32_t make_classification_flags(struct pp_hwmgr *hwmgr,
hwmgr             356 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c int vega12_get_powerplay_table_entry(struct pp_hwmgr *hwmgr,
hwmgr             365 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c 			get_powerplay_table(hwmgr);
hwmgr             389 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c 		result = call_back_func(hwmgr, (void *)state_entry, power_state,
hwmgr             391 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c 				make_classification_flags(hwmgr,
hwmgr             398 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c 		result = hwmgr->hwmgr_func->patch_boot_state(hwmgr, &(power_state->hardware));
hwmgr              32 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c static int vega12_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm)
hwmgr              34 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c 	PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
hwmgr              38 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c 	*current_rpm = smum_get_argument(hwmgr);
hwmgr              43 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c int vega12_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr,
hwmgr              55 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c int vega12_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed)
hwmgr              59 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c 	return vega12_get_current_rpm(hwmgr, speed);
hwmgr              69 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c static int vega12_enable_fan_control_feature(struct pp_hwmgr *hwmgr)
hwmgr              72 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
hwmgr              76 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c 				hwmgr, true,
hwmgr              87 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c static int vega12_disable_fan_control_feature(struct pp_hwmgr *hwmgr)
hwmgr              90 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
hwmgr              94 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c 				hwmgr, false,
hwmgr             105 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c int vega12_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
hwmgr             107 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
hwmgr             111 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c 				!vega12_enable_fan_control_feature(hwmgr),
hwmgr             119 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c int vega12_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr)
hwmgr             121 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
hwmgr             124 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c 		PP_ASSERT_WITH_CODE(!vega12_disable_fan_control_feature(hwmgr),
hwmgr             136 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c int vega12_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr)
hwmgr             138 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c 	return vega12_fan_ctrl_start_smc_fan_control(hwmgr);
hwmgr             146 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c int vega12_thermal_get_temperature(struct pp_hwmgr *hwmgr)
hwmgr             148 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             170 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c static int vega12_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
hwmgr             173 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             206 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c static int vega12_thermal_enable_alert(struct pp_hwmgr *hwmgr)
hwmgr             208 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             224 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c int vega12_thermal_disable_alert(struct pp_hwmgr *hwmgr)
hwmgr             226 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             238 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c int vega12_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr)
hwmgr             240 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c 	int result = vega12_thermal_disable_alert(hwmgr);
hwmgr             254 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c int vega12_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
hwmgr             257 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c 	struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
hwmgr             260 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c 	ret = smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             276 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c int vega12_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr)
hwmgr             284 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c 		vega12_fan_ctrl_start_smc_fan_control(hwmgr);
hwmgr             290 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c int vega12_start_thermal_controller(struct pp_hwmgr *hwmgr,
hwmgr             298 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c 	ret = vega12_thermal_set_temperature_range(hwmgr, range);
hwmgr             302 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c 	vega12_thermal_enable_alert(hwmgr);
hwmgr             308 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c 	ret = vega12_thermal_setup_fan_table(hwmgr);
hwmgr             312 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.c 	vega12_thermal_start_smc_fan_control(hwmgr);
hwmgr              52 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.h extern int vega12_thermal_get_temperature(struct pp_hwmgr *hwmgr);
hwmgr              53 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.h extern int vega12_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr);
hwmgr              54 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.h extern int vega12_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr,
hwmgr              56 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.h extern int vega12_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr);
hwmgr              57 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.h extern int vega12_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr,
hwmgr              59 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.h extern int vega12_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr);
hwmgr              60 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.h extern int vega12_thermal_disable_alert(struct pp_hwmgr *hwmgr);
hwmgr              61 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.h extern int vega12_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr);
hwmgr              62 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_thermal.h extern int vega12_start_thermal_controller(struct pp_hwmgr *hwmgr,
hwmgr              40 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c int vega20_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)
hwmgr              42 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c 	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
hwmgr              46 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c 	if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))
hwmgr              59 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c int vega20_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)
hwmgr              61 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c 	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
hwmgr              74 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c int vega20_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
hwmgr              76 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c 	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
hwmgr              81 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c 	vega20_baco_get_state(hwmgr, &cur_state);
hwmgr              94 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c 		if(smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_EnterBaco, 0))
hwmgr              98 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c 		if (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ExitBaco))
hwmgr             100 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c 		if (!soc15_baco_program_registers(hwmgr, clean_baco_tbl,
hwmgr             108 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c int vega20_baco_apply_vdci_flush_workaround(struct pp_hwmgr *hwmgr)
hwmgr             112 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c 	ret = vega20_set_pptable_driver_address(hwmgr);
hwmgr             116 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c 	return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_BacoWorkAroundFlushVDCI);
hwmgr              28 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.h extern int vega20_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap);
hwmgr              29 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.h extern int vega20_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);
hwmgr              30 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.h extern int vega20_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state);
hwmgr              31 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.h extern int vega20_baco_apply_vdci_flush_workaround(struct pp_hwmgr *hwmgr);
hwmgr              58 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static void vega20_set_default_registry_data(struct pp_hwmgr *hwmgr)
hwmgr              61 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			(struct vega20_hwmgr *)(hwmgr->backend);
hwmgr              95 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion);
hwmgr              96 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	hwmgr->smu_version = smum_get_argument(hwmgr);
hwmgr              97 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	if (hwmgr->smu_version < 0x282100)
hwmgr             100 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	if (!(hwmgr->feature_mask & PP_PCIE_DPM_MASK))
hwmgr             103 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	if (!(hwmgr->feature_mask & PP_SCLK_DPM_MASK))
hwmgr             106 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	if (!(hwmgr->feature_mask & PP_SOCCLK_DPM_MASK))
hwmgr             109 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	if (!(hwmgr->feature_mask & PP_MCLK_DPM_MASK))
hwmgr             112 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	if (!(hwmgr->feature_mask & PP_DCEFCLK_DPM_MASK))
hwmgr             115 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	if (!(hwmgr->feature_mask & PP_ULV_MASK))
hwmgr             118 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	if (!(hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK))
hwmgr             172 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_set_features_platform_caps(struct pp_hwmgr *hwmgr)
hwmgr             175 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			(struct vega20_hwmgr *)(hwmgr->backend);
hwmgr             176 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             179 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             182 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             185 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             189 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             193 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             196 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             200 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             203 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             205 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             210 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             216 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	    hwmgr->thermal_controller.advanceFanControlParameters.usTMax)
hwmgr             217 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             220 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             222 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             224 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             228 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             231 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             235 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             240 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             242 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             244 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             246 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             248 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             250 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             252 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             254 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             256 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             258 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             262 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             265 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             268 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             271 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             274 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             277 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             280 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             283 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             286 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             290 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             294 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             296 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             301 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             303 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             305 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             310 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr             313 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             318 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             324 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static void vega20_init_dpm_defaults(struct pp_hwmgr *hwmgr)
hwmgr             326 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
hwmgr             327 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             400 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32);
hwmgr             401 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	top32 = smum_get_argument(hwmgr);
hwmgr             402 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32);
hwmgr             403 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	bottom32 = smum_get_argument(hwmgr);
hwmgr             408 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
hwmgr             413 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
hwmgr             415 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	kfree(hwmgr->backend);
hwmgr             416 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	hwmgr->backend = NULL;
hwmgr             421 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
hwmgr             424 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             430 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	hwmgr->backend = data;
hwmgr             432 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
hwmgr             433 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
hwmgr             434 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
hwmgr             436 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	vega20_set_default_registry_data(hwmgr);
hwmgr             448 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	vega20_set_features_platform_caps(hwmgr);
hwmgr             450 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	vega20_init_dpm_defaults(hwmgr);
hwmgr             453 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	vega20_set_private_data_based_on_pptable(hwmgr);
hwmgr             457 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
hwmgr             459 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
hwmgr             460 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
hwmgr             462 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
hwmgr             464 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	hwmgr->platform_descriptor.clockStep.engineClock = 500;
hwmgr             465 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	hwmgr->platform_descriptor.clockStep.memoryClock = 500;
hwmgr             473 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_init_sclk_threshold(struct pp_hwmgr *hwmgr)
hwmgr             476 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			(struct vega20_hwmgr *)(hwmgr->backend);
hwmgr             483 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_setup_asic_task(struct pp_hwmgr *hwmgr)
hwmgr             485 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
hwmgr             488 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	ret = vega20_init_sclk_threshold(hwmgr);
hwmgr             496 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_baco_apply_vdci_flush_workaround(hwmgr);
hwmgr             519 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_get_number_of_dpm_level(struct pp_hwmgr *hwmgr,
hwmgr             524 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	ret = smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             531 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	*num_of_levels = smum_get_argument(hwmgr);
hwmgr             539 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_get_dpm_frequency_by_index(struct pp_hwmgr *hwmgr,
hwmgr             544 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	ret = smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             551 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	*clk = smum_get_argument(hwmgr);
hwmgr             559 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_setup_single_dpm_table(struct pp_hwmgr *hwmgr,
hwmgr             565 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	ret = vega20_get_number_of_dpm_level(hwmgr, clk_id, &num_of_levels);
hwmgr             573 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_get_dpm_frequency_by_index(hwmgr, clk_id, i, &clk);
hwmgr             584 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_setup_gfxclk_dpm_table(struct pp_hwmgr *hwmgr)
hwmgr             587 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			(struct vega20_hwmgr *)(hwmgr->backend);
hwmgr             593 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_GFXCLK);
hwmgr             605 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_setup_memclk_dpm_table(struct pp_hwmgr *hwmgr)
hwmgr             608 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			(struct vega20_hwmgr *)(hwmgr->backend);
hwmgr             614 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_UCLK);
hwmgr             634 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
hwmgr             637 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			(struct vega20_hwmgr *)(hwmgr->backend);
hwmgr             646 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_SOCCLK);
hwmgr             658 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	ret = vega20_setup_gfxclk_dpm_table(hwmgr);
hwmgr             665 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	ret = vega20_setup_memclk_dpm_table(hwmgr);
hwmgr             673 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_ECLK);
hwmgr             686 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_VCLK);
hwmgr             699 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCLK);
hwmgr             712 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCEFCLK);
hwmgr             725 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PIXCLK);
hwmgr             736 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DISPCLK);
hwmgr             747 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PHYCLK);
hwmgr             758 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_FCLK);
hwmgr             782 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_init_smc_table(struct pp_hwmgr *hwmgr)
hwmgr             786 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			(struct vega20_hwmgr *)(hwmgr->backend);
hwmgr             790 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		(struct phm_ppt_v3_information *)hwmgr->pptable;
hwmgr             792 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values);
hwmgr             810 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             816 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	result = smum_smc_table_manager(hwmgr,
hwmgr             831 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_override_pcie_parameters(struct pp_hwmgr *hwmgr)
hwmgr             833 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
hwmgr             835 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			(struct vega20_hwmgr *)(hwmgr->backend);
hwmgr             866 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	ret = smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             879 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_set_allowed_featuresmask(struct pp_hwmgr *hwmgr)
hwmgr             882 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			(struct vega20_hwmgr *)(hwmgr->backend);
hwmgr             897 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	ret = smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             903 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	ret = smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             912 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_run_btc(struct pp_hwmgr *hwmgr)
hwmgr             914 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunBtc);
hwmgr             917 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_run_btc_afll(struct pp_hwmgr *hwmgr)
hwmgr             919 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAfllBtc);
hwmgr             922 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_enable_all_smu_features(struct pp_hwmgr *hwmgr)
hwmgr             925 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			(struct vega20_hwmgr *)(hwmgr->backend);
hwmgr             931 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr,
hwmgr             936 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
hwmgr             958 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_notify_smc_display_change(struct pp_hwmgr *hwmgr)
hwmgr             960 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
hwmgr             963 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		return smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             970 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_send_clock_ratio(struct pp_hwmgr *hwmgr)
hwmgr             973 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			(struct vega20_hwmgr *)(hwmgr->backend);
hwmgr             975 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	return smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             980 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_disable_all_smu_features(struct pp_hwmgr *hwmgr)
hwmgr             983 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			(struct vega20_hwmgr *)(hwmgr->backend);
hwmgr             989 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr,
hwmgr             994 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
hwmgr            1010 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		struct pp_hwmgr *hwmgr)
hwmgr            1013 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		(struct phm_ppt_v3_information *)hwmgr->pptable;
hwmgr            1014 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
hwmgr            1097 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		hwmgr->od_enabled = false;
hwmgr            1103 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		struct pp_hwmgr *hwmgr)
hwmgr            1105 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
hwmgr            1190 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		struct pp_hwmgr *hwmgr,
hwmgr            1196 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	ret = smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            1203 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	*voltage = smum_get_argument(hwmgr);
hwmgr            1210 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		struct pp_hwmgr *hwmgr)
hwmgr            1213 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		(struct phm_ppt_v3_information *)hwmgr->pptable;
hwmgr            1214 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
hwmgr            1220 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	vega20_od8_set_feature_capabilities(hwmgr);
hwmgr            1223 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	vega20_od8_set_feature_id(hwmgr);
hwmgr            1226 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE, true);
hwmgr            1256 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
hwmgr            1264 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
hwmgr            1272 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		PP_ASSERT_WITH_CODE(!vega20_od8_get_gfx_clock_base_voltage(hwmgr,
hwmgr            1354 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	ret = smum_smc_table_manager(hwmgr, (uint8_t *)od_table, TABLE_OVERDRIVE, false);
hwmgr            1363 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		struct pp_hwmgr *hwmgr,
hwmgr            1369 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
hwmgr            1373 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	ret = smum_smc_table_manager(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE, true);
hwmgr            1430 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	ret = smum_smc_table_manager(hwmgr, (uint8_t *)(&od_table), TABLE_OVERDRIVE, false);
hwmgr            1439 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		struct pp_hwmgr *hwmgr)
hwmgr            1441 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	struct vega20_hwmgr *data = hwmgr->backend;
hwmgr            1458 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		struct pp_hwmgr *hwmgr, uint32_t value)
hwmgr            1460 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	struct vega20_hwmgr *data = hwmgr->backend;
hwmgr            1470 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	ret = vega20_od8_set_settings(hwmgr, OD8_SETTING_GFXCLK_FMAX, od_sclk);
hwmgr            1476 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	ret = vega20_setup_gfxclk_dpm_table(hwmgr);
hwmgr            1485 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		struct pp_hwmgr *hwmgr)
hwmgr            1487 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	struct vega20_hwmgr *data = hwmgr->backend;
hwmgr            1504 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		struct pp_hwmgr *hwmgr, uint32_t value)
hwmgr            1506 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	struct vega20_hwmgr *data = hwmgr->backend;
hwmgr            1516 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	ret = vega20_od8_set_settings(hwmgr, OD8_SETTING_UCLK_FMAX, od_mclk);
hwmgr            1522 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	ret = vega20_setup_memclk_dpm_table(hwmgr);
hwmgr            1531 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		struct pp_hwmgr *hwmgr)
hwmgr            1533 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
hwmgr            1537 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	hwmgr->pstate_sclk = gfx_table->dpm_levels[0].value;
hwmgr            1538 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	hwmgr->pstate_mclk = mem_table->dpm_levels[0].value;
hwmgr            1542 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		hwmgr->pstate_sclk = gfx_table->dpm_levels[VEGA20_UMD_PSTATE_GFXCLK_LEVEL].value;
hwmgr            1543 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		hwmgr->pstate_mclk = mem_table->dpm_levels[VEGA20_UMD_PSTATE_MCLK_LEVEL].value;
hwmgr            1546 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	hwmgr->pstate_sclk = hwmgr->pstate_sclk * 100;
hwmgr            1547 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	hwmgr->pstate_mclk = hwmgr->pstate_mclk * 100;
hwmgr            1552 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_get_max_sustainable_clock(struct pp_hwmgr *hwmgr,
hwmgr            1557 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            1562 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	*clock = smum_get_argument(hwmgr);
hwmgr            1566 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            1571 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		*clock = smum_get_argument(hwmgr);
hwmgr            1577 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_init_max_sustainable_clocks(struct pp_hwmgr *hwmgr)
hwmgr            1580 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		(struct vega20_hwmgr *)(hwmgr->backend);
hwmgr            1593 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
hwmgr            1600 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
hwmgr            1607 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
hwmgr            1612 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
hwmgr            1617 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
hwmgr            1622 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		PP_ASSERT_WITH_CODE((ret = vega20_get_max_sustainable_clock(hwmgr,
hwmgr            1635 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_enable_mgpu_fan_boost(struct pp_hwmgr *hwmgr)
hwmgr            1639 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	result = smum_send_msg_to_smc(hwmgr,
hwmgr            1648 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static void vega20_init_powergate_state(struct pp_hwmgr *hwmgr)
hwmgr            1651 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		(struct vega20_hwmgr *)(hwmgr->backend);
hwmgr            1663 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
hwmgr            1667 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            1670 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	result = vega20_set_allowed_featuresmask(hwmgr);
hwmgr            1675 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	result = vega20_init_smc_table(hwmgr);
hwmgr            1680 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	result = vega20_run_btc(hwmgr);
hwmgr            1685 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	result = vega20_run_btc_afll(hwmgr);
hwmgr            1690 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	result = vega20_enable_all_smu_features(hwmgr);
hwmgr            1695 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	result = vega20_override_pcie_parameters(hwmgr);
hwmgr            1700 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	result = vega20_notify_smc_display_change(hwmgr);
hwmgr            1705 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	result = vega20_send_clock_ratio(hwmgr);
hwmgr            1711 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	vega20_init_powergate_state(hwmgr);
hwmgr            1713 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	result = vega20_setup_default_dpm_tables(hwmgr);
hwmgr            1718 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	result = vega20_init_max_sustainable_clocks(hwmgr);
hwmgr            1723 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	result = vega20_power_control_set_level(hwmgr);
hwmgr            1728 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	result = vega20_od8_initialize_default_settings(hwmgr);
hwmgr            1733 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	result = vega20_populate_umdpstate_clocks(hwmgr);
hwmgr            1738 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetPptLimit,
hwmgr            1743 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	hwmgr->power_limit =
hwmgr            1744 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		hwmgr->default_power_limit = smum_get_argument(hwmgr);
hwmgr            1793 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask)
hwmgr            1796 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			(struct vega20_hwmgr *)(hwmgr->backend);
hwmgr            1804 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 					hwmgr, PPSMC_MSG_SetSoftMinByFreq,
hwmgr            1814 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 					hwmgr, PPSMC_MSG_SetSoftMinByFreq,
hwmgr            1825 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 					hwmgr, PPSMC_MSG_SetSoftMinByFreq,
hwmgr            1833 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 					hwmgr, PPSMC_MSG_SetSoftMinByFreq,
hwmgr            1844 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 					hwmgr, PPSMC_MSG_SetSoftMinByFreq,
hwmgr            1855 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 					hwmgr, PPSMC_MSG_SetSoftMinByFreq,
hwmgr            1866 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 					hwmgr, PPSMC_MSG_SetSoftMinByFreq,
hwmgr            1877 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 					hwmgr, PPSMC_MSG_SetHardMinByFreq,
hwmgr            1886 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask)
hwmgr            1889 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			(struct vega20_hwmgr *)(hwmgr->backend);
hwmgr            1898 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 					hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
hwmgr            1909 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 					hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
hwmgr            1920 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 					hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
hwmgr            1927 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 					hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
hwmgr            1938 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 					hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
hwmgr            1949 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 					hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
hwmgr            1960 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 					hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
hwmgr            1969 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c int vega20_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
hwmgr            1972 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			(struct vega20_hwmgr *)(hwmgr->backend);
hwmgr            1983 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_enable_smc_features(hwmgr,
hwmgr            1995 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_get_clock_ranges(struct pp_hwmgr *hwmgr,
hwmgr            2004 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            2008 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		*clock = smum_get_argument(hwmgr);
hwmgr            2010 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            2015 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		*clock = smum_get_argument(hwmgr);
hwmgr            2021 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static uint32_t vega20_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
hwmgr            2024 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			(struct vega20_hwmgr *)(hwmgr->backend);
hwmgr            2033 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, false);
hwmgr            2038 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, true);
hwmgr            2047 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static uint32_t vega20_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
hwmgr            2050 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			(struct vega20_hwmgr *)(hwmgr->backend);
hwmgr            2059 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, false);
hwmgr            2064 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, true);
hwmgr            2073 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_get_metrics_table(struct pp_hwmgr *hwmgr, SmuMetrics_t *metrics_table)
hwmgr            2076 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			(struct vega20_hwmgr *)(hwmgr->backend);
hwmgr            2080 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = smum_smc_table_manager(hwmgr, (uint8_t *)metrics_table,
hwmgr            2094 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_get_gpu_power(struct pp_hwmgr *hwmgr,
hwmgr            2100 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	ret = vega20_get_metrics_table(hwmgr, &metrics_table);
hwmgr            2105 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	if (hwmgr->smu_version == 0x282e00)
hwmgr            2113 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_get_current_clk_freq(struct pp_hwmgr *hwmgr,
hwmgr            2120 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            2124 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	*clk_freq = smum_get_argument(hwmgr);
hwmgr            2131 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_get_current_activity_percent(struct pp_hwmgr *hwmgr,
hwmgr            2138 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	ret = vega20_get_metrics_table(hwmgr, &metrics_table);
hwmgr            2157 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_read_sensor(struct pp_hwmgr *hwmgr, int idx,
hwmgr            2160 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
hwmgr            2161 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr            2168 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_get_metrics_table(hwmgr, &metrics_table);
hwmgr            2176 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_get_current_clk_freq(hwmgr,
hwmgr            2184 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_get_current_activity_percent(hwmgr, idx, (uint32_t *)value);
hwmgr            2189 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		*((uint32_t *)value) = vega20_thermal_get_temperature(hwmgr);
hwmgr            2193 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_get_metrics_table(hwmgr, &metrics_table);
hwmgr            2202 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_get_metrics_table(hwmgr, &metrics_table);
hwmgr            2220 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_get_gpu_power(hwmgr, (uint32_t *)value);
hwmgr            2230 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_get_enabled_smc_features(hwmgr, (uint64_t *)value);
hwmgr            2241 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c int vega20_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
hwmgr            2245 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
hwmgr            2273 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			result = smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            2282 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
hwmgr            2290 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		struct pp_hwmgr *hwmgr)
hwmgr            2293 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			(struct vega20_hwmgr *)(hwmgr->backend);
hwmgr            2300 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
hwmgr            2301 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
hwmgr            2302 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
hwmgr            2307 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		if (!vega20_display_clock_voltage_request(hwmgr, &clock_req)) {
hwmgr            2310 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 					hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk,
hwmgr            2321 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            2331 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_force_dpm_highest(struct pp_hwmgr *hwmgr)
hwmgr            2334 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			(struct vega20_hwmgr *)(hwmgr->backend);
hwmgr            2356 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |
hwmgr            2363 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |
hwmgr            2373 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_force_dpm_lowest(struct pp_hwmgr *hwmgr)
hwmgr            2376 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			(struct vega20_hwmgr *)(hwmgr->backend);
hwmgr            2398 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |
hwmgr            2405 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |
hwmgr            2416 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
hwmgr            2419 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			(struct vega20_hwmgr *)(hwmgr->backend);
hwmgr            2456 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |
hwmgr            2463 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK |
hwmgr            2473 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level,
hwmgr            2476 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
hwmgr            2506 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_force_clock_level(struct pp_hwmgr *hwmgr,
hwmgr            2509 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
hwmgr            2530 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_GFXCLK_MASK);
hwmgr            2535 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_GFXCLK_MASK);
hwmgr            2557 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_UCLK_MASK);
hwmgr            2562 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_UCLK_MASK);
hwmgr            2585 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_SOCCLK_MASK);
hwmgr            2590 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_SOCCLK_MASK);
hwmgr            2613 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_FCLK_MASK);
hwmgr            2618 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_upload_dpm_max_level(hwmgr, FEATURE_DPM_FCLK_MASK);
hwmgr            2638 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_upload_dpm_min_level(hwmgr, FEATURE_DPM_DCEFCLK_MASK);
hwmgr            2654 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            2669 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
hwmgr            2677 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_force_dpm_highest(hwmgr);
hwmgr            2681 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_force_dpm_lowest(hwmgr);
hwmgr            2685 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_unforce_dpm_levels(hwmgr);
hwmgr            2692 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
hwmgr            2695 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		vega20_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask);
hwmgr            2696 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		vega20_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask);
hwmgr            2697 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		vega20_force_clock_level(hwmgr, PP_SOCCLK, 1 << soc_mask);
hwmgr            2709 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static uint32_t vega20_get_fan_control_mode(struct pp_hwmgr *hwmgr)
hwmgr            2711 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
hwmgr            2719 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static void vega20_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
hwmgr            2723 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		vega20_fan_ctrl_set_fan_speed_percent(hwmgr, 100);
hwmgr            2727 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			vega20_fan_ctrl_stop_smc_fan_control(hwmgr);
hwmgr            2731 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			vega20_fan_ctrl_start_smc_fan_control(hwmgr);
hwmgr            2738 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_get_dal_power_level(struct pp_hwmgr *hwmgr,
hwmgr            2743 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			(struct phm_ppt_v2_information *)hwmgr->pptable;
hwmgr            2754 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_get_sclks(struct pp_hwmgr *hwmgr,
hwmgr            2757 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
hwmgr            2776 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static uint32_t vega20_get_mem_latency(struct pp_hwmgr *hwmgr,
hwmgr            2782 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_get_memclocks(struct pp_hwmgr *hwmgr,
hwmgr            2785 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
hwmgr            2801 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			vega20_get_mem_latency(hwmgr, dpm_table->dpm_levels[i].value);
hwmgr            2807 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_get_dcefclocks(struct pp_hwmgr *hwmgr,
hwmgr            2810 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
hwmgr            2829 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_get_socclocks(struct pp_hwmgr *hwmgr,
hwmgr            2832 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
hwmgr            2852 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
hwmgr            2860 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_get_sclks(hwmgr, clocks);
hwmgr            2863 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_get_memclocks(hwmgr, clocks);
hwmgr            2866 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_get_dcefclocks(hwmgr, clocks);
hwmgr            2869 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_get_socclocks(hwmgr, clocks);
hwmgr            2878 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
hwmgr            2887 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
hwmgr            2890 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
hwmgr            2905 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
hwmgr            2910 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			(struct vega20_hwmgr *)(hwmgr->backend);
hwmgr            3076 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = smum_smc_table_manager(hwmgr,
hwmgr            3085 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = smum_smc_table_manager(hwmgr,
hwmgr            3096 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			ret = vega20_setup_gfxclk_dpm_table(hwmgr);
hwmgr            3105 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			ret = vega20_setup_memclk_dpm_table(hwmgr);
hwmgr            3118 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_set_mp1_state(struct pp_hwmgr *hwmgr,
hwmgr            3139 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, msg)) == 0,
hwmgr            3146 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf)
hwmgr            3192 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
hwmgr            3212 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfeature_masks)
hwmgr            3222 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
hwmgr            3235 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_enable_smc_features(hwmgr, false, features_to_disable);
hwmgr            3241 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_enable_smc_features(hwmgr, true, features_to_enable);
hwmgr            3249 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
hwmgr            3253 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			(struct vega20_hwmgr *)(hwmgr->backend);
hwmgr            3259 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		(struct phm_ppt_v3_information *)hwmgr->pptable;
hwmgr            3261 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr            3271 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_get_current_clk_freq(hwmgr, PPCLK_GFXCLK, &now);
hwmgr            3276 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		if (vega20_get_sclks(hwmgr, &clocks)) {
hwmgr            3289 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_get_current_clk_freq(hwmgr, PPCLK_UCLK, &now);
hwmgr            3294 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		if (vega20_get_memclocks(hwmgr, &clocks)) {
hwmgr            3307 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_get_current_clk_freq(hwmgr, PPCLK_SOCCLK, &now);
hwmgr            3312 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		if (vega20_get_socclocks(hwmgr, &clocks)) {
hwmgr            3325 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_get_current_clk_freq(hwmgr, PPCLK_FCLK, &now);
hwmgr            3337 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_get_current_clk_freq(hwmgr, PPCLK_DCEFCLK, &now);
hwmgr            3342 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		if (vega20_get_dcefclocks(hwmgr, &clocks)) {
hwmgr            3477 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr,
hwmgr            3480 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
hwmgr            3492 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            3502 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_set_fclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr)
hwmgr            3504 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
hwmgr            3517 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            3527 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_pre_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
hwmgr            3529 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
hwmgr            3532 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            3535 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	ret = vega20_set_uclk_to_highest_dpm_level(hwmgr,
hwmgr            3540 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	return vega20_set_fclk_to_highest_dpm_level(hwmgr);
hwmgr            3543 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
hwmgr            3545 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
hwmgr            3551 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		result = smum_smc_table_manager(hwmgr,
hwmgr            3562 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		result = smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            3564 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			hwmgr->display_config->num_display);
hwmgr            3570 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c int vega20_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
hwmgr            3573 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			(struct vega20_hwmgr *)(hwmgr->backend);
hwmgr            3584 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		ret = vega20_enable_smc_features(hwmgr,
hwmgr            3596 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static void vega20_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
hwmgr            3598 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
hwmgr            3605 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		vega20_enable_disable_vce_dpm(hwmgr, !bgate);
hwmgr            3606 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		amdgpu_device_ip_set_powergating_state(hwmgr->adev,
hwmgr            3610 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		amdgpu_device_ip_set_powergating_state(hwmgr->adev,
hwmgr            3613 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		vega20_enable_disable_vce_dpm(hwmgr, !bgate);
hwmgr            3618 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static void vega20_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
hwmgr            3620 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
hwmgr            3626 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	vega20_enable_disable_uvd_dpm(hwmgr, !bgate);
hwmgr            3629 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr)
hwmgr            3631 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
hwmgr            3638 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
hwmgr            3639 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c                            !hwmgr->display_config->multi_monitor_in_sync) ||
hwmgr            3641 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
hwmgr            3656 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
hwmgr            3661 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
hwmgr            3680 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
hwmgr            3685 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
hwmgr            3692 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100))
hwmgr            3693 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100;
hwmgr            3700 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 				if (dpm_table->dpm_levels[i].value >= (hwmgr->display_config->min_mem_set_clock / 100)) {
hwmgr            3708 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	if (hwmgr->display_config->nb_pstate_switch_disable)
hwmgr            3713 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	     hwmgr->display_config->min_mem_set_clock / 100 >= dpm_table->dpm_levels[dpm_table->count - 1].value)
hwmgr            3724 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	if (hwmgr->display_config->nb_pstate_switch_disable || disable_fclk_switching)
hwmgr            3740 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
hwmgr            3759 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
hwmgr            3778 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
hwmgr            3797 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
hwmgr            3807 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c vega20_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
hwmgr            3809 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
hwmgr            3813 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			hwmgr->display_config->num_display)
hwmgr            3818 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	    hwmgr->display_config->min_core_set_clock_in_sr))
hwmgr            3824 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
hwmgr            3828 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	ret = vega20_disable_all_smu_features(hwmgr);
hwmgr            3836 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_power_off_asic(struct pp_hwmgr *hwmgr)
hwmgr            3838 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
hwmgr            3841 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	result = vega20_disable_dpm_tasks(hwmgr);
hwmgr            3881 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
hwmgr            3918 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		result = vega20_get_activity_monitor_coeff(hwmgr,
hwmgr            3925 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			i, profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ");
hwmgr            3987 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
hwmgr            4000 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			(struct vega20_hwmgr *)(hwmgr->backend);
hwmgr            4006 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		result = vega20_get_activity_monitor_coeff(hwmgr,
hwmgr            4067 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 		result = vega20_set_activity_monitor_coeff(hwmgr,
hwmgr            4080 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetWorkloadMask,
hwmgr            4083 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	hwmgr->power_profile_mode = power_profile_mode;
hwmgr            4088 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
hwmgr            4095 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            4098 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            4101 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            4105 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            4109 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            4115 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
hwmgr            4119 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 			(struct vega20_hwmgr *)(hwmgr->backend);
hwmgr            4140 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c static int vega20_smu_i2c_bus_access(struct pp_hwmgr *hwmgr, bool acquire)
hwmgr            4145 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	if (!vega20_is_smc_ram_running(hwmgr))
hwmgr            4148 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	res = smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            4228 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c int vega20_hwmgr_init(struct pp_hwmgr *hwmgr)
hwmgr            4230 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	hwmgr->hwmgr_func = &vega20_hwmgr_funcs;
hwmgr            4231 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 	hwmgr->pptable_func = &vega20_pptable_funcs;
hwmgr              32 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_powertune.c int vega20_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
hwmgr              35 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_powertune.c 			(struct vega20_hwmgr *)(hwmgr->backend);
hwmgr              38 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_powertune.c 		return smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr              44 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_powertune.c int vega20_validate_power_level_request(struct pp_hwmgr *hwmgr,
hwmgr              47 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_powertune.c 	return (tdp_percentage_adjustment > hwmgr->platform_descriptor.TDPLimit) ? -1 : 0;
hwmgr              50 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_powertune.c static int vega20_set_overdrive_target_percentage(struct pp_hwmgr *hwmgr,
hwmgr              53 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_powertune.c 	return smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr              57 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_powertune.c int vega20_power_control_set_level(struct pp_hwmgr *hwmgr)
hwmgr              63 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_powertune.c 				hwmgr->platform_descriptor.TDPAdjustmentPolarity ?
hwmgr              64 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_powertune.c 				hwmgr->platform_descriptor.TDPAdjustment :
hwmgr              65 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_powertune.c 				(-1 * hwmgr->platform_descriptor.TDPAdjustment);
hwmgr              66 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_powertune.c 		result = vega20_set_overdrive_target_percentage(hwmgr,
hwmgr              26 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_powertune.h int vega20_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n);
hwmgr              27 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_powertune.h int vega20_power_control_set_level(struct pp_hwmgr *hwmgr);
hwmgr              28 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_powertune.h int vega20_validate_power_level_request(struct pp_hwmgr *hwmgr,
hwmgr              37 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c static void set_hw_cap(struct pp_hwmgr *hwmgr, bool enable,
hwmgr              41 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps, cap);
hwmgr              43 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps, cap);
hwmgr              46 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c static const void *get_powerplay_table(struct pp_hwmgr *hwmgr)
hwmgr              52 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c 	const void *table_address = hwmgr->soft_pp_table;
hwmgr              56 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c 				smu_atom_get_data_table(hwmgr->adev, index,
hwmgr              59 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c 		hwmgr->soft_pp_table = table_address;
hwmgr              60 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c 		hwmgr->soft_pp_table_size = size;
hwmgr             639 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c 		struct pp_hwmgr *hwmgr,
hwmgr             661 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c static int set_platform_caps(struct pp_hwmgr *hwmgr, uint32_t powerplay_caps)
hwmgr             664 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c 		hwmgr,
hwmgr             669 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c 		hwmgr,
hwmgr             674 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c 		hwmgr,
hwmgr             679 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c 		hwmgr,
hwmgr             687 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c 		struct pp_hwmgr *hwmgr,
hwmgr             710 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr             716 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c static int append_vbios_pptable(struct pp_hwmgr *hwmgr, PPTable_t *ppsmc_pptable)
hwmgr             723 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c 		smc_dpm_table = smu_atom_get_data_table(hwmgr->adev, index, NULL, NULL, NULL),
hwmgr             803 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c static int override_powerplay_table_fantargettemperature(struct pp_hwmgr *hwmgr)
hwmgr             806 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c 		(struct phm_ppt_v3_information *)hwmgr->pptable;
hwmgr             816 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c 		struct pp_hwmgr *hwmgr,
hwmgr             820 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c 		(struct phm_ppt_v3_information *)hwmgr->pptable;
hwmgr             825 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c 	hwmgr->thermal_controller.ucType = powerplay_table->ucThermalControllerType;
hwmgr             827 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c 	hwmgr->thermal_controller.fanInfo.ulMinRPM = 0;
hwmgr             828 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c 	hwmgr->thermal_controller.fanInfo.ulMaxRPM = powerplay_table->smcPPTable.FanMaximumRpm;
hwmgr             830 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c 	set_hw_cap(hwmgr,
hwmgr             831 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c 		ATOM_VEGA20_PP_THERMALCONTROLLER_NONE != hwmgr->thermal_controller.ucType,
hwmgr             834 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl);
hwmgr             848 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c 		copy_overdrive_feature_capabilities_array(hwmgr,
hwmgr             852 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c 		phm_copy_overdrive_settings_limits_array(hwmgr,
hwmgr             856 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c 		phm_copy_overdrive_settings_limits_array(hwmgr,
hwmgr             870 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c 	hwmgr->platform_descriptor.TDPODLimit = le32_to_cpu(powerplay_table->OverDrive8Table.ODSettingsMax[ATOM_VEGA20_ODSETTING_POWERPERCENTAGE]);
hwmgr             873 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c 	if (!disable_power_control && hwmgr->platform_descriptor.TDPODLimit)
hwmgr             875 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PowerControl);
hwmgr             883 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c 		phm_copy_clock_limits_array(hwmgr,
hwmgr             887 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c 		phm_copy_clock_limits_array(hwmgr,
hwmgr             902 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c 	result = append_vbios_pptable(hwmgr, (pptable_information->smc_pptable));
hwmgr             906 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c 	result = override_powerplay_table_fantargettemperature(hwmgr);
hwmgr             911 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c static int vega20_pp_tables_initialize(struct pp_hwmgr *hwmgr)
hwmgr             916 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c 	hwmgr->pptable = kzalloc(sizeof(struct phm_ppt_v3_information), GFP_KERNEL);
hwmgr             917 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c 	PP_ASSERT_WITH_CODE((hwmgr->pptable != NULL),
hwmgr             920 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c 	powerplay_table = get_powerplay_table(hwmgr);
hwmgr             924 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c 	result = check_powerplay_tables(hwmgr, powerplay_table);
hwmgr             928 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c 	result = set_platform_caps(hwmgr,
hwmgr             933 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c 	result = init_powerplay_table_information(hwmgr, powerplay_table);
hwmgr             940 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c static int vega20_pp_tables_uninitialize(struct pp_hwmgr *hwmgr)
hwmgr             943 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c 			(struct phm_ppt_v3_information *)(hwmgr->pptable);
hwmgr             963 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c 	kfree(hwmgr->pptable);
hwmgr             964 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_processpptables.c 	hwmgr->pptable = NULL;
hwmgr              32 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c static int vega20_disable_fan_control_feature(struct pp_hwmgr *hwmgr)
hwmgr              34 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c 	struct vega20_hwmgr *data = hwmgr->backend;
hwmgr              39 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c 				hwmgr, false,
hwmgr              51 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c int vega20_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr)
hwmgr              53 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c 	struct vega20_hwmgr *data = hwmgr->backend;
hwmgr              56 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c 		return vega20_disable_fan_control_feature(hwmgr);
hwmgr              61 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c static int vega20_enable_fan_control_feature(struct pp_hwmgr *hwmgr)
hwmgr              63 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c 	struct vega20_hwmgr *data = hwmgr->backend;
hwmgr              68 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c 				hwmgr, true,
hwmgr              80 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c int vega20_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
hwmgr              82 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c 	struct vega20_hwmgr *data = hwmgr->backend;
hwmgr              85 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c 		return vega20_enable_fan_control_feature(hwmgr);
hwmgr              90 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c static int vega20_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
hwmgr              92 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             104 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c static int vega20_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm)
hwmgr             108 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c 	PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr,
hwmgr             112 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c 	*current_rpm = smum_get_argument(hwmgr);
hwmgr             117 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c int vega20_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr,
hwmgr             120 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c 	struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
hwmgr             125 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c 	ret = vega20_get_current_rpm(hwmgr, &current_rpm);
hwmgr             136 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c int vega20_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
hwmgr             139 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             148 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c 		vega20_fan_ctrl_stop_smc_fan_control(hwmgr);
hwmgr             164 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c 	return vega20_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
hwmgr             167 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c int vega20_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr,
hwmgr             179 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c int vega20_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed)
hwmgr             183 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c 	return vega20_get_current_rpm(hwmgr, speed);
hwmgr             186 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c int vega20_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed)
hwmgr             188 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             196 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c 		result = vega20_fan_ctrl_stop_smc_fan_control(hwmgr);
hwmgr             201 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c 	crystal_clock_freq = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
hwmgr             208 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c 	return vega20_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC_RPM);
hwmgr             216 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c int vega20_thermal_get_temperature(struct pp_hwmgr *hwmgr)
hwmgr             218 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             240 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c static int vega20_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
hwmgr             243 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             276 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c static int vega20_thermal_enable_alert(struct pp_hwmgr *hwmgr)
hwmgr             278 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             294 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c int vega20_thermal_disable_alert(struct pp_hwmgr *hwmgr)
hwmgr             296 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             308 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c int vega20_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr)
hwmgr             310 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c 	int result = vega20_thermal_disable_alert(hwmgr);
hwmgr             324 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c static int vega20_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
hwmgr             327 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c 	struct vega20_hwmgr *data = (struct vega20_hwmgr *)(hwmgr->backend);
hwmgr             330 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c 	ret = smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             337 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c int vega20_start_thermal_controller(struct pp_hwmgr *hwmgr,
hwmgr             345 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c 	ret = vega20_thermal_set_temperature_range(hwmgr, range);
hwmgr             349 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c 	ret = vega20_thermal_enable_alert(hwmgr);
hwmgr             353 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.c 	ret = vega20_thermal_setup_fan_table(hwmgr);
hwmgr              52 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.h extern int vega20_thermal_get_temperature(struct pp_hwmgr *hwmgr);
hwmgr              53 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.h extern int vega20_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr,
hwmgr              55 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.h extern int vega20_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr,
hwmgr              57 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.h extern int vega20_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr,
hwmgr              59 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.h extern int vega20_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr,
hwmgr              61 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.h extern int vega20_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr,
hwmgr              63 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.h extern int vega20_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr);
hwmgr              64 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.h extern int vega20_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr);
hwmgr              65 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.h extern int vega20_thermal_disable_alert(struct pp_hwmgr *hwmgr);
hwmgr              66 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.h extern int vega20_start_thermal_controller(struct pp_hwmgr *hwmgr,
hwmgr              68 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_thermal.h extern int vega20_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr);
hwmgr             302 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h #define PP_CAP(c) phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, (c))
hwmgr             399 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h extern int phm_disable_clock_power_gatings(struct pp_hwmgr *hwmgr);
hwmgr             400 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h extern int phm_powerdown_uvd(struct pp_hwmgr *hwmgr);
hwmgr             401 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h extern int phm_setup_asic(struct pp_hwmgr *hwmgr);
hwmgr             402 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h extern int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr);
hwmgr             403 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h extern int phm_disable_dynamic_state_management(struct pp_hwmgr *hwmgr);
hwmgr             404 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h extern bool phm_is_hw_access_blocked(struct pp_hwmgr *hwmgr);
hwmgr             405 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h extern int phm_block_hw_access(struct pp_hwmgr *hwmgr, bool block);
hwmgr             406 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h extern int phm_set_power_state(struct pp_hwmgr *hwmgr,
hwmgr             410 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h extern int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
hwmgr             414 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h extern int phm_apply_clock_adjust_rules(struct pp_hwmgr *hwmgr);
hwmgr             416 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h extern int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level);
hwmgr             417 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h extern int phm_pre_display_configuration_changed(struct pp_hwmgr *hwmgr);
hwmgr             418 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h extern int phm_display_configuration_changed(struct pp_hwmgr *hwmgr);
hwmgr             419 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h extern int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr);
hwmgr             420 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h extern int phm_register_irq_handlers(struct pp_hwmgr *hwmgr);
hwmgr             421 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h extern int phm_start_thermal_controller(struct pp_hwmgr *hwmgr);
hwmgr             422 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h extern int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr);
hwmgr             423 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h extern bool phm_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr);
hwmgr             425 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h extern int phm_check_states_equal(struct pp_hwmgr *hwmgr,
hwmgr             430 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h extern int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
hwmgr             433 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h extern int phm_get_dal_power_level(struct pp_hwmgr *hwmgr,
hwmgr             436 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h extern int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr);
hwmgr             438 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h extern int phm_power_down_asic(struct pp_hwmgr *hwmgr);
hwmgr             440 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h extern int phm_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
hwmgr             444 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h extern int phm_get_clock_info(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
hwmgr             448 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h extern int phm_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, struct pp_clock_info *clock_info);
hwmgr             450 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h extern int phm_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks);
hwmgr             452 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h extern int phm_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
hwmgr             455 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h extern int phm_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
hwmgr             458 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h extern int phm_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
hwmgr             460 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h extern int phm_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
hwmgr             463 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h extern int phm_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);
hwmgr             464 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h extern int phm_disable_smc_firmware_ctf(struct pp_hwmgr *hwmgr);
hwmgr             466 drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h extern int phm_set_active_display_count(struct pp_hwmgr *hwmgr, uint32_t count);
hwmgr             202 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*smu_init)(struct pp_hwmgr  *hwmgr);
hwmgr             203 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*smu_fini)(struct pp_hwmgr  *hwmgr);
hwmgr             204 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*start_smu)(struct pp_hwmgr  *hwmgr);
hwmgr             205 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*check_fw_load_finish)(struct pp_hwmgr  *hwmgr,
hwmgr             207 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*request_smu_load_fw)(struct pp_hwmgr  *hwmgr);
hwmgr             208 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*request_smu_load_specific_fw)(struct pp_hwmgr  *hwmgr,
hwmgr             210 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	uint32_t (*get_argument)(struct pp_hwmgr  *hwmgr);
hwmgr             211 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*send_msg_to_smc)(struct pp_hwmgr  *hwmgr, uint16_t msg);
hwmgr             212 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*send_msg_to_smc_with_parameter)(struct pp_hwmgr  *hwmgr,
hwmgr             214 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*download_pptable_settings)(struct pp_hwmgr  *hwmgr,
hwmgr             216 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*upload_pptable_settings)(struct pp_hwmgr  *hwmgr);
hwmgr             217 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*update_smc_table)(struct pp_hwmgr *hwmgr, uint32_t type);
hwmgr             218 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*process_firmware_header)(struct pp_hwmgr *hwmgr);
hwmgr             219 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*update_sclk_threshold)(struct pp_hwmgr *hwmgr);
hwmgr             220 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*thermal_setup_fan_table)(struct pp_hwmgr *hwmgr);
hwmgr             221 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*thermal_avfs_enable)(struct pp_hwmgr *hwmgr);
hwmgr             222 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*init_smc_table)(struct pp_hwmgr *hwmgr);
hwmgr             223 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*populate_all_graphic_levels)(struct pp_hwmgr *hwmgr);
hwmgr             224 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*populate_all_memory_levels)(struct pp_hwmgr *hwmgr);
hwmgr             225 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*initialize_mc_reg_table)(struct pp_hwmgr *hwmgr);
hwmgr             228 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	bool (*is_dpm_running)(struct pp_hwmgr *hwmgr);
hwmgr             229 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	bool (*is_hw_avfs_present)(struct pp_hwmgr  *hwmgr);
hwmgr             230 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*update_dpm_settings)(struct pp_hwmgr *hwmgr, void *profile_setting);
hwmgr             231 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*smc_table_manager)(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw); /*rw: true for read, false for write */
hwmgr             240 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*apply_state_adjust_rules)(struct pp_hwmgr *hwmgr,
hwmgr             244 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*apply_clocks_adjust_rules)(struct pp_hwmgr *hwmgr);
hwmgr             254 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*patch_boot_state)(struct pp_hwmgr *hwmgr,
hwmgr             257 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*get_pp_table_entry)(struct pp_hwmgr *hwmgr,
hwmgr             259 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*get_num_of_pp_table_entries)(struct pp_hwmgr *hwmgr);
hwmgr             260 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*powerdown_uvd)(struct pp_hwmgr *hwmgr);
hwmgr             261 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	void (*powergate_vce)(struct pp_hwmgr *hwmgr, bool bgate);
hwmgr             262 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	void (*powergate_uvd)(struct pp_hwmgr *hwmgr, bool bgate);
hwmgr             263 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	void (*powergate_acp)(struct pp_hwmgr *hwmgr, bool bgate);
hwmgr             264 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	uint32_t (*get_mclk)(struct pp_hwmgr *hwmgr, bool low);
hwmgr             265 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	uint32_t (*get_sclk)(struct pp_hwmgr *hwmgr, bool low);
hwmgr             266 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*power_state_set)(struct pp_hwmgr *hwmgr,
hwmgr             268 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*notify_smc_display_config_after_ps_adjustment)(struct pp_hwmgr *hwmgr);
hwmgr             269 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*pre_display_config_changed)(struct pp_hwmgr *hwmgr);
hwmgr             270 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*display_config_changed)(struct pp_hwmgr *hwmgr);
hwmgr             271 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*disable_clock_power_gating)(struct pp_hwmgr *hwmgr);
hwmgr             272 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*update_clock_gatings)(struct pp_hwmgr *hwmgr,
hwmgr             274 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*set_max_fan_rpm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
hwmgr             275 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*set_max_fan_pwm_output)(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm);
hwmgr             276 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*stop_thermal_controller)(struct pp_hwmgr *hwmgr);
hwmgr             277 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*get_fan_speed_info)(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info);
hwmgr             278 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	void (*set_fan_control_mode)(struct pp_hwmgr *hwmgr, uint32_t mode);
hwmgr             279 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	uint32_t (*get_fan_control_mode)(struct pp_hwmgr *hwmgr);
hwmgr             280 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*set_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t percent);
hwmgr             281 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*get_fan_speed_percent)(struct pp_hwmgr *hwmgr, uint32_t *speed);
hwmgr             282 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*set_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t percent);
hwmgr             283 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*get_fan_speed_rpm)(struct pp_hwmgr *hwmgr, uint32_t *speed);
hwmgr             284 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*reset_fan_speed_to_default)(struct pp_hwmgr *hwmgr);
hwmgr             285 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*uninitialize_thermal_controller)(struct pp_hwmgr *hwmgr);
hwmgr             286 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*register_irq_handlers)(struct pp_hwmgr *hwmgr);
hwmgr             287 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	bool (*check_smc_update_required_for_display_configuration)(struct pp_hwmgr *hwmgr);
hwmgr             288 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*check_states_equal)(struct pp_hwmgr *hwmgr,
hwmgr             292 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*set_cpu_power_state)(struct pp_hwmgr *hwmgr);
hwmgr             293 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*store_cc6_data)(struct pp_hwmgr *hwmgr, uint32_t separation_time,
hwmgr             296 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*get_dal_power_level)(struct pp_hwmgr *hwmgr,
hwmgr             300 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*get_current_shallow_sleep_clocks)(struct pp_hwmgr *hwmgr,
hwmgr             302 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*get_clock_by_type)(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks);
hwmgr             303 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*get_clock_by_type_with_latency)(struct pp_hwmgr *hwmgr,
hwmgr             306 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*get_clock_by_type_with_voltage)(struct pp_hwmgr *hwmgr,
hwmgr             309 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*set_watermarks_for_clocks_ranges)(struct pp_hwmgr *hwmgr, void *clock_ranges);
hwmgr             310 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*display_clock_voltage_request)(struct pp_hwmgr *hwmgr,
hwmgr             312 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*get_max_high_clocks)(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);
hwmgr             313 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*power_off_asic)(struct pp_hwmgr *hwmgr);
hwmgr             314 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask);
hwmgr             315 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, char *buf);
hwmgr             316 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*powergate_gfx)(struct pp_hwmgr *hwmgr, bool enable);
hwmgr             317 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*get_sclk_od)(struct pp_hwmgr *hwmgr);
hwmgr             318 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*set_sclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
hwmgr             319 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*get_mclk_od)(struct pp_hwmgr *hwmgr);
hwmgr             320 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*set_mclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);
hwmgr             321 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*read_sensor)(struct pp_hwmgr *hwmgr, int idx, void *value, int *size);
hwmgr             322 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*avfs_control)(struct pp_hwmgr *hwmgr, bool enable);
hwmgr             323 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*disable_smc_firmware_ctf)(struct pp_hwmgr *hwmgr);
hwmgr             324 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*set_active_display_count)(struct pp_hwmgr *hwmgr, uint32_t count);
hwmgr             325 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*set_min_deep_sleep_dcefclk)(struct pp_hwmgr *hwmgr, uint32_t clock);
hwmgr             326 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*start_thermal_controller)(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *range);
hwmgr             327 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*notify_cac_buffer_info)(struct pp_hwmgr *hwmgr,
hwmgr             333 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*update_nbdpm_pstate)(struct pp_hwmgr *hwmgr,
hwmgr             336 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*get_thermal_temperature_range)(struct pp_hwmgr *hwmgr,
hwmgr             338 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*get_power_profile_mode)(struct pp_hwmgr *hwmgr, char *buf);
hwmgr             339 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*set_power_profile_mode)(struct pp_hwmgr *hwmgr, long *input, uint32_t size);
hwmgr             340 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*odn_edit_dpm_table)(struct pp_hwmgr *hwmgr,
hwmgr             343 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*set_power_limit)(struct pp_hwmgr *hwmgr, uint32_t n);
hwmgr             344 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*powergate_mmhub)(struct pp_hwmgr *hwmgr);
hwmgr             345 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*smus_notify_pwe)(struct pp_hwmgr *hwmgr);
hwmgr             346 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*powergate_sdma)(struct pp_hwmgr *hwmgr, bool bgate);
hwmgr             347 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*enable_mgpu_fan_boost)(struct pp_hwmgr *hwmgr);
hwmgr             348 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*set_hard_min_dcefclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);
hwmgr             349 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*set_hard_min_fclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);
hwmgr             350 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*get_asic_baco_capability)(struct pp_hwmgr *hwmgr, bool *cap);
hwmgr             351 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*get_asic_baco_state)(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);
hwmgr             352 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*set_asic_baco_state)(struct pp_hwmgr *hwmgr, enum BACO_STATE state);
hwmgr             353 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*get_ppfeature_status)(struct pp_hwmgr *hwmgr, char *buf);
hwmgr             354 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*set_ppfeature_status)(struct pp_hwmgr *hwmgr, uint64_t ppfeature_masks);
hwmgr             355 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*set_mp1_state)(struct pp_hwmgr *hwmgr, enum pp_mp1_state mp1_state);
hwmgr             356 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*asic_reset)(struct pp_hwmgr *hwmgr, enum SMU_ASIC_RESET_MODE mode);
hwmgr             357 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 	int (*smu_i2c_bus_access)(struct pp_hwmgr *hwmgr, bool aquire);
hwmgr             365 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h 						struct pp_hwmgr *hwmgr,
hwmgr             801 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h int hwmgr_early_init(struct pp_hwmgr *hwmgr);
hwmgr             802 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h int hwmgr_sw_init(struct pp_hwmgr *hwmgr);
hwmgr             803 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h int hwmgr_sw_fini(struct pp_hwmgr *hwmgr);
hwmgr             804 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h int hwmgr_hw_init(struct pp_hwmgr *hwmgr);
hwmgr             805 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h int hwmgr_hw_fini(struct pp_hwmgr *hwmgr);
hwmgr             806 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h int hwmgr_suspend(struct pp_hwmgr *hwmgr);
hwmgr             807 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h int hwmgr_resume(struct pp_hwmgr *hwmgr);
hwmgr             809 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h int hwmgr_handle_task(struct pp_hwmgr *hwmgr,
hwmgr              84 drivers/gpu/drm/amd/powerplay/inc/smumgr.h extern uint32_t smum_get_argument(struct pp_hwmgr *hwmgr);
hwmgr              86 drivers/gpu/drm/amd/powerplay/inc/smumgr.h extern int smum_download_powerplay_table(struct pp_hwmgr *hwmgr, void **table);
hwmgr              88 drivers/gpu/drm/amd/powerplay/inc/smumgr.h extern int smum_upload_powerplay_table(struct pp_hwmgr *hwmgr);
hwmgr              90 drivers/gpu/drm/amd/powerplay/inc/smumgr.h extern int smum_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg);
hwmgr              92 drivers/gpu/drm/amd/powerplay/inc/smumgr.h extern int smum_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
hwmgr              95 drivers/gpu/drm/amd/powerplay/inc/smumgr.h extern int smum_update_sclk_threshold(struct pp_hwmgr *hwmgr);
hwmgr              97 drivers/gpu/drm/amd/powerplay/inc/smumgr.h extern int smum_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type);
hwmgr              98 drivers/gpu/drm/amd/powerplay/inc/smumgr.h extern int smum_process_firmware_header(struct pp_hwmgr *hwmgr);
hwmgr              99 drivers/gpu/drm/amd/powerplay/inc/smumgr.h extern int smum_thermal_avfs_enable(struct pp_hwmgr *hwmgr);
hwmgr             100 drivers/gpu/drm/amd/powerplay/inc/smumgr.h extern int smum_thermal_setup_fan_table(struct pp_hwmgr *hwmgr);
hwmgr             101 drivers/gpu/drm/amd/powerplay/inc/smumgr.h extern int smum_init_smc_table(struct pp_hwmgr *hwmgr);
hwmgr             102 drivers/gpu/drm/amd/powerplay/inc/smumgr.h extern int smum_populate_all_graphic_levels(struct pp_hwmgr *hwmgr);
hwmgr             103 drivers/gpu/drm/amd/powerplay/inc/smumgr.h extern int smum_populate_all_memory_levels(struct pp_hwmgr *hwmgr);
hwmgr             104 drivers/gpu/drm/amd/powerplay/inc/smumgr.h extern int smum_initialize_mc_reg_table(struct pp_hwmgr *hwmgr);
hwmgr             105 drivers/gpu/drm/amd/powerplay/inc/smumgr.h extern uint32_t smum_get_offsetof(struct pp_hwmgr *hwmgr,
hwmgr             107 drivers/gpu/drm/amd/powerplay/inc/smumgr.h extern uint32_t smum_get_mac_definition(struct pp_hwmgr *hwmgr, uint32_t value);
hwmgr             109 drivers/gpu/drm/amd/powerplay/inc/smumgr.h extern bool smum_is_dpm_running(struct pp_hwmgr *hwmgr);
hwmgr             111 drivers/gpu/drm/amd/powerplay/inc/smumgr.h extern bool smum_is_hw_avfs_present(struct pp_hwmgr *hwmgr);
hwmgr             113 drivers/gpu/drm/amd/powerplay/inc/smumgr.h extern int smum_update_dpm_settings(struct pp_hwmgr *hwmgr, void *profile_setting);
hwmgr             115 drivers/gpu/drm/amd/powerplay/inc/smumgr.h extern int smum_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw);
hwmgr              94 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_set_smc_sram_address(struct pp_hwmgr *hwmgr,
hwmgr             103 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_0, smc_addr);
hwmgr             104 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);
hwmgr             108 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_copy_bytes_to_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address,
hwmgr             129 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		result = ci_set_smc_sram_address(hwmgr, addr, limit);
hwmgr             134 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data);
hwmgr             145 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		result = ci_set_smc_sram_address(hwmgr, addr, limit);
hwmgr             151 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		original_data = cgs_read_register(hwmgr->device, mmSMC_IND_DATA_0);
hwmgr             165 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		result = ci_set_smc_sram_address(hwmgr, addr, limit);
hwmgr             170 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data);
hwmgr             177 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_program_jump_on_start(struct pp_hwmgr *hwmgr)
hwmgr             181 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	ci_copy_bytes_to_smc(hwmgr, 0x0, data, 4, sizeof(data)+1);
hwmgr             186 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c bool ci_is_smc_ram_running(struct pp_hwmgr *hwmgr)
hwmgr             188 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	return ((0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
hwmgr             190 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	&& (0x20100 <= cgs_read_ind_register(hwmgr->device,
hwmgr             194 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_read_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr,
hwmgr             199 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	result = ci_set_smc_sram_address(hwmgr, smc_addr, limit);
hwmgr             204 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	*value = cgs_read_register(hwmgr->device, mmSMC_IND_DATA_0);
hwmgr             208 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
hwmgr             212 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	cgs_write_register(hwmgr->device, mmSMC_RESP_0, 0);
hwmgr             213 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, msg);
hwmgr             215 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);
hwmgr             217 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	ret = PHM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP);
hwmgr             225 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
hwmgr             228 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, parameter);
hwmgr             229 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	return ci_send_msg_to_smc(hwmgr, msg);
hwmgr             232 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static void ci_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
hwmgr             234 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
hwmgr             235 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             275 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
hwmgr             295 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_calculate_sclk_params(struct pp_hwmgr *hwmgr,
hwmgr             298 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             311 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock,  &dividers);
hwmgr             318 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	ref_clock = atomctrl_get_reference_clock(hwmgr);
hwmgr             338 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr             343 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		if (!atomctrl_get_engine_clock_spread_spectrum(hwmgr,
hwmgr             369 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static void ci_populate_phase_value_based_on_sclk(struct pp_hwmgr *hwmgr,
hwmgr             406 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
hwmgr             410 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             413 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	result = ci_calculate_sclk_params(hwmgr, clock, level);
hwmgr             416 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	result = ci_get_dependency_volt_by_clk(hwmgr,
hwmgr             417 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			hwmgr->dyn_state.vddc_dependency_on_sclk, clock,
hwmgr             428 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		ci_populate_phase_value_based_on_sclk(hwmgr,
hwmgr             429 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				hwmgr->dyn_state.vddc_phase_shed_limits_table,
hwmgr             445 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr             470 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
hwmgr             472 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             473 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
hwmgr             485 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		result = ci_populate_single_graphic_level(hwmgr,
hwmgr             503 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	result = ci_copy_bytes_to_smc(hwmgr, array,
hwmgr             511 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_populate_svi_load_line(struct pp_hwmgr *hwmgr)
hwmgr             513 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
hwmgr             524 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_populate_tdc_limit(struct pp_hwmgr *hwmgr)
hwmgr             527 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
hwmgr             530 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	tdc_limit = (uint16_t)(hwmgr->dyn_state.cac_dtp_table->usTDC * 256);
hwmgr             540 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
hwmgr             542 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
hwmgr             546 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	if (ci_read_smc_sram_dword(hwmgr,
hwmgr             559 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_populate_fuzzy_fan(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
hwmgr             562 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
hwmgr             564 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	if ((hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity & (1 << 15))
hwmgr             565 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		|| 0 == hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity)
hwmgr             566 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		tmp = hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity;
hwmgr             568 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		tmp = hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity;
hwmgr             575 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_populate_bapm_vddc_vid_sidd(struct pp_hwmgr *hwmgr)
hwmgr             578 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
hwmgr             583 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.cac_leakage_table,
hwmgr             585 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count <= 8,
hwmgr             587 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count == hwmgr->dyn_state.vddc_dependency_on_sclk->count,
hwmgr             590 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	for (i = 0; (uint32_t) i < hwmgr->dyn_state.cac_leakage_table->count; i++) {
hwmgr             591 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_EVV)) {
hwmgr             592 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			lo_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc1);
hwmgr             593 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			hi_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc2);
hwmgr             594 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			hi2_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc3);
hwmgr             596 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			lo_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc);
hwmgr             597 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			hi_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Leakage);
hwmgr             604 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_populate_vddc_vid(struct pp_hwmgr *hwmgr)
hwmgr             607 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
hwmgr             609 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             621 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct pp_hwmgr *hwmgr)
hwmgr             623 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
hwmgr             653 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
hwmgr             655 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
hwmgr             658 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct phm_cac_tdp_table *cac_table = hwmgr->dyn_state.cac_dtp_table;
hwmgr             671 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_populate_pm_fuses(struct pp_hwmgr *hwmgr)
hwmgr             673 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
hwmgr             677 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr             679 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		if (ci_read_smc_sram_dword(hwmgr,
hwmgr             688 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		ret = ci_populate_bapm_vddc_vid_sidd(hwmgr);
hwmgr             690 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		ret |= ci_populate_vddc_vid(hwmgr);
hwmgr             692 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		ret |= ci_populate_svi_load_line(hwmgr);
hwmgr             694 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		ret |= ci_populate_tdc_limit(hwmgr);
hwmgr             696 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		ret |= ci_populate_dw8(hwmgr, pm_fuse_table_offset);
hwmgr             698 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		ret |= ci_populate_fuzzy_fan(hwmgr, pm_fuse_table_offset);
hwmgr             700 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		ret |= ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(hwmgr);
hwmgr             702 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		ret |= ci_populate_bapm_vddc_base_leakage_sidd(hwmgr);
hwmgr             706 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		ret = ci_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
hwmgr             713 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
hwmgr             715 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
hwmgr             716 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             719 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct phm_cac_tdp_table *cac_dtp_table = hwmgr->dyn_state.cac_dtp_table;
hwmgr             720 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct phm_ppm_table *ppm = hwmgr->dyn_state.ppm_parameter_table;
hwmgr             762 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_get_std_voltage_value_sidd(struct pp_hwmgr *hwmgr,
hwmgr             771 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.vddc_dependency_on_sclk,
hwmgr             775 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	if (NULL == hwmgr->dyn_state.cac_leakage_table) {
hwmgr             780 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) {
hwmgr             781 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		if (tab->value == hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) {
hwmgr             783 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			if ((uint32_t)v_index < hwmgr->dyn_state.cac_leakage_table->count) {
hwmgr             784 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				*lo = hwmgr->dyn_state.cac_leakage_table->entries[v_index].Vddc * VOLTAGE_SCALE;
hwmgr             785 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				*hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[v_index].Leakage * VOLTAGE_SCALE);
hwmgr             788 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				*lo = hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Vddc * VOLTAGE_SCALE;
hwmgr             789 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				*hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Leakage * VOLTAGE_SCALE);
hwmgr             796 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) {
hwmgr             797 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			if (tab->value <= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) {
hwmgr             799 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				if ((uint32_t)v_index < hwmgr->dyn_state.cac_leakage_table->count) {
hwmgr             800 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 					*lo = hwmgr->dyn_state.cac_leakage_table->entries[v_index].Vddc * VOLTAGE_SCALE;
hwmgr             801 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 					*hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[v_index].Leakage) * VOLTAGE_SCALE;
hwmgr             804 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 					*lo = hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Vddc * VOLTAGE_SCALE;
hwmgr             805 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 					*hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Leakage * VOLTAGE_SCALE);
hwmgr             818 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_populate_smc_voltage_table(struct pp_hwmgr *hwmgr,
hwmgr             824 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	result = ci_get_std_voltage_value_sidd(hwmgr, tab,
hwmgr             839 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_populate_smc_vddc_table(struct pp_hwmgr *hwmgr,
hwmgr             844 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             848 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		result = ci_populate_smc_voltage_table(hwmgr,
hwmgr             868 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_populate_smc_vdd_ci_table(struct pp_hwmgr *hwmgr,
hwmgr             871 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             878 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		result = ci_populate_smc_voltage_table(hwmgr,
hwmgr             896 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
hwmgr             899 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             906 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		result = ci_populate_smc_voltage_table(hwmgr,
hwmgr             925 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
hwmgr             930 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	result = ci_populate_smc_vddc_table(hwmgr, table);
hwmgr             934 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	result = ci_populate_smc_vdd_ci_table(hwmgr, table);
hwmgr             938 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	result = ci_populate_smc_mvdd_table(hwmgr, table);
hwmgr             945 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_populate_ulv_level(struct pp_hwmgr *hwmgr,
hwmgr             950 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             955 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	result = pp_tables_get_response_times(hwmgr, &voltage_response_time, &ulv_voltage);
hwmgr             965 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v)
hwmgr             969 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			state->VddcOffset = (uint16_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage);
hwmgr             972 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v)
hwmgr             976 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 					(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage)
hwmgr             989 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_populate_ulv_state(struct pp_hwmgr *hwmgr,
hwmgr             992 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	return ci_populate_ulv_level(hwmgr, ulv_level);
hwmgr             995 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU7_Discrete_DpmTable *table)
hwmgr             997 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             999 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
hwmgr            1022 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		struct pp_hwmgr *hwmgr,
hwmgr            1029 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1043 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	result = atomctrl_get_memory_pll_dividers_si(hwmgr,
hwmgr            1067 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            1072 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		uint32_t reference_clock = atomctrl_get_mpll_reference_clock(hwmgr);
hwmgr            1084 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		if (0 == atomctrl_get_memory_clock_spread_spectrum(hwmgr, freq_nom, &ss_info)) {
hwmgr            1155 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_populate_phase_value_based_on_mclk(struct pp_hwmgr *hwmgr, const struct phm_phase_shedding_limits_table *pl,
hwmgr            1173 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		struct pp_hwmgr *hwmgr,
hwmgr            1178 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1185 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	if (hwmgr->dyn_state.vddc_dependency_on_mclk != NULL) {
hwmgr            1186 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		result = ci_get_dependency_volt_by_clk(hwmgr,
hwmgr            1187 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			hwmgr->dyn_state.vddc_dependency_on_mclk, memory_clock, &memory_level->MinVddc);
hwmgr            1192 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	if (NULL != hwmgr->dyn_state.vddci_dependency_on_mclk) {
hwmgr            1193 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		result = ci_get_dependency_volt_by_clk(hwmgr,
hwmgr            1194 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				hwmgr->dyn_state.vddci_dependency_on_mclk,
hwmgr            1201 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	if (NULL != hwmgr->dyn_state.mvdd_dependency_on_mclk) {
hwmgr            1202 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		result = ci_get_dependency_volt_by_clk(hwmgr,
hwmgr            1203 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				hwmgr->dyn_state.mvdd_dependency_on_mclk,
hwmgr            1213 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		ci_populate_phase_value_based_on_mclk(hwmgr, hwmgr->dyn_state.vddc_phase_shed_limits_table,
hwmgr            1234 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
hwmgr            1235 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	data->display_timing.vrefresh = hwmgr->display_config->vrefresh;
hwmgr            1260 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 					((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC7) >> 16) & 0xf))
hwmgr            1261 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
hwmgr            1263 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC6) >> 1) & 0x1) ? 1 : 0;
hwmgr            1269 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
hwmgr            1272 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	result = ci_calculate_mclk_params(hwmgr,
hwmgr            1298 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
hwmgr            1300 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1301 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
hwmgr            1304 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr            1317 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		result = ci_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value,
hwmgr            1341 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	result = ci_copy_bytes_to_smc(hwmgr,
hwmgr            1348 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_populate_mvdd_value(struct pp_hwmgr *hwmgr, uint32_t mclk,
hwmgr            1351 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1357 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		for (i = 0; i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count; i++) {
hwmgr            1358 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			if (mclk <= hwmgr->dyn_state.mvdd_dependency_on_mclk->entries[i].clk) {
hwmgr            1365 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		PP_ASSERT_WITH_CODE(i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count,
hwmgr            1375 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
hwmgr            1379 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1399 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr);
hwmgr            1402 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	result = atomctrl_get_engine_pll_dividers_vi(hwmgr,
hwmgr            1456 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	if (0 == ci_populate_mvdd_value(hwmgr, 0, &voltage_level))
hwmgr            1516 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
hwmgr            1523 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
hwmgr            1536 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
hwmgr            1543 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
hwmgr            1557 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
hwmgr            1564 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				hwmgr->dyn_state.vce_clock_voltage_dependency_table;
hwmgr            1575 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
hwmgr            1589 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
hwmgr            1596 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				hwmgr->dyn_state.acp_clock_voltage_dependency_table;
hwmgr            1606 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
hwmgr            1620 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		struct pp_hwmgr *hwmgr,
hwmgr            1631 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
hwmgr            1637 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	dramTiming  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
hwmgr            1638 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	dramTiming2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
hwmgr            1639 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	burstTime = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
hwmgr            1648 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
hwmgr            1650 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1651 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
hwmgr            1661 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				(hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value,
hwmgr            1672 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				hwmgr,
hwmgr            1683 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
hwmgr            1687 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1688 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
hwmgr            1721 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_populate_mc_reg_address(struct pp_hwmgr *hwmgr,
hwmgr            1724 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	const struct ci_smumgr *smu_data = (struct ci_smumgr *)hwmgr->smu_backend;
hwmgr            1761 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		struct pp_hwmgr *hwmgr,
hwmgr            1766 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
hwmgr            1786 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
hwmgr            1790 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1796 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				hwmgr,
hwmgr            1808 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
hwmgr            1810 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
hwmgr            1811 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1821 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	result = ci_convert_mc_reg_table_to_smc(hwmgr, &(smu_data->mc_regs));
hwmgr            1828 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	return  ci_copy_bytes_to_smc(hwmgr, address,
hwmgr            1834 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
hwmgr            1837 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
hwmgr            1840 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	result = ci_populate_mc_reg_address(hwmgr, &(smu_data->mc_regs));
hwmgr            1844 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	result = ci_convert_mc_reg_table_to_smc(hwmgr, &smu_data->mc_regs);
hwmgr            1848 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	return ci_copy_bytes_to_smc(hwmgr, smu_data->mc_reg_table_start,
hwmgr            1852 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_populate_smc_initial_state(struct pp_hwmgr *hwmgr)
hwmgr            1854 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1855 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
hwmgr            1858 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->count);
hwmgr            1861 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		if (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[level].clk
hwmgr            1868 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_mclk->count);
hwmgr            1871 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		if (hwmgr->dyn_state.vddc_dependency_on_mclk->entries[level].clk
hwmgr            1881 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_populate_smc_svi2_config(struct pp_hwmgr *hwmgr,
hwmgr            1884 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1893 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_start_smc(struct pp_hwmgr *hwmgr)
hwmgr            1896 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	ci_program_jump_on_start(hwmgr);
hwmgr            1899 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
hwmgr            1901 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 0);
hwmgr            1903 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	PHM_WAIT_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS,
hwmgr            1909 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_populate_vr_config(struct pp_hwmgr *hwmgr, SMU7_Discrete_DpmTable *table)
hwmgr            1911 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1940 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_init_smc_table(struct pp_hwmgr *hwmgr)
hwmgr            1943 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1944 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
hwmgr            1949 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	ci_initialize_power_tune_defaults(hwmgr);
hwmgr            1953 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		ci_populate_smc_voltage_tables(hwmgr, table);
hwmgr            1955 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            1960 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            1968 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		result = ci_populate_ulv_state(hwmgr, &(table->Ulv));
hwmgr            1972 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
hwmgr            1976 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	result = ci_populate_all_graphic_levels(hwmgr);
hwmgr            1980 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	result = ci_populate_all_memory_levels(hwmgr);
hwmgr            1984 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	result = ci_populate_smc_link_level(hwmgr, table);
hwmgr            1988 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	result = ci_populate_smc_acpi_level(hwmgr, table);
hwmgr            1992 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	result = ci_populate_smc_vce_level(hwmgr, table);
hwmgr            1996 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	result = ci_populate_smc_acp_level(hwmgr, table);
hwmgr            2002 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	result = ci_program_memory_timing_parameters(hwmgr);
hwmgr            2006 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	result = ci_populate_smc_uvd_level(hwmgr, table);
hwmgr            2018 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	result = ci_populate_smc_boot_level(hwmgr, table);
hwmgr            2022 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	result = ci_populate_smc_initial_state(hwmgr);
hwmgr            2025 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	result = ci_populate_bapm_parameters_in_dpm_table(hwmgr);
hwmgr            2059 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	result = ci_populate_vr_config(hwmgr, table);
hwmgr            2064 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	ci_populate_smc_svi2_config(hwmgr, table);
hwmgr            2071 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
hwmgr            2073 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr            2077 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr            2101 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	result = ci_copy_bytes_to_smc(hwmgr, smu_data->dpm_table_start +
hwmgr            2110 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	result = ci_populate_initial_mc_reg_table(hwmgr);
hwmgr            2114 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	result = ci_populate_pm_fuses(hwmgr);
hwmgr            2118 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	ci_start_smc(hwmgr);
hwmgr            2123 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
hwmgr            2125 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *ci_data = (struct ci_smumgr *)(hwmgr->smu_backend);
hwmgr            2134 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl))
hwmgr            2137 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	if (hwmgr->thermal_controller.fanInfo.bNoFan) {
hwmgr            2138 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr            2144 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl);
hwmgr            2148 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_FDO_CTRL1, FMAX_DUTY100);
hwmgr            2151 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl);
hwmgr            2155 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin * duty100;
hwmgr            2159 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed - hwmgr->thermal_controller.advanceFanControlParameters.usTMin;
hwmgr            2160 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh - hwmgr->thermal_controller.advanceFanControlParameters.usTMed;
hwmgr            2162 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed - hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin;
hwmgr            2163 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh - hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed;
hwmgr            2168 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	fan_table.TempMin = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMin) / 100);
hwmgr            2169 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	fan_table.TempMed = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMed) / 100);
hwmgr            2170 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	fan_table.TempMax = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMax) / 100);
hwmgr            2177 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	fan_table.HystDown = cpu_to_be16(hwmgr->thermal_controller.advanceFanControlParameters.ucTHyst);
hwmgr            2185 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	reference_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
hwmgr            2187 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	fan_table.RefreshPeriod = cpu_to_be32((hwmgr->thermal_controller.advanceFanControlParameters.ulCycleDelay * reference_clock) / 1600);
hwmgr            2191 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_MULT_THERMAL_CTRL, TEMP_SEL);
hwmgr            2193 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	res = ci_copy_bytes_to_smc(hwmgr, ci_data->fan_table_start, (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), SMC_RAM_END);
hwmgr            2198 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
hwmgr            2200 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            2204 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		return ci_program_memory_timing_parameters(hwmgr);
hwmgr            2209 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_update_sclk_threshold(struct pp_hwmgr *hwmgr)
hwmgr            2211 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            2212 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
hwmgr            2217 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            2226 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				hwmgr,
hwmgr            2235 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	result = ci_update_and_upload_mc_reg_table(hwmgr);
hwmgr            2239 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	result = ci_program_mem_timing_parameters(hwmgr);
hwmgr            2310 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_load_smc_ucode(struct pp_hwmgr *hwmgr)
hwmgr            2318 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	cgs_get_firmware_info(hwmgr->device, CGS_UCODE_ID_SMU, &info);
hwmgr            2320 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	hwmgr->is_kicker = info.is_kicker;
hwmgr            2321 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	hwmgr->smu_version = info.version;
hwmgr            2331 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_0, start_addr);
hwmgr            2332 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1);
hwmgr            2336 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data);
hwmgr            2339 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);
hwmgr            2349 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_upload_firmware(struct pp_hwmgr *hwmgr)
hwmgr            2351 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	if (ci_is_smc_ram_running(hwmgr)) {
hwmgr            2355 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	PHM_WAIT_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS,
hwmgr            2357 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_MISC_CNTL,
hwmgr            2360 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 1);
hwmgr            2361 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 1);
hwmgr            2362 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	return ci_load_smc_ucode(hwmgr);
hwmgr            2365 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_process_firmware_header(struct pp_hwmgr *hwmgr)
hwmgr            2367 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            2368 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *ci_data = (struct ci_smumgr *)(hwmgr->smu_backend);
hwmgr            2374 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	if (ci_upload_firmware(hwmgr))
hwmgr            2377 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	result = ci_read_smc_sram_dword(hwmgr,
hwmgr            2387 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	result = ci_read_smc_sram_dword(hwmgr,
hwmgr            2399 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	result = ci_read_smc_sram_dword(hwmgr,
hwmgr            2407 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	result = ci_read_smc_sram_dword(hwmgr,
hwmgr            2417 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	result = ci_read_smc_sram_dword(hwmgr,
hwmgr            2427 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	result = ci_read_smc_sram_dword(hwmgr,
hwmgr            2433 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		hwmgr->microcode_version_info.SMC = tmp;
hwmgr            2440 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static uint8_t ci_get_memory_modile_index(struct pp_hwmgr *hwmgr)
hwmgr            2442 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16));
hwmgr            2580 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_set_mc_special_registers(struct pp_hwmgr *hwmgr,
hwmgr            2585 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            2594 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS);
hwmgr            2606 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS);
hwmgr            2634 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1);
hwmgr            2673 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
hwmgr            2676 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *smu_data = (struct ci_smumgr *)(hwmgr->smu_backend);
hwmgr            2679 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	uint8_t module_index = ci_get_memory_modile_index(hwmgr);
hwmgr            2687 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
hwmgr            2688 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING));
hwmgr            2689 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_DLL_STBY_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_DLL_STBY));
hwmgr            2690 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0));
hwmgr            2691 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1));
hwmgr            2692 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL));
hwmgr            2693 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD));
hwmgr            2694 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL));
hwmgr            2695 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING));
hwmgr            2696 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2));
hwmgr            2697 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_EMRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS));
hwmgr            2698 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS));
hwmgr            2699 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS1_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1));
hwmgr            2700 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0));
hwmgr            2701 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1));
hwmgr            2702 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0));
hwmgr            2703 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1));
hwmgr            2704 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING));
hwmgr            2705 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS2_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS2));
hwmgr            2706 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2));
hwmgr            2708 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table);
hwmgr            2715 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		result = ci_set_mc_special_registers(hwmgr, ni_table);
hwmgr            2726 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static bool ci_is_dpm_running(struct pp_hwmgr *hwmgr)
hwmgr            2728 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	return ci_is_smc_ram_running(hwmgr);
hwmgr            2731 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_smu_init(struct pp_hwmgr *hwmgr)
hwmgr            2740 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	hwmgr->smu_backend = ci_priv;
hwmgr            2745 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_smu_fini(struct pp_hwmgr *hwmgr)
hwmgr            2747 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	kfree(hwmgr->smu_backend);
hwmgr            2748 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	hwmgr->smu_backend = NULL;
hwmgr            2752 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_start_smu(struct pp_hwmgr *hwmgr)
hwmgr            2757 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_update_dpm_settings(struct pp_hwmgr *hwmgr,
hwmgr            2760 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            2762 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			(hwmgr->smu_backend);
hwmgr            2783 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_FreezeLevel);
hwmgr            2792 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
hwmgr            2794 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
hwmgr            2806 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
hwmgr            2809 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
hwmgr            2813 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_UnfreezeLevel);
hwmgr            2818 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_FreezeLevel);
hwmgr            2827 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
hwmgr            2829 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
hwmgr            2841 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
hwmgr            2844 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
hwmgr            2848 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_UnfreezeLevel);
hwmgr            2853 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
hwmgr            2855 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr            2856 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct smu7_hwmgr *data = hwmgr->backend;
hwmgr            2857 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct ci_smumgr *smu_data = hwmgr->smu_backend;
hwmgr            2859 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
hwmgr            2864 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	uint32_t max_vddc = adev->pm.ac_power ? hwmgr->dyn_state.max_clock_voltage_on_ac.vddc :
hwmgr            2865 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 						hwmgr->dyn_state.max_clock_voltage_on_dc.vddc;
hwmgr            2873 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, DPM_TABLE_475,
hwmgr            2881 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		if (hwmgr->dpm_level & profile_mode_mask || !PP_CAP(PHM_PlatformCaps_UVDDPM))
hwmgr            2884 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	ci_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_UVDDPM_SetEnabledMask,
hwmgr            2890 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_update_vce_smc_table(struct pp_hwmgr *hwmgr)
hwmgr            2892 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr            2893 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	struct smu7_hwmgr *data = hwmgr->backend;
hwmgr            2895 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			hwmgr->dyn_state.vce_clock_voltage_dependency_table;
hwmgr            2900 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	uint32_t max_vddc = adev->pm.ac_power ? hwmgr->dyn_state.max_clock_voltage_on_ac.vddc :
hwmgr            2901 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 						hwmgr->dyn_state.max_clock_voltage_on_dc.vddc;
hwmgr            2904 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, DPM_TABLE_475,
hwmgr            2912 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		if (hwmgr->dpm_level & profile_mode_mask || !PP_CAP(PHM_PlatformCaps_VCEDPM))
hwmgr            2915 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	ci_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_VCEDPM_SetEnabledMask,
hwmgr            2921 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c static int ci_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
hwmgr            2925 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		ci_update_uvd_smc_table(hwmgr);
hwmgr            2928 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		ci_update_vce_smc_table(hwmgr);
hwmgr              99 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
hwmgr             107 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             110 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	result = smu7_upload_smu_firmware_image(hwmgr);
hwmgr             115 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             118 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             122 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             130 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             134 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             137 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS,
hwmgr             140 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, 0x20000);
hwmgr             141 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, PPSMC_MSG_Test);
hwmgr             142 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);
hwmgr             145 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
hwmgr             149 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             156 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
hwmgr             162 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr)
hwmgr             167 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
hwmgr             171 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             175 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             178 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	result = smu7_upload_smu_firmware_image(hwmgr);
hwmgr             183 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	smu7_program_jump_on_start(hwmgr);
hwmgr             186 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             190 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             194 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
hwmgr             200 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_start_avfs_btc(struct pp_hwmgr *hwmgr)
hwmgr             203 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
hwmgr             206 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		if (0 != smu7_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             214 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, 0x50000000);
hwmgr             216 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0xffffffff);
hwmgr             218 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0);
hwmgr             223 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_setup_graphics_level_structure(struct pp_hwmgr *hwmgr)
hwmgr             230 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(hwmgr,
hwmgr             245 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, vr_config_addr,
hwmgr             253 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, level_addr,
hwmgr             261 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_avfs_event_mgr(struct pp_hwmgr *hwmgr)
hwmgr             263 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	if (!hwmgr->avfs_supported)
hwmgr             266 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	PP_ASSERT_WITH_CODE(0 == fiji_setup_graphics_level_structure(hwmgr),
hwmgr             270 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	PP_ASSERT_WITH_CODE(0 == smu7_setup_pwr_virus(hwmgr),
hwmgr             274 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	PP_ASSERT_WITH_CODE(0 == fiji_start_avfs_btc(hwmgr),
hwmgr             282 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_start_smu(struct pp_hwmgr *hwmgr)
hwmgr             285 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct fiji_smumgr *priv = (struct fiji_smumgr *)(hwmgr->smu_backend);
hwmgr             288 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	if (!smu7_is_smc_ram_running(hwmgr) && hwmgr->not_vf) {
hwmgr             290 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		if (0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
hwmgr             293 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			result = fiji_start_smu_in_non_protection_mode(hwmgr);
hwmgr             297 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			result = fiji_start_smu_in_protection_mode(hwmgr);
hwmgr             301 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		if (fiji_avfs_event_mgr(hwmgr))
hwmgr             302 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			hwmgr->avfs_supported = false;
hwmgr             308 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	smu7_read_smc_sram_dword(hwmgr,
hwmgr             313 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	result = smu7_request_smu_load_fw(hwmgr);
hwmgr             318 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static bool fiji_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
hwmgr             324 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	if (!hwmgr->not_vf)
hwmgr             327 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	if (!atomctrl_read_efuse(hwmgr, AVFS_EN_LSB, AVFS_EN_MSB,
hwmgr             335 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_smu_init(struct pp_hwmgr *hwmgr)
hwmgr             344 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	hwmgr->smu_backend = fiji_priv;
hwmgr             346 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	if (smu7_init(hwmgr)) {
hwmgr             354 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
hwmgr             360 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             469 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static void fiji_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
hwmgr             471 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
hwmgr             473 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			(struct  phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr             486 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
hwmgr             489 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
hwmgr             495 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr             498 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			&hwmgr->thermal_controller.advanceFanControlParameters;
hwmgr             570 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_populate_svi_load_line(struct pp_hwmgr *hwmgr)
hwmgr             572 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
hwmgr             584 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_populate_tdc_limit(struct pp_hwmgr *hwmgr)
hwmgr             587 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
hwmgr             589 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr             605 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
hwmgr             607 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
hwmgr             611 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	if (smu7_read_smc_sram_dword(hwmgr,
hwmgr             629 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
hwmgr             632 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
hwmgr             641 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
hwmgr             643 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
hwmgr             645 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	if ((hwmgr->thermal_controller.advanceFanControlParameters.
hwmgr             647 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			0 == hwmgr->thermal_controller.advanceFanControlParameters.
hwmgr             649 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		hwmgr->thermal_controller.advanceFanControlParameters.
hwmgr             650 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		usFanOutputSensitivity = hwmgr->thermal_controller.
hwmgr             654 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			PP_HOST_TO_SMC_US(hwmgr->thermal_controller.
hwmgr             659 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
hwmgr             662 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
hwmgr             671 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
hwmgr             673 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
hwmgr             675 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr             691 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_populate_pm_fuses(struct pp_hwmgr *hwmgr)
hwmgr             694 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
hwmgr             696 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr             698 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		if (smu7_read_smc_sram_dword(hwmgr,
hwmgr             707 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		if (fiji_populate_svi_load_line(hwmgr))
hwmgr             712 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		if (fiji_populate_tdc_limit(hwmgr))
hwmgr             716 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		if (fiji_populate_dw8(hwmgr, pm_fuse_table_offset))
hwmgr             723 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		if (0 != fiji_populate_temperature_scaler(hwmgr))
hwmgr             729 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		if (fiji_populate_fuzzy_fan(hwmgr))
hwmgr             735 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		if (fiji_populate_gnb_lpml(hwmgr))
hwmgr             741 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		if (fiji_populate_bapm_vddc_base_leakage_sidd(hwmgr))
hwmgr             746 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
hwmgr             756 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_populate_cac_table(struct pp_hwmgr *hwmgr,
hwmgr             761 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             763 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr             784 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
hwmgr             789 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	result = fiji_populate_cac_table(hwmgr, table);
hwmgr             797 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_populate_ulv_level(struct pp_hwmgr *hwmgr,
hwmgr             803 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr             822 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_populate_ulv_state(struct pp_hwmgr *hwmgr,
hwmgr             825 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	return fiji_populate_ulv_level(hwmgr, &table->Ulv);
hwmgr             828 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_populate_smc_link_level(struct pp_hwmgr *hwmgr,
hwmgr             831 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             833 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
hwmgr             857 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_calculate_sclk_params(struct pp_hwmgr *hwmgr,
hwmgr             860 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             873 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	result = atomctrl_get_engine_pll_dividers_vi(hwmgr, clock,  &dividers);
hwmgr             880 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	ref_clock = atomctrl_get_reference_clock(hwmgr);
hwmgr             900 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr             905 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		if (!atomctrl_get_engine_clock_spread_spectrum(hwmgr,
hwmgr             938 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
hwmgr             944 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             946 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr             949 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	result = fiji_calculate_sclk_params(hwmgr, clock, level);
hwmgr             951 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	if (hwmgr->od_enabled)
hwmgr             957 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	result = fiji_get_dependency_volt_by_clk(hwmgr,
hwmgr             978 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr;
hwmgr             980 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
hwmgr             982 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 								hwmgr->display_config->min_core_set_clock_in_sr);
hwmgr            1003 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
hwmgr            1005 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1006 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
hwmgr            1010 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            1027 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		result = fiji_populate_single_graphic_level(hwmgr,
hwmgr            1090 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
hwmgr            1146 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_calculate_mclk_params(struct pp_hwmgr *hwmgr,
hwmgr            1152 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	result = atomctrl_get_memory_pll_dividers_vi(hwmgr, clock, &mem_param);
hwmgr            1165 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_populate_single_memory_level(struct pp_hwmgr *hwmgr,
hwmgr            1168 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1170 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            1175 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	if (hwmgr->od_enabled)
hwmgr            1181 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		result = fiji_get_dependency_volt_by_clk(hwmgr,
hwmgr            1203 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
hwmgr            1204 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	data->display_timing.vrefresh = hwmgr->display_config->vrefresh;
hwmgr            1209 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		(PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
hwmgr            1213 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	result = fiji_calculate_mclk_params(hwmgr, clock, mem_level);
hwmgr            1223 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
hwmgr            1225 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1226 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
hwmgr            1242 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		result = fiji_populate_single_memory_level(hwmgr,
hwmgr            1269 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
hwmgr            1275 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_populate_mvdd_value(struct pp_hwmgr *hwmgr,
hwmgr            1278 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1280 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            1300 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
hwmgr            1304 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1306 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            1321 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		result = fiji_get_dependency_volt_by_clk(hwmgr,
hwmgr            1337 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	result = atomctrl_get_engine_pll_dividers_vi(hwmgr,
hwmgr            1379 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		result = fiji_get_dependency_volt_by_clk(hwmgr,
hwmgr            1398 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		if (!fiji_populate_mvdd_value(hwmgr,
hwmgr            1422 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
hwmgr            1429 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            1447 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
hwmgr            1461 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
hwmgr            1468 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            1484 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
hwmgr            1497 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
hwmgr            1507 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
hwmgr            1512 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
hwmgr            1513 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
hwmgr            1514 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	burstTime = cgs_read_register(hwmgr->device, mmMC_ARB_BURST_TIME);
hwmgr            1529 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
hwmgr            1531 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1532 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
hwmgr            1539 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			result = fiji_populate_memory_timing_parameters(hwmgr,
hwmgr            1550 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				hwmgr,
hwmgr            1558 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
hwmgr            1565 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            1583 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
hwmgr            1590 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
hwmgr            1605 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
hwmgr            1609 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1637 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
hwmgr            1639 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1640 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
hwmgr            1642 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            1666 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
hwmgr            1671 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
hwmgr            1675 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            1684 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
hwmgr            1686 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	efuse2 = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
hwmgr            1721 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
hwmgr            1723 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
hwmgr            1725 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
hwmgr            1727 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
hwmgr            1736 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr            1743 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
hwmgr            1775 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
hwmgr            1816 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
hwmgr            1818 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
hwmgr            1823 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_populate_vr_config(struct pp_hwmgr *hwmgr,
hwmgr            1826 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1867 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_init_arb_table_index(struct pp_hwmgr *hwmgr)
hwmgr            1869 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
hwmgr            1881 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	result = smu7_read_smc_sram_dword(hwmgr,
hwmgr            1890 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	return smu7_write_smc_sram_dword(hwmgr,
hwmgr            1894 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_setup_dpm_led_config(struct pp_hwmgr *hwmgr)
hwmgr            1900 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	result = atomctrl_get_voltage_table_v3(hwmgr,
hwmgr            1917 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            1923 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_init_smc_table(struct pp_hwmgr *hwmgr)
hwmgr            1926 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1927 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
hwmgr            1929 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            1934 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	fiji_initialize_power_tune_defaults(hwmgr);
hwmgr            1937 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		fiji_populate_smc_voltage_tables(hwmgr, table);
hwmgr            1941 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            1945 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            1953 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		result = fiji_populate_ulv_state(hwmgr, table);
hwmgr            1956 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
hwmgr            1960 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	result = fiji_populate_smc_link_level(hwmgr, table);
hwmgr            1964 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	result = fiji_populate_all_graphic_levels(hwmgr);
hwmgr            1968 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	result = fiji_populate_all_memory_levels(hwmgr);
hwmgr            1972 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	result = fiji_populate_smc_acpi_level(hwmgr, table);
hwmgr            1976 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	result = fiji_populate_smc_vce_level(hwmgr, table);
hwmgr            1980 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	result = fiji_populate_smc_acp_level(hwmgr, table);
hwmgr            1988 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	result = fiji_program_memory_timing_parameters(hwmgr);
hwmgr            1992 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	result = fiji_populate_smc_uvd_level(hwmgr, table);
hwmgr            1996 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	result = fiji_populate_smc_boot_level(hwmgr, table);
hwmgr            2000 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	result = fiji_populate_smc_initailial_state(hwmgr);
hwmgr            2004 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	result = fiji_populate_bapm_parameters_in_dpm_table(hwmgr);
hwmgr            2008 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            2010 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		result = fiji_populate_clock_stretcher_data_table(hwmgr);
hwmgr            2036 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	result = fiji_populate_vr_config(hwmgr, table);
hwmgr            2043 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
hwmgr            2045 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr            2049 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr            2053 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
hwmgr            2056 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr            2060 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr            2065 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
hwmgr            2067 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr            2077 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) &
hwmgr            2082 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            2084 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            2088 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr            2109 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	result = smu7_copy_bytes_to_smc(hwmgr,
hwmgr            2118 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	result = fiji_init_arb_table_index(hwmgr);
hwmgr            2122 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	result = fiji_populate_pm_fuses(hwmgr);
hwmgr            2126 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	result = fiji_setup_dpm_led_config(hwmgr);
hwmgr            2133 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
hwmgr            2135 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
hwmgr            2145 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	if (hwmgr->thermal_controller.fanInfo.bNoFan) {
hwmgr            2146 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr            2152 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr            2157 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr            2161 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr            2166 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.
hwmgr            2171 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed -
hwmgr            2172 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			hwmgr->thermal_controller.advanceFanControlParameters.usTMin;
hwmgr            2173 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh -
hwmgr            2174 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			hwmgr->thermal_controller.advanceFanControlParameters.usTMed;
hwmgr            2176 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed -
hwmgr            2177 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin;
hwmgr            2178 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh -
hwmgr            2179 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed;
hwmgr            2184 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	fan_table.TempMin = cpu_to_be16((50 + hwmgr->
hwmgr            2186 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	fan_table.TempMed = cpu_to_be16((50 + hwmgr->
hwmgr            2188 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	fan_table.TempMax = cpu_to_be16((50 + hwmgr->
hwmgr            2196 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	fan_table.HystDown = cpu_to_be16(hwmgr->
hwmgr            2205 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	reference_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
hwmgr            2207 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	fan_table.RefreshPeriod = cpu_to_be32((hwmgr->
hwmgr            2214 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			hwmgr->device, CGS_IND_REG__SMC,
hwmgr            2217 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	res = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.fan_table_start,
hwmgr            2221 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	if (!res && hwmgr->thermal_controller.
hwmgr            2223 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		res = smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            2225 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				hwmgr->thermal_controller.
hwmgr            2228 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	if (!res && hwmgr->thermal_controller.
hwmgr            2230 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		res = smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            2232 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				hwmgr->thermal_controller.
hwmgr            2236 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr            2243 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_thermal_avfs_enable(struct pp_hwmgr *hwmgr)
hwmgr            2245 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	if (!hwmgr->avfs_supported)
hwmgr            2248 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAvfs);
hwmgr            2253 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
hwmgr            2255 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            2259 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		return fiji_program_memory_timing_parameters(hwmgr);
hwmgr            2264 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_update_sclk_threshold(struct pp_hwmgr *hwmgr)
hwmgr            2266 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            2267 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
hwmgr            2272 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            2281 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				hwmgr,
hwmgr            2289 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	result = fiji_program_mem_timing_parameters(hwmgr);
hwmgr            2368 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
hwmgr            2370 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
hwmgr            2373 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            2383 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
hwmgr            2387 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	cgs_write_ind_register(hwmgr->device,
hwmgr            2390 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            2392 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            2394 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            2400 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_update_vce_smc_table(struct pp_hwmgr *hwmgr)
hwmgr            2402 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
hwmgr            2405 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            2407 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            2418 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
hwmgr            2422 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	cgs_write_ind_register(hwmgr->device,
hwmgr            2425 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
hwmgr            2426 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            2432 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
hwmgr            2436 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		fiji_update_uvd_smc_table(hwmgr);
hwmgr            2439 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		fiji_update_vce_smc_table(hwmgr);
hwmgr            2447 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_process_firmware_header(struct pp_hwmgr *hwmgr)
hwmgr            2449 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            2450 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct fiji_smumgr *smu_data = (struct fiji_smumgr *)(hwmgr->smu_backend);
hwmgr            2455 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	result = smu7_read_smc_sram_dword(hwmgr,
hwmgr            2465 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	result = smu7_read_smc_sram_dword(hwmgr,
hwmgr            2477 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	result = smu7_read_smc_sram_dword(hwmgr,
hwmgr            2485 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	result = smu7_read_smc_sram_dword(hwmgr,
hwmgr            2495 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	result = smu7_read_smc_sram_dword(hwmgr,
hwmgr            2505 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	result = smu7_read_smc_sram_dword(hwmgr,
hwmgr            2511 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		hwmgr->microcode_version_info.SMC = tmp;
hwmgr            2518 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
hwmgr            2524 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP,
hwmgr            2525 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
hwmgr            2526 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP,
hwmgr            2527 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING));
hwmgr            2528 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP,
hwmgr            2529 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2));
hwmgr            2530 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP,
hwmgr            2531 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1));
hwmgr            2532 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP,
hwmgr            2533 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0));
hwmgr            2534 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP,
hwmgr            2535 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1));
hwmgr            2536 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP,
hwmgr            2537 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING));
hwmgr            2542 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static bool fiji_is_dpm_running(struct pp_hwmgr *hwmgr)
hwmgr            2544 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
hwmgr            2549 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c static int fiji_update_dpm_settings(struct pp_hwmgr *hwmgr,
hwmgr            2552 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            2554 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			(hwmgr->smu_backend);
hwmgr            2575 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_FreezeLevel);
hwmgr            2584 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
hwmgr            2586 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
hwmgr            2598 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
hwmgr            2601 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
hwmgr            2605 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_UnfreezeLevel);
hwmgr            2610 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_FreezeLevel);
hwmgr            2619 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
hwmgr            2621 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
hwmgr            2633 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
hwmgr            2636 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
hwmgr            2640 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 			smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_UnfreezeLevel);
hwmgr             109 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_start_smc(struct pp_hwmgr *hwmgr)
hwmgr             111 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             117 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static void iceland_reset_smc(struct pp_hwmgr *hwmgr)
hwmgr             119 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             125 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static void iceland_stop_smc_clock(struct pp_hwmgr *hwmgr)
hwmgr             127 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             132 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static void iceland_start_smc_clock(struct pp_hwmgr *hwmgr)
hwmgr             134 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             139 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_smu_start_smc(struct pp_hwmgr *hwmgr)
hwmgr             142 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	smu7_program_jump_on_start(hwmgr);
hwmgr             145 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	iceland_start_smc_clock(hwmgr);
hwmgr             148 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	iceland_start_smc(hwmgr);
hwmgr             150 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	PHM_WAIT_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS,
hwmgr             157 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_upload_smc_firmware_data(struct pp_hwmgr *hwmgr,
hwmgr             166 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_0, start_addr);
hwmgr             167 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 1);
hwmgr             171 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		cgs_write_register(hwmgr->device, mmSMC_IND_DATA_0, data);
hwmgr             176 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, 0);
hwmgr             184 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_smu_upload_firmware_image(struct pp_hwmgr *hwmgr)
hwmgr             189 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	if (hwmgr == NULL || hwmgr->device == NULL)
hwmgr             193 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	cgs_get_firmware_info(hwmgr->device,
hwmgr             205 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	hwmgr->smu_version = info.version;
hwmgr             207 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	PHM_WAIT_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
hwmgr             211 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	val = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             213 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             217 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	iceland_stop_smc_clock(hwmgr);
hwmgr             220 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	iceland_reset_smc(hwmgr);
hwmgr             221 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	iceland_upload_smc_firmware_data(hwmgr, info.image_size,
hwmgr             228 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_request_smu_load_specific_fw(struct pp_hwmgr *hwmgr,
hwmgr             234 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_start_smu(struct pp_hwmgr *hwmgr)
hwmgr             236 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct iceland_smumgr *priv = hwmgr->smu_backend;
hwmgr             239 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	if (!smu7_is_smc_ram_running(hwmgr)) {
hwmgr             240 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		result = iceland_smu_upload_firmware_image(hwmgr);
hwmgr             244 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		iceland_smu_start_smc(hwmgr);
hwmgr             250 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	smu7_read_smc_sram_dword(hwmgr,
hwmgr             255 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = smu7_request_smu_load_fw(hwmgr);
hwmgr             260 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_smu_init(struct pp_hwmgr *hwmgr)
hwmgr             269 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	hwmgr->smu_backend = iceland_priv;
hwmgr             271 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	if (smu7_init(hwmgr)) {
hwmgr             280 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static void iceland_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
hwmgr             282 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
hwmgr             283 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             306 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_populate_svi_load_line(struct pp_hwmgr *hwmgr)
hwmgr             308 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
hwmgr             319 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_populate_tdc_limit(struct pp_hwmgr *hwmgr)
hwmgr             322 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
hwmgr             325 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	tdc_limit = (uint16_t)(hwmgr->dyn_state.cac_dtp_table->usTDC * 256);
hwmgr             335 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
hwmgr             337 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
hwmgr             341 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	if (smu7_read_smc_sram_dword(hwmgr,
hwmgr             354 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
hwmgr             359 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
hwmgr             362 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
hwmgr             371 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
hwmgr             373 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
hwmgr             376 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct phm_cac_tdp_table *cac_table = hwmgr->dyn_state.cac_dtp_table;
hwmgr             389 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_populate_bapm_vddc_vid_sidd(struct pp_hwmgr *hwmgr)
hwmgr             392 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
hwmgr             396 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.cac_leakage_table,
hwmgr             398 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count <= 8,
hwmgr             400 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count == hwmgr->dyn_state.vddc_dependency_on_sclk->count,
hwmgr             403 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_EVV)) {
hwmgr             404 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		for (i = 0; (uint32_t) i < hwmgr->dyn_state.cac_leakage_table->count; i++) {
hwmgr             405 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 			lo_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc1);
hwmgr             406 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 			hi_vid[i] = convert_to_vid(hwmgr->dyn_state.cac_leakage_table->entries[i].Vddc2);
hwmgr             415 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_populate_vddc_vid(struct pp_hwmgr *hwmgr)
hwmgr             418 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
hwmgr             420 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             435 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_populate_pm_fuses(struct pp_hwmgr *hwmgr)
hwmgr             437 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
hwmgr             440 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr             442 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		if (smu7_read_smc_sram_dword(hwmgr,
hwmgr             451 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		if (iceland_populate_bapm_vddc_vid_sidd(hwmgr))
hwmgr             457 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		if (iceland_populate_vddc_vid(hwmgr))
hwmgr             463 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		if (iceland_populate_svi_load_line(hwmgr))
hwmgr             468 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		if (iceland_populate_tdc_limit(hwmgr))
hwmgr             472 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		if (iceland_populate_dw8(hwmgr, pm_fuse_table_offset))
hwmgr             479 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		if (0 != iceland_populate_temperature_scaler(hwmgr))
hwmgr             485 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		if (iceland_populate_gnb_lpml(hwmgr))
hwmgr             491 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		if (iceland_populate_bapm_vddc_base_leakage_sidd(hwmgr))
hwmgr             496 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
hwmgr             506 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
hwmgr             530 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_get_std_voltage_value_sidd(struct pp_hwmgr *hwmgr,
hwmgr             540 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.vddc_dependency_on_sclk,
hwmgr             544 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	if (NULL == hwmgr->dyn_state.cac_leakage_table) {
hwmgr             554 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) {
hwmgr             555 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		if (tab->value == hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) {
hwmgr             557 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 			if ((uint32_t)v_index < hwmgr->dyn_state.cac_leakage_table->count) {
hwmgr             558 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 				*lo = hwmgr->dyn_state.cac_leakage_table->entries[v_index].Vddc * VOLTAGE_SCALE;
hwmgr             559 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 				*hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[v_index].Leakage * VOLTAGE_SCALE);
hwmgr             562 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 				*lo = hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Vddc * VOLTAGE_SCALE;
hwmgr             563 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 				*hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Leakage * VOLTAGE_SCALE);
hwmgr             574 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		for (v_index = 0; (uint32_t)v_index < hwmgr->dyn_state.vddc_dependency_on_sclk->count; v_index++) {
hwmgr             575 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 			if (tab->value <= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[v_index].v) {
hwmgr             577 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 				if ((uint32_t)v_index < hwmgr->dyn_state.cac_leakage_table->count) {
hwmgr             578 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 					*lo = hwmgr->dyn_state.cac_leakage_table->entries[v_index].Vddc * VOLTAGE_SCALE;
hwmgr             579 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 					*hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[v_index].Leakage) * VOLTAGE_SCALE;
hwmgr             582 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 					*lo = hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Vddc * VOLTAGE_SCALE;
hwmgr             583 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 					*hi = (uint16_t)(hwmgr->dyn_state.cac_leakage_table->entries[hwmgr->dyn_state.cac_leakage_table->count - 1].Leakage * VOLTAGE_SCALE);
hwmgr             596 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_populate_smc_voltage_table(struct pp_hwmgr *hwmgr,
hwmgr             602 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = iceland_get_std_voltage_value_sidd(hwmgr, tab,
hwmgr             617 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_populate_smc_vddc_table(struct pp_hwmgr *hwmgr,
hwmgr             622 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             626 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		result = iceland_populate_smc_voltage_table(hwmgr,
hwmgr             643 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_populate_smc_vdd_ci_table(struct pp_hwmgr *hwmgr,
hwmgr             646 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             653 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		result = iceland_populate_smc_voltage_table(hwmgr,
hwmgr             668 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
hwmgr             671 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             678 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		result = iceland_populate_smc_voltage_table(hwmgr,
hwmgr             694 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
hwmgr             699 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = iceland_populate_smc_vddc_table(hwmgr, table);
hwmgr             703 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = iceland_populate_smc_vdd_ci_table(hwmgr, table);
hwmgr             707 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = iceland_populate_smc_mvdd_table(hwmgr, table);
hwmgr             714 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_populate_ulv_level(struct pp_hwmgr *hwmgr,
hwmgr             719 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             724 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = pp_tables_get_response_times(hwmgr, &voltage_response_time, &ulv_voltage);
hwmgr             734 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v)
hwmgr             738 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 			state->VddcOffset = (uint16_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage);
hwmgr             741 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		if (ulv_voltage > hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v)
hwmgr             745 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 					(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage)
hwmgr             758 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_populate_ulv_state(struct pp_hwmgr *hwmgr,
hwmgr             761 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	return iceland_populate_ulv_level(hwmgr, ulv_level);
hwmgr             764 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU71_Discrete_DpmTable *table)
hwmgr             766 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             768 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
hwmgr             795 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_calculate_sclk_params(struct pp_hwmgr *hwmgr,
hwmgr             798 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             811 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock,  &dividers);
hwmgr             817 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	reference_clock = atomctrl_get_reference_clock(hwmgr);
hwmgr             838 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr             843 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		if (0 == atomctrl_get_engine_clock_spread_spectrum(hwmgr, vcoFreq, &ss_info)) {
hwmgr             873 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_populate_phase_value_based_on_sclk(struct pp_hwmgr *hwmgr,
hwmgr             891 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
hwmgr             896 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             898 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = iceland_calculate_sclk_params(hwmgr, engine_clock, graphic_level);
hwmgr             901 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = iceland_get_dependency_volt_by_clk(hwmgr,
hwmgr             902 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		hwmgr->dyn_state.vddc_dependency_on_sclk, engine_clock,
hwmgr             912 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		iceland_populate_phase_value_based_on_sclk(hwmgr,
hwmgr             913 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 				hwmgr->dyn_state.vddc_phase_shed_limits_table,
hwmgr             932 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 			hwmgr->display_config->min_core_set_clock_in_sr;
hwmgr             934 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr             959 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
hwmgr             961 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             962 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
hwmgr             981 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		result = iceland_populate_single_graphic_level(hwmgr,
hwmgr            1037 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = smu7_copy_bytes_to_smc(hwmgr, level_array_adress,
hwmgr            1045 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		struct pp_hwmgr *hwmgr,
hwmgr            1052 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1067 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = atomctrl_get_memory_pll_dividers_si(hwmgr,
hwmgr            1095 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            1115 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		uint32_t reference_clock = atomctrl_get_mpll_reference_clock(hwmgr);
hwmgr            1127 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		if (0 == atomctrl_get_memory_clock_spread_spectrum(hwmgr, freq_nom, &ss_info)) {
hwmgr            1210 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_populate_phase_value_based_on_mclk(struct pp_hwmgr *hwmgr, const struct phm_phase_shedding_limits_table *pl,
hwmgr            1228 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		struct pp_hwmgr *hwmgr,
hwmgr            1233 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1240 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	if (hwmgr->dyn_state.vddc_dependency_on_mclk != NULL) {
hwmgr            1241 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		result = iceland_get_dependency_volt_by_clk(hwmgr,
hwmgr            1242 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 			hwmgr->dyn_state.vddc_dependency_on_mclk, memory_clock, &memory_level->MinVddc);
hwmgr            1249 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	} else if (NULL != hwmgr->dyn_state.vddci_dependency_on_mclk) {
hwmgr            1250 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		result = iceland_get_dependency_volt_by_clk(hwmgr,
hwmgr            1251 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 				hwmgr->dyn_state.vddci_dependency_on_mclk,
hwmgr            1261 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		iceland_populate_phase_value_based_on_mclk(hwmgr, hwmgr->dyn_state.vddc_phase_shed_limits_table,
hwmgr            1282 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
hwmgr            1283 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	data->display_timing.vrefresh = hwmgr->display_config->vrefresh;
hwmgr            1308 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 					((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC7) >> 16) & 0xf))
hwmgr            1309 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 				dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
hwmgr            1311 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 				dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC6) >> 1) & 0x1) ? 1 : 0;
hwmgr            1317 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
hwmgr            1320 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = iceland_calculate_mclk_params(hwmgr,
hwmgr            1346 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
hwmgr            1348 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1349 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
hwmgr            1364 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		result = iceland_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value,
hwmgr            1388 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = smu7_copy_bytes_to_smc(hwmgr,
hwmgr            1395 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_populate_mvdd_value(struct pp_hwmgr *hwmgr, uint32_t mclk,
hwmgr            1398 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1404 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		for (i = 0; i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count; i++) {
hwmgr            1405 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 			if (mclk <= hwmgr->dyn_state.mvdd_dependency_on_mclk->entries[i].clk) {
hwmgr            1412 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		PP_ASSERT_WITH_CODE(i < hwmgr->dyn_state.mvdd_dependency_on_mclk->count,
hwmgr            1422 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
hwmgr            1426 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1447 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr);
hwmgr            1450 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = atomctrl_get_engine_pll_dividers_vi(hwmgr,
hwmgr            1504 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	if (0 == iceland_populate_mvdd_value(hwmgr, 0, &voltage_level))
hwmgr            1564 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
hwmgr            1570 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
hwmgr            1576 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
hwmgr            1583 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		struct pp_hwmgr *hwmgr,
hwmgr            1594 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
hwmgr            1600 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	dramTiming  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
hwmgr            1601 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	dramTiming2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
hwmgr            1602 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	burstTime = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
hwmgr            1611 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
hwmgr            1613 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1614 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
hwmgr            1624 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 				(hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value,
hwmgr            1636 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 				hwmgr,
hwmgr            1647 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
hwmgr            1651 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1652 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
hwmgr            1688 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_populate_mc_reg_address(struct pp_hwmgr *hwmgr,
hwmgr            1691 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	const struct iceland_smumgr *smu_data = (struct iceland_smumgr *)hwmgr->smu_backend;
hwmgr            1728 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_convert_mc_reg_table_entry_to_smc(struct pp_hwmgr *hwmgr,
hwmgr            1733 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
hwmgr            1753 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
hwmgr            1757 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1763 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 				hwmgr,
hwmgr            1775 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
hwmgr            1777 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
hwmgr            1778 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1788 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = iceland_convert_mc_reg_table_to_smc(hwmgr, &(smu_data->mc_regs));
hwmgr            1796 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	return  smu7_copy_bytes_to_smc(hwmgr, address,
hwmgr            1802 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
hwmgr            1805 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
hwmgr            1808 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = iceland_populate_mc_reg_address(hwmgr, &(smu_data->mc_regs));
hwmgr            1812 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = iceland_convert_mc_reg_table_to_smc(hwmgr, &smu_data->mc_regs);
hwmgr            1816 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	return smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.mc_reg_table_start,
hwmgr            1820 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_populate_smc_initial_state(struct pp_hwmgr *hwmgr)
hwmgr            1822 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1823 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
hwmgr            1826 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->count);
hwmgr            1829 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		if (hwmgr->dyn_state.vddc_dependency_on_sclk->entries[level].clk
hwmgr            1836 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	count = (uint8_t)(hwmgr->dyn_state.vddc_dependency_on_mclk->count);
hwmgr            1839 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		if (hwmgr->dyn_state.vddc_dependency_on_mclk->entries[level].clk
hwmgr            1849 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
hwmgr            1851 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1852 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
hwmgr            1855 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct phm_cac_tdp_table *cac_dtp_table = hwmgr->dyn_state.cac_dtp_table;
hwmgr            1856 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct phm_ppm_table *ppm = hwmgr->dyn_state.ppm_parameter_table;
hwmgr            1907 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_populate_smc_svi2_config(struct pp_hwmgr *hwmgr,
hwmgr            1910 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1929 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_init_smc_table(struct pp_hwmgr *hwmgr)
hwmgr            1932 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1933 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
hwmgr            1937 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	iceland_initialize_power_tune_defaults(hwmgr);
hwmgr            1941 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		iceland_populate_smc_voltage_tables(hwmgr, table);
hwmgr            1944 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            1949 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            1958 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		result = iceland_populate_ulv_state(hwmgr, &(smu_data->ulv_setting));
hwmgr            1962 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
hwmgr            1966 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = iceland_populate_smc_link_level(hwmgr, table);
hwmgr            1970 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = iceland_populate_all_graphic_levels(hwmgr);
hwmgr            1974 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = iceland_populate_all_memory_levels(hwmgr);
hwmgr            1978 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = iceland_populate_smc_acpi_level(hwmgr, table);
hwmgr            1982 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = iceland_populate_smc_vce_level(hwmgr, table);
hwmgr            1986 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = iceland_populate_smc_acp_level(hwmgr, table);
hwmgr            1992 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = iceland_program_memory_timing_parameters(hwmgr);
hwmgr            1996 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = iceland_populate_smc_uvd_level(hwmgr, table);
hwmgr            2003 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = iceland_populate_smc_boot_level(hwmgr, table);
hwmgr            2007 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = iceland_populate_smc_initial_state(hwmgr);
hwmgr            2010 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = iceland_populate_bapm_parameters_in_dpm_table(hwmgr);
hwmgr            2034 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = iceland_populate_smc_svi2_config(hwmgr, table);
hwmgr            2057 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.dpm_table_start +
hwmgr            2067 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = smu7_copy_bytes_to_smc(hwmgr,
hwmgr            2074 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = iceland_populate_initial_mc_reg_table(hwmgr);
hwmgr            2078 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = iceland_populate_pm_fuses(hwmgr);
hwmgr            2085 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c int iceland_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
hwmgr            2087 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct smu7_smumgr *smu7_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
hwmgr            2096 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl))
hwmgr            2099 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	if (hwmgr->thermal_controller.fanInfo.bNoFan) {
hwmgr            2100 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr            2106 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl);
hwmgr            2110 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_FDO_CTRL1, FMAX_DUTY100);
hwmgr            2113 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl);
hwmgr            2117 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin * duty100;
hwmgr            2121 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed - hwmgr->thermal_controller.advanceFanControlParameters.usTMin;
hwmgr            2122 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh - hwmgr->thermal_controller.advanceFanControlParameters.usTMed;
hwmgr            2124 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed - hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin;
hwmgr            2125 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh - hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed;
hwmgr            2130 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	fan_table.TempMin = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMin) / 100);
hwmgr            2131 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	fan_table.TempMed = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMed) / 100);
hwmgr            2132 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	fan_table.TempMax = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMax) / 100);
hwmgr            2139 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	fan_table.HystDown = cpu_to_be16(hwmgr->thermal_controller.advanceFanControlParameters.ucTHyst);
hwmgr            2147 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	reference_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
hwmgr            2149 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	fan_table.RefreshPeriod = cpu_to_be32((hwmgr->thermal_controller.advanceFanControlParameters.ulCycleDelay * reference_clock) / 1600);
hwmgr            2153 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_MULT_THERMAL_CTRL, TEMP_SEL);
hwmgr            2157 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	res = smu7_copy_bytes_to_smc(hwmgr, smu7_data->fan_table_start, (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), SMC_RAM_END);
hwmgr            2163 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
hwmgr            2165 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            2169 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		return iceland_program_memory_timing_parameters(hwmgr);
hwmgr            2174 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_update_sclk_threshold(struct pp_hwmgr *hwmgr)
hwmgr            2176 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            2177 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
hwmgr            2182 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            2191 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 				hwmgr,
hwmgr            2200 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = iceland_update_and_upload_mc_reg_table(hwmgr);
hwmgr            2204 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = iceland_program_mem_timing_parameters(hwmgr);
hwmgr            2277 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_process_firmware_header(struct pp_hwmgr *hwmgr)
hwmgr            2279 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            2280 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct smu7_smumgr *smu7_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
hwmgr            2286 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = smu7_read_smc_sram_dword(hwmgr,
hwmgr            2297 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = smu7_read_smc_sram_dword(hwmgr,
hwmgr            2310 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = smu7_read_smc_sram_dword(hwmgr,
hwmgr            2319 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = smu7_read_smc_sram_dword(hwmgr,
hwmgr            2330 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = smu7_read_smc_sram_dword(hwmgr,
hwmgr            2342 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = smu7_read_smc_sram_dword(hwmgr,
hwmgr            2348 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		hwmgr->microcode_version_info.SMC = tmp;
hwmgr            2353 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = smu7_read_smc_sram_dword(hwmgr,
hwmgr            2369 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static uint8_t iceland_get_memory_modile_index(struct pp_hwmgr *hwmgr)
hwmgr            2371 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16));
hwmgr            2509 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_set_mc_special_registers(struct pp_hwmgr *hwmgr,
hwmgr            2514 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            2523 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 			temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS);
hwmgr            2535 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 			temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS);
hwmgr            2564 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 			temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1);
hwmgr            2602 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static int iceland_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
hwmgr            2605 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	struct iceland_smumgr *smu_data = (struct iceland_smumgr *)(hwmgr->smu_backend);
hwmgr            2608 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	uint8_t module_index = iceland_get_memory_modile_index(hwmgr);
hwmgr            2616 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
hwmgr            2617 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING));
hwmgr            2618 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_DLL_STBY_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_DLL_STBY));
hwmgr            2619 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0));
hwmgr            2620 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1));
hwmgr            2621 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL));
hwmgr            2622 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD));
hwmgr            2623 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL));
hwmgr            2624 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING));
hwmgr            2625 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2));
hwmgr            2626 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_EMRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS));
hwmgr            2627 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS));
hwmgr            2628 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS1_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1));
hwmgr            2629 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0));
hwmgr            2630 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1));
hwmgr            2631 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0));
hwmgr            2632 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1));
hwmgr            2633 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING));
hwmgr            2634 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS2_LP, cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS2));
hwmgr            2635 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2));
hwmgr            2637 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table);
hwmgr            2644 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 		result = iceland_set_mc_special_registers(hwmgr, ni_table);
hwmgr            2655 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c static bool iceland_is_dpm_running(struct pp_hwmgr *hwmgr)
hwmgr            2657 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
hwmgr              96 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_perform_btc(struct pp_hwmgr *hwmgr)
hwmgr              99 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
hwmgr             102 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		if (0 != smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_PerformBtc, smu_data->avfs_btc_param)) {
hwmgr             110 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, 0x50000000);
hwmgr             112 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0xffffffff);
hwmgr             113 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0);
hwmgr             119 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_setup_graphics_level_structure(struct pp_hwmgr *hwmgr)
hwmgr             130 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(hwmgr,
hwmgr             141 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, vr_config_address,
hwmgr             148 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
hwmgr             156 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
hwmgr             165 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
hwmgr             174 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_avfs_event_mgr(struct pp_hwmgr *hwmgr)
hwmgr             176 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
hwmgr             178 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	if (!hwmgr->avfs_supported)
hwmgr             181 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	PP_ASSERT_WITH_CODE(0 == polaris10_setup_graphics_level_structure(hwmgr),
hwmgr             187 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		PP_ASSERT_WITH_CODE(0 == smu7_setup_pwr_virus(hwmgr),
hwmgr             192 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	PP_ASSERT_WITH_CODE(0 == polaris10_perform_btc(hwmgr),
hwmgr             199 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
hwmgr             207 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             210 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	result = smu7_upload_smu_firmware_image(hwmgr);
hwmgr             215 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0);
hwmgr             217 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             221 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             225 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1);
hwmgr             229 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	smu7_send_msg_to_smc_offset(hwmgr);
hwmgr             234 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, SMU_STATUS, SMU_DONE, 0);
hwmgr             236 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	if (1 != PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             240 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0);
hwmgr             242 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             245 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             249 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
hwmgr             254 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr)
hwmgr             259 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0);
hwmgr             263 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             266 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             270 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	result = smu7_upload_smu_firmware_image(hwmgr);
hwmgr             275 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	smu7_program_jump_on_start(hwmgr);
hwmgr             277 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             280 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             285 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
hwmgr             291 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_start_smu(struct pp_hwmgr *hwmgr)
hwmgr             294 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
hwmgr             297 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	if (!smu7_is_smc_ram_running(hwmgr) && hwmgr->not_vf) {
hwmgr             298 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		smu_data->protected_mode = (uint8_t) (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE));
hwmgr             299 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		smu_data->smu7_data.security_hard_key = (uint8_t) (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL));
hwmgr             303 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			result = polaris10_start_smu_in_non_protection_mode(hwmgr);
hwmgr             305 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			result = polaris10_start_smu_in_protection_mode(hwmgr);
hwmgr             310 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		polaris10_avfs_event_mgr(hwmgr);
hwmgr             314 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	smu7_read_smc_sram_dword(hwmgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, SoftRegisters),
hwmgr             317 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	result = smu7_request_smu_load_fw(hwmgr);
hwmgr             322 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static bool polaris10_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
hwmgr             326 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_EFUSE_0 + (49*4));
hwmgr             334 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_smu_init(struct pp_hwmgr *hwmgr)
hwmgr             342 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	hwmgr->smu_backend = smu_data;
hwmgr             344 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	if (smu7_init(hwmgr)) {
hwmgr             352 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
hwmgr             358 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             424 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
hwmgr             426 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
hwmgr             431 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr             434 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			&hwmgr->thermal_controller.advanceFanControlParameters;
hwmgr             472 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_populate_svi_load_line(struct pp_hwmgr *hwmgr)
hwmgr             474 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
hwmgr             485 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_populate_tdc_limit(struct pp_hwmgr *hwmgr)
hwmgr             488 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
hwmgr             490 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr             503 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
hwmgr             505 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
hwmgr             509 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	if (smu7_read_smc_sram_dword(hwmgr,
hwmgr             527 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
hwmgr             530 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
hwmgr             539 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
hwmgr             541 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
hwmgr             544 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	if ((hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity & (1 << 15))
hwmgr             545 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		|| 0 == hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity)
hwmgr             546 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity =
hwmgr             547 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity;
hwmgr             550 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity);
hwmgr             554 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
hwmgr             557 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
hwmgr             566 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
hwmgr             568 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
hwmgr             570 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr             586 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_populate_pm_fuses(struct pp_hwmgr *hwmgr)
hwmgr             588 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
hwmgr             591 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr             593 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		if (smu7_read_smc_sram_dword(hwmgr,
hwmgr             601 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		if (polaris10_populate_svi_load_line(hwmgr))
hwmgr             606 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		if (polaris10_populate_tdc_limit(hwmgr))
hwmgr             610 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		if (polaris10_populate_dw8(hwmgr, pm_fuse_table_offset))
hwmgr             616 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		if (0 != polaris10_populate_temperature_scaler(hwmgr))
hwmgr             621 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		if (polaris10_populate_fuzzy_fan(hwmgr))
hwmgr             626 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		if (polaris10_populate_gnb_lpml(hwmgr))
hwmgr             631 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		if (polaris10_populate_bapm_vddc_base_leakage_sidd(hwmgr))
hwmgr             636 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
hwmgr             646 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
hwmgr             649 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             673 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_populate_smc_vddci_table(struct pp_hwmgr *hwmgr,
hwmgr             677 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             698 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_populate_cac_table(struct pp_hwmgr *hwmgr,
hwmgr             703 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             705 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr             724 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
hwmgr             727 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	polaris10_populate_smc_vddci_table(hwmgr, table);
hwmgr             728 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	polaris10_populate_smc_mvdd_table(hwmgr, table);
hwmgr             729 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	polaris10_populate_cac_table(hwmgr, table);
hwmgr             734 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr,
hwmgr             737 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             739 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr             748 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	if (hwmgr->chip_id == CHIP_POLARIS12 || hwmgr->is_kicker)
hwmgr             760 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_populate_ulv_state(struct pp_hwmgr *hwmgr,
hwmgr             763 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	return polaris10_populate_ulv_level(hwmgr, &table->Ulv);
hwmgr             766 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_populate_smc_link_level(struct pp_hwmgr *hwmgr,
hwmgr             769 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             770 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
hwmgr             798 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr,
hwmgr             801 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
hwmgr             806 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	ref_clk = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
hwmgr             808 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) {
hwmgr             841 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr,
hwmgr             844 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
hwmgr             855 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock,  &dividers);
hwmgr             871 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	ref_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
hwmgr             906 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
hwmgr             912 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             914 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr             918 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	result = polaris10_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);
hwmgr             920 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	if (hwmgr->od_enabled)
hwmgr             926 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	result = polaris10_get_dependency_volt_by_clk(hwmgr,
hwmgr             944 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr;
hwmgr             946 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
hwmgr             948 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 								hwmgr->display_config->min_core_set_clock_in_sr);
hwmgr             977 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
hwmgr             979 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             980 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
hwmgr             983 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr             999 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	polaris10_get_sclk_range_table(hwmgr, &(smu_data->smc_state_table));
hwmgr            1003 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		result = polaris10_populate_single_graphic_level(hwmgr,
hwmgr            1013 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            1064 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
hwmgr            1071 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
hwmgr            1074 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1076 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            1082 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	if (hwmgr->od_enabled)
hwmgr            1088 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		result = polaris10_get_dependency_volt_by_clk(hwmgr,
hwmgr            1106 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
hwmgr            1107 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	data->display_timing.vrefresh = hwmgr->display_config->vrefresh;
hwmgr            1111 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		(PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
hwmgr            1124 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
hwmgr            1126 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1127 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
hwmgr            1143 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		result = polaris10_populate_single_memory_level(hwmgr,
hwmgr            1168 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
hwmgr            1174 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_populate_mvdd_value(struct pp_hwmgr *hwmgr,
hwmgr            1177 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1179 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            1199 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
hwmgr            1204 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1206 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            1215 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	result = polaris10_get_dependency_volt_by_clk(hwmgr,
hwmgr            1224 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	result = polaris10_calculate_sclk_params(hwmgr, sclk_frequency,  &(table->ACPILevel.SclkSetting));
hwmgr            1250 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	result = polaris10_get_dependency_volt_by_clk(hwmgr,
hwmgr            1261 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		polaris10_populate_mvdd_value(hwmgr,
hwmgr            1265 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	if (0 == polaris10_populate_mvdd_value(hwmgr, 0, &vol_level))
hwmgr            1286 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
hwmgr            1293 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            1296 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1322 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
hwmgr            1336 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
hwmgr            1345 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
hwmgr            1350 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
hwmgr            1351 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
hwmgr            1352 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
hwmgr            1362 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
hwmgr            1364 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1365 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
hwmgr            1372 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			result = polaris10_populate_memory_timing_parameters(hwmgr,
hwmgr            1377 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				result = atomctrl_set_ac_timing_ai(hwmgr, hw_data->dpm_table.mclk_table.dpm_levels[j].value, j);
hwmgr            1384 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			hwmgr,
hwmgr            1392 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
hwmgr            1399 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            1402 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1427 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
hwmgr            1434 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
hwmgr            1449 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
hwmgr            1453 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1481 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
hwmgr            1483 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1484 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
hwmgr            1486 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            1511 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
hwmgr            1514 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
hwmgr            1518 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            1527 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
hwmgr            1532 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	if (hwmgr->chip_id == CHIP_POLARIS10) {
hwmgr            1533 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		if (hwmgr->is_kicker) {
hwmgr            1540 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	} else if (hwmgr->chip_id == CHIP_POLARIS11) {
hwmgr            1541 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		if (hwmgr->is_kicker) {
hwmgr            1559 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		if (hwmgr->chip_id == CHIP_POLARIS10) {
hwmgr            1581 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr            1588 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
hwmgr            1590 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
hwmgr            1595 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr,
hwmgr            1598 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1599 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
hwmgr            1629 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, smu_data->smu7_data.soft_regs_start +
hwmgr            1640 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
hwmgr            1642 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1643 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
hwmgr            1644 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr            1654 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			(struct phm_ppt_v1_information *)hwmgr->pptable;
hwmgr            1659 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	if (!hwmgr->avfs_supported)
hwmgr            1662 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	result = atomctrl_get_avfs_information(hwmgr, &avfs_params);
hwmgr            1689 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		} else if (hwmgr->chip_id == CHIP_POLARIS12 && !hwmgr->is_kicker) {
hwmgr            1748 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		result = smu7_read_smc_sram_dword(hwmgr,
hwmgr            1752 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		smu7_copy_bytes_to_smc(hwmgr,
hwmgr            1758 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		result = smu7_read_smc_sram_dword(hwmgr,
hwmgr            1761 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		smu7_copy_bytes_to_smc(hwmgr,
hwmgr            1776 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_init_arb_table_index(struct pp_hwmgr *hwmgr)
hwmgr            1778 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
hwmgr            1790 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	result = smu7_read_smc_sram_dword(hwmgr,
hwmgr            1799 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	return smu7_write_smc_sram_dword(hwmgr,
hwmgr            1803 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static void polaris10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
hwmgr            1805 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
hwmgr            1807 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			(struct  phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            1820 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
hwmgr            1823 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1824 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
hwmgr            1827 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            1833 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	polaris10_initialize_power_tune_defaults(hwmgr);
hwmgr            1836 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		polaris10_populate_smc_voltage_tables(hwmgr, table);
hwmgr            1839 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            1843 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            1851 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		result = polaris10_populate_ulv_state(hwmgr, table);
hwmgr            1854 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
hwmgr            1858 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	result = polaris10_populate_smc_link_level(hwmgr, table);
hwmgr            1862 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	result = polaris10_populate_all_graphic_levels(hwmgr);
hwmgr            1866 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	result = polaris10_populate_all_memory_levels(hwmgr);
hwmgr            1870 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	result = polaris10_populate_smc_acpi_level(hwmgr, table);
hwmgr            1874 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	result = polaris10_populate_smc_vce_level(hwmgr, table);
hwmgr            1882 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	result = polaris10_program_memory_timing_parameters(hwmgr);
hwmgr            1886 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	result = polaris10_populate_smc_uvd_level(hwmgr, table);
hwmgr            1890 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	result = polaris10_populate_smc_boot_level(hwmgr, table);
hwmgr            1894 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	result = polaris10_populate_smc_initailial_state(hwmgr);
hwmgr            1898 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	result = polaris10_populate_bapm_parameters_in_dpm_table(hwmgr);
hwmgr            1902 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            1904 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		result = polaris10_populate_clock_stretcher_data_table(hwmgr);
hwmgr            1910 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	result = polaris10_populate_avfs_parameters(hwmgr);
hwmgr            1934 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	result = polaris10_populate_vr_config(hwmgr, table);
hwmgr            1941 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
hwmgr            1945 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr            1949 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
hwmgr            1952 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr            1956 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr            1961 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
hwmgr            1963 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr            1973 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A)
hwmgr            1978 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_RegulatorHot)
hwmgr            1979 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		&& phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_CombinePCCWithThermalSignal))
hwmgr            1989 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, smu_data->bif_sclk_table[i], &dividers);
hwmgr            2013 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	result = smu7_copy_bytes_to_smc(hwmgr,
hwmgr            2022 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	result = polaris10_init_arb_table_index(hwmgr);
hwmgr            2026 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	result = polaris10_populate_pm_fuses(hwmgr);
hwmgr            2033 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
hwmgr            2035 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            2039 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		return polaris10_program_memory_timing_parameters(hwmgr);
hwmgr            2044 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c int polaris10_thermal_avfs_enable(struct pp_hwmgr *hwmgr)
hwmgr            2046 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            2048 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	if (!hwmgr->avfs_supported)
hwmgr            2051 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            2054 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAvfs);
hwmgr            2060 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ApplyAvfsCksOffVoltage);
hwmgr            2065 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
hwmgr            2067 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
hwmgr            2076 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	if (hwmgr->thermal_controller.fanInfo.bNoFan) {
hwmgr            2077 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr            2083 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr            2088 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr            2092 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr            2098 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	if (hwmgr->thermal_controller.use_hw_fan_control)
hwmgr            2101 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.
hwmgr            2106 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed -
hwmgr            2107 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			hwmgr->thermal_controller.advanceFanControlParameters.usTMin;
hwmgr            2108 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh -
hwmgr            2109 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			hwmgr->thermal_controller.advanceFanControlParameters.usTMed;
hwmgr            2111 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed -
hwmgr            2112 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin;
hwmgr            2113 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh -
hwmgr            2114 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed;
hwmgr            2119 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	fan_table.TempMin = cpu_to_be16((50 + hwmgr->
hwmgr            2121 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	fan_table.TempMed = cpu_to_be16((50 + hwmgr->
hwmgr            2123 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	fan_table.TempMax = cpu_to_be16((50 + hwmgr->
hwmgr            2131 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	fan_table.HystDown = cpu_to_be16(hwmgr->
hwmgr            2140 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	reference_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
hwmgr            2142 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	fan_table.RefreshPeriod = cpu_to_be32((hwmgr->
hwmgr            2149 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			hwmgr->device, CGS_IND_REG__SMC,
hwmgr            2152 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	res = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.fan_table_start,
hwmgr            2156 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	if (!res && hwmgr->thermal_controller.
hwmgr            2158 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		res = smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            2160 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				hwmgr->thermal_controller.
hwmgr            2163 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	if (!res && hwmgr->thermal_controller.
hwmgr            2165 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		res = smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            2167 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				hwmgr->thermal_controller.
hwmgr            2171 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr            2177 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
hwmgr            2179 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
hwmgr            2182 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            2192 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
hwmgr            2196 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	cgs_write_ind_register(hwmgr->device,
hwmgr            2199 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            2201 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            2203 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            2209 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_update_vce_smc_table(struct pp_hwmgr *hwmgr)
hwmgr            2211 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
hwmgr            2214 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            2216 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            2227 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
hwmgr            2231 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	cgs_write_ind_register(hwmgr->device,
hwmgr            2234 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
hwmgr            2235 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            2241 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_update_bif_smc_table(struct pp_hwmgr *hwmgr)
hwmgr            2243 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
hwmgr            2245 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            2258 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
hwmgr            2262 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		polaris10_update_uvd_smc_table(hwmgr);
hwmgr            2265 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		polaris10_update_vce_smc_table(hwmgr);
hwmgr            2268 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		polaris10_update_bif_smc_table(hwmgr);
hwmgr            2275 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
hwmgr            2277 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            2278 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
hwmgr            2283 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            2292 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				hwmgr,
hwmgr            2303 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	result = polaris10_program_mem_timing_parameters(hwmgr);
hwmgr            2384 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
hwmgr            2386 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
hwmgr            2387 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            2392 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	result = smu7_read_smc_sram_dword(hwmgr,
hwmgr            2402 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	result = smu7_read_smc_sram_dword(hwmgr,
hwmgr            2414 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	result = smu7_read_smc_sram_dword(hwmgr,
hwmgr            2422 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	result = smu7_read_smc_sram_dword(hwmgr,
hwmgr            2432 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	result = smu7_read_smc_sram_dword(hwmgr,
hwmgr            2442 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	result = smu7_read_smc_sram_dword(hwmgr,
hwmgr            2448 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		hwmgr->microcode_version_info.SMC = tmp;
hwmgr            2455 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr)
hwmgr            2457 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
hwmgr            2462 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c static int polaris10_update_dpm_settings(struct pp_hwmgr *hwmgr,
hwmgr            2465 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            2467 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			(hwmgr->smu_backend);
hwmgr            2488 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_FreezeLevel);
hwmgr            2497 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
hwmgr            2499 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
hwmgr            2511 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
hwmgr            2514 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
hwmgr            2518 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_UnfreezeLevel);
hwmgr            2523 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_FreezeLevel);
hwmgr            2532 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
hwmgr            2534 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
hwmgr            2546 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
hwmgr            2549 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
hwmgr            2553 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 			smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_UnfreezeLevel);
hwmgr              49 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c static uint32_t smu10_wait_for_response(struct pp_hwmgr *hwmgr)
hwmgr              51 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr              56 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 	phm_wait_for_register_unequal(hwmgr, reg,
hwmgr              62 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c static int smu10_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr,
hwmgr              65 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr              72 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c static uint32_t smu10_read_arg_from_smc(struct pp_hwmgr *hwmgr)
hwmgr              74 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr              79 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c static int smu10_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
hwmgr              81 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr              83 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 	smu10_wait_for_response(hwmgr);
hwmgr              87 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 	smu10_send_msg_to_smc_without_waiting(hwmgr, msg);
hwmgr              89 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 	if (smu10_wait_for_response(hwmgr) == 0)
hwmgr              96 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c static int smu10_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
hwmgr              99 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             101 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 	smu10_wait_for_response(hwmgr);
hwmgr             107 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 	smu10_send_msg_to_smc_without_waiting(hwmgr, msg);
hwmgr             110 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 	if (smu10_wait_for_response(hwmgr) == 0)
hwmgr             116 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c static int smu10_copy_table_from_smc(struct pp_hwmgr *hwmgr,
hwmgr             120 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 			(struct smu10_smumgr *)(hwmgr->smu_backend);
hwmgr             121 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             129 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 	smu10_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             132 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 	smu10_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             135 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 	smu10_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             148 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c static int smu10_copy_table_to_smc(struct pp_hwmgr *hwmgr,
hwmgr             152 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 			(struct smu10_smumgr *)(hwmgr->smu_backend);
hwmgr             164 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 	smu10_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             167 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 	smu10_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             170 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 	smu10_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             177 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c static int smu10_verify_smc_interface(struct pp_hwmgr *hwmgr)
hwmgr             181 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 	smu10_send_msg_to_smc(hwmgr,
hwmgr             183 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 	smc_driver_if_version = smu10_read_arg_from_smc(hwmgr);
hwmgr             194 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c static int smu10_smu_fini(struct pp_hwmgr *hwmgr)
hwmgr             197 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 			(struct smu10_smumgr *)(hwmgr->smu_backend);
hwmgr             206 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 		kfree(hwmgr->smu_backend);
hwmgr             207 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 		hwmgr->smu_backend = NULL;
hwmgr             213 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c static int smu10_start_smu(struct pp_hwmgr *hwmgr)
hwmgr             215 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             217 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 	smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion);
hwmgr             218 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 	hwmgr->smu_version = smu10_read_arg_from_smc(hwmgr);
hwmgr             219 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 	adev->pm.fw_version = hwmgr->smu_version >> 8;
hwmgr             225 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 	if (smu10_verify_smc_interface(hwmgr))
hwmgr             231 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c static int smu10_smu_init(struct pp_hwmgr *hwmgr)
hwmgr             241 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 	hwmgr->smu_backend = priv;
hwmgr             244 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 	r = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
hwmgr             260 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 	r = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
hwmgr             286 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c static int smu10_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw)
hwmgr             291 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 		ret = smu10_copy_table_from_smc(hwmgr, table, table_id);
hwmgr             293 drivers/gpu/drm/amd/powerplay/smumgr/smu10_smumgr.c 		ret = smu10_copy_table_to_smc(hwmgr, table, table_id);
hwmgr              38 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c static int smu7_set_smc_sram_address(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t limit)
hwmgr              43 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_11, smc_addr);
hwmgr              44 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0); /* on ci, SMC_IND_ACCESS_CNTL is different */
hwmgr              49 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c int smu7_copy_bytes_from_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address, uint32_t *dest, uint32_t byte_count, uint32_t limit)
hwmgr              63 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 		smu7_read_smc_sram_dword(hwmgr, addr, &data, limit);
hwmgr              73 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 		smu7_read_smc_sram_dword(hwmgr, addr, &data, limit);
hwmgr              85 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c int smu7_copy_bytes_to_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address,
hwmgr             103 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 		result = smu7_set_smc_sram_address(hwmgr, addr, limit);
hwmgr             108 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 		cgs_write_register(hwmgr->device, mmSMC_IND_DATA_11, data);
hwmgr             119 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 		result = smu7_set_smc_sram_address(hwmgr, addr, limit);
hwmgr             125 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 		original_data = cgs_read_register(hwmgr->device, mmSMC_IND_DATA_11);
hwmgr             139 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 		result = smu7_set_smc_sram_address(hwmgr, addr, limit);
hwmgr             144 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 		cgs_write_register(hwmgr->device, mmSMC_IND_DATA_11, data);
hwmgr             151 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c int smu7_program_jump_on_start(struct pp_hwmgr *hwmgr)
hwmgr             155 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	smu7_copy_bytes_to_smc(hwmgr, 0x0, data, 4, sizeof(data)+1);
hwmgr             160 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c bool smu7_is_smc_ram_running(struct pp_hwmgr *hwmgr)
hwmgr             162 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	return ((0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable))
hwmgr             163 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	&& (0x20100 <= cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMC_PC_C)));
hwmgr             166 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c int smu7_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
hwmgr             170 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);
hwmgr             172 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	ret = PHM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP);
hwmgr             179 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	cgs_write_register(hwmgr->device, mmSMC_RESP_0, 0);
hwmgr             180 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, msg);
hwmgr             182 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);
hwmgr             184 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	ret = PHM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP);
hwmgr             194 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c int smu7_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr, uint16_t msg)
hwmgr             196 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, msg);
hwmgr             201 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c int smu7_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr, uint16_t msg, uint32_t parameter)
hwmgr             203 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);
hwmgr             205 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, parameter);
hwmgr             207 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	return smu7_send_msg_to_smc(hwmgr, msg);
hwmgr             210 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c int smu7_send_msg_to_smc_with_parameter_without_waiting(struct pp_hwmgr *hwmgr, uint16_t msg, uint32_t parameter)
hwmgr             212 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, parameter);
hwmgr             214 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	return smu7_send_msg_to_smc_without_waiting(hwmgr, msg);
hwmgr             217 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c int smu7_send_msg_to_smc_offset(struct pp_hwmgr *hwmgr)
hwmgr             219 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, 0x20000);
hwmgr             221 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	cgs_write_register(hwmgr->device, mmSMC_MESSAGE_0, PPSMC_MSG_Test);
hwmgr             223 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	PHM_WAIT_FIELD_UNEQUAL(hwmgr, SMC_RESP_0, SMC_RESP, 0);
hwmgr             225 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	if (1 != PHM_READ_FIELD(hwmgr->device, SMC_RESP_0, SMC_RESP))
hwmgr             280 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c int smu7_read_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t *value, uint32_t limit)
hwmgr             284 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	result = smu7_set_smc_sram_address(hwmgr, smc_addr, limit);
hwmgr             286 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	*value = result ? 0 : cgs_read_register(hwmgr->device, mmSMC_IND_DATA_11);
hwmgr             291 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c int smu7_write_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t value, uint32_t limit)
hwmgr             295 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	result = smu7_set_smc_sram_address(hwmgr, smc_addr, limit);
hwmgr             300 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	cgs_write_register(hwmgr->device, mmSMC_IND_DATA_11, value);
hwmgr             305 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c static int smu7_populate_single_firmware_entry(struct pp_hwmgr *hwmgr,
hwmgr             312 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	result = cgs_get_firmware_info(hwmgr->device,
hwmgr             325 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 		if (!hwmgr->not_vf)
hwmgr             340 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr)
hwmgr             342 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
hwmgr             346 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	amdgpu_ucode_init_bo(hwmgr->adev);
hwmgr             349 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             350 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 					smu_data->soft_regs_start + smum_get_offsetof(hwmgr,
hwmgr             354 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	if (hwmgr->chip_id > CHIP_TOPAZ) { /* add support for Topaz */
hwmgr             355 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 		if (hwmgr->not_vf) {
hwmgr             356 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 			smu7_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             359 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 			smu7_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             392 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 		PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
hwmgr             395 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 		PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
hwmgr             398 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 		PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
hwmgr             401 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 		PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
hwmgr             404 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 		PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
hwmgr             407 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 		PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
hwmgr             410 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 		PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
hwmgr             413 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 		PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
hwmgr             416 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 		PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
hwmgr             419 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 		if (!hwmgr->not_vf)
hwmgr             420 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 			PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
hwmgr             426 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DRV_DRAM_ADDR_HI, upper_32_bits(smu_data->header_buffer.mc_addr));
hwmgr             427 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_DRV_DRAM_ADDR_LO, lower_32_bits(smu_data->header_buffer.mc_addr));
hwmgr             429 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	smu7_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_LoadUcodes, fw_to_load);
hwmgr             431 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	r = smu7_check_fw_load_finish(hwmgr, fw_to_load);
hwmgr             444 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c int smu7_check_fw_load_finish(struct pp_hwmgr *hwmgr, uint32_t fw_type)
hwmgr             446 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
hwmgr             449 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	ret = phm_wait_on_indirect_register(hwmgr, mmSMC_IND_INDEX_11,
hwmgr             450 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 					smu_data->soft_regs_start + smum_get_offsetof(hwmgr,
hwmgr             456 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c int smu7_reload_firmware(struct pp_hwmgr *hwmgr)
hwmgr             458 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	return hwmgr->smumgr_funcs->start_smu(hwmgr);
hwmgr             461 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c static int smu7_upload_smc_firmware_data(struct pp_hwmgr *hwmgr, uint32_t length, uint32_t *src, uint32_t limit)
hwmgr             467 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	cgs_write_register(hwmgr->device, mmSMC_IND_INDEX_11, 0x20000);
hwmgr             468 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 1);
hwmgr             471 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 		cgs_write_register(hwmgr->device, mmSMC_IND_DATA_11, *src++);
hwmgr             473 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	PHM_WRITE_FIELD(hwmgr->device, SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_11, 0);
hwmgr             481 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c int smu7_upload_smu_firmware_image(struct pp_hwmgr *hwmgr)
hwmgr             484 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
hwmgr             489 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 		cgs_get_firmware_info(hwmgr->device,
hwmgr             492 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 		cgs_get_firmware_info(hwmgr->device,
hwmgr             495 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	hwmgr->is_kicker = info.is_kicker;
hwmgr             496 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	hwmgr->smu_version = info.version;
hwmgr             497 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	result = smu7_upload_smc_firmware_data(hwmgr, info.image_size, (uint32_t *)info.kptr, SMU7_SMC_SIZE);
hwmgr             502 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c static void execute_pwr_table(struct pp_hwmgr *hwmgr, const PWR_Command_Table *pvirus, int size)
hwmgr             511 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 			cgs_write_register(hwmgr->device, reg, data);
hwmgr             518 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c static void execute_pwr_dfy_table(struct pp_hwmgr *hwmgr, const PWR_DFY_Section *section)
hwmgr             522 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	cgs_write_register(hwmgr->device, mmCP_DFY_CNTL, section->dfy_cntl);
hwmgr             523 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	cgs_write_register(hwmgr->device, mmCP_DFY_ADDR_HI, section->dfy_addr_hi);
hwmgr             524 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	cgs_write_register(hwmgr->device, mmCP_DFY_ADDR_LO, section->dfy_addr_lo);
hwmgr             526 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 		cgs_write_register(hwmgr->device, mmCP_DFY_DATA_0, section->dfy_data[i]);
hwmgr             529 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c int smu7_setup_pwr_virus(struct pp_hwmgr *hwmgr)
hwmgr             531 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	execute_pwr_table(hwmgr, pwr_virus_table_pre, ARRAY_SIZE(pwr_virus_table_pre));
hwmgr             532 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	execute_pwr_dfy_table(hwmgr, &pwr_virus_section1);
hwmgr             533 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	execute_pwr_dfy_table(hwmgr, &pwr_virus_section2);
hwmgr             534 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	execute_pwr_dfy_table(hwmgr, &pwr_virus_section3);
hwmgr             535 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	execute_pwr_dfy_table(hwmgr, &pwr_virus_section4);
hwmgr             536 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	execute_pwr_dfy_table(hwmgr, &pwr_virus_section5);
hwmgr             537 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	execute_pwr_dfy_table(hwmgr, &pwr_virus_section6);
hwmgr             538 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	execute_pwr_table(hwmgr, pwr_virus_table_post, ARRAY_SIZE(pwr_virus_table_post));
hwmgr             543 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c int smu7_init(struct pp_hwmgr *hwmgr)
hwmgr             548 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
hwmgr             554 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	r = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
hwmgr             565 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	if (!hwmgr->not_vf)
hwmgr             569 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	r = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
hwmgr             584 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	if (smum_is_hw_avfs_present(hwmgr) &&
hwmgr             585 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	    (hwmgr->feature_mask & PP_AVFS_MASK))
hwmgr             586 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 		hwmgr->avfs_supported = true;
hwmgr             592 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c int smu7_smu_fini(struct pp_hwmgr *hwmgr)
hwmgr             594 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
hwmgr             600 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	if (hwmgr->not_vf)
hwmgr             608 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	kfree(hwmgr->smu_backend);
hwmgr             609 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c 	hwmgr->smu_backend = NULL;
hwmgr              56 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h int smu7_copy_bytes_from_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address,
hwmgr              58 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h int smu7_copy_bytes_to_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address,
hwmgr              60 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h int smu7_program_jump_on_start(struct pp_hwmgr *hwmgr);
hwmgr              61 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h bool smu7_is_smc_ram_running(struct pp_hwmgr *hwmgr);
hwmgr              62 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h int smu7_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg);
hwmgr              63 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h int smu7_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr, uint16_t msg);
hwmgr              64 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h int smu7_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr, uint16_t msg,
hwmgr              66 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h int smu7_send_msg_to_smc_with_parameter_without_waiting(struct pp_hwmgr *hwmgr,
hwmgr              68 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h int smu7_send_msg_to_smc_offset(struct pp_hwmgr *hwmgr);
hwmgr              71 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h int smu7_read_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr,
hwmgr              73 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h int smu7_write_smc_sram_dword(struct pp_hwmgr *hwmgr, uint32_t smc_addr,
hwmgr              76 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h int smu7_request_smu_load_fw(struct pp_hwmgr *hwmgr);
hwmgr              77 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h int smu7_check_fw_load_finish(struct pp_hwmgr *hwmgr, uint32_t fw_type);
hwmgr              78 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h int smu7_reload_firmware(struct pp_hwmgr *hwmgr);
hwmgr              79 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h int smu7_upload_smu_firmware_image(struct pp_hwmgr *hwmgr);
hwmgr              80 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h int smu7_init(struct pp_hwmgr *hwmgr);
hwmgr              81 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h int smu7_smu_fini(struct pp_hwmgr *hwmgr);
hwmgr              83 drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.h int smu7_setup_pwr_virus(struct pp_hwmgr *hwmgr);
hwmgr              56 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c static uint32_t smu8_get_argument(struct pp_hwmgr *hwmgr)
hwmgr              58 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	if (hwmgr == NULL || hwmgr->device == NULL)
hwmgr              61 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	return cgs_read_register(hwmgr->device,
hwmgr              66 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c static int smu8_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
hwmgr              73 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	if (hwmgr == NULL || hwmgr->device == NULL)
hwmgr              76 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	result = PHM_WAIT_FIELD_UNEQUAL(hwmgr,
hwmgr              80 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 		uint32_t val = cgs_read_register(hwmgr->device,
hwmgr              88 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	cgs_write_register(hwmgr->device, mmSMU_MP1_SRBM2P_ARG_0, parameter);
hwmgr              90 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	cgs_write_register(hwmgr->device, mmSMU_MP1_SRBM2P_RESP_0, 0);
hwmgr              91 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	cgs_write_register(hwmgr->device, mmSMU_MP1_SRBM2P_MSG_0, msg);
hwmgr              93 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	result = PHM_WAIT_FIELD_UNEQUAL(hwmgr,
hwmgr             104 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c static int smu8_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
hwmgr             106 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	return smu8_send_msg_to_smc_with_parameter(hwmgr, msg, 0);
hwmgr             109 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c static int smu8_set_smc_sram_address(struct pp_hwmgr *hwmgr,
hwmgr             112 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	if (hwmgr == NULL || hwmgr->device == NULL)
hwmgr             125 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	cgs_write_register(hwmgr->device, mmMP0PUB_IND_INDEX_0,
hwmgr             131 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c static int smu8_write_smc_sram_dword(struct pp_hwmgr *hwmgr,
hwmgr             136 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	if (hwmgr == NULL || hwmgr->device == NULL)
hwmgr             139 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	result = smu8_set_smc_sram_address(hwmgr, smc_address, limit);
hwmgr             141 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 		cgs_write_register(hwmgr->device, mmMP0PUB_IND_DATA_0, value);
hwmgr             146 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c static int smu8_check_fw_load_finish(struct pp_hwmgr *hwmgr,
hwmgr             154 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	if (hwmgr == NULL || hwmgr->device == NULL)
hwmgr             157 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	cgs_write_register(hwmgr->device, mmMP0PUB_IND_INDEX, index);
hwmgr             159 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	for (i = 0; i < hwmgr->usec_timeout; i++) {
hwmgr             161 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 			(cgs_read_register(hwmgr->device, mmMP0PUB_IND_DATA) & firmware))
hwmgr             166 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	if (i >= hwmgr->usec_timeout) {
hwmgr             174 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c static int smu8_load_mec_firmware(struct pp_hwmgr *hwmgr)
hwmgr             182 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	if (hwmgr == NULL || hwmgr->device == NULL)
hwmgr             185 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	smu8_smu = hwmgr->smu_backend;
hwmgr             186 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	ret = cgs_get_firmware_info(hwmgr->device,
hwmgr             193 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	tmp = cgs_read_register(hwmgr->device,
hwmgr             197 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, tmp);
hwmgr             199 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	tmp = cgs_read_register(hwmgr->device,
hwmgr             206 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_CNTL, tmp);
hwmgr             210 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_LO, reg_data);
hwmgr             214 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_HI, reg_data);
hwmgr             219 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c static uint8_t smu8_translate_firmware_enum_to_arg(struct pp_hwmgr *hwmgr,
hwmgr             229 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 		if (hwmgr->chip_id == CHIP_STONEY)
hwmgr             247 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 		if (hwmgr->chip_id == CHIP_STONEY)
hwmgr             329 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 			struct pp_hwmgr *hwmgr,
hwmgr             334 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	struct smu8_smumgr *smu8_smu = hwmgr->smu_backend;
hwmgr             339 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	task->arg = smu8_translate_firmware_enum_to_arg(hwmgr, fw_enum);
hwmgr             366 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 					struct pp_hwmgr *hwmgr,
hwmgr             371 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	struct smu8_smumgr *smu8_smu = hwmgr->smu_backend;
hwmgr             376 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	task->arg = smu8_translate_firmware_enum_to_arg(hwmgr, fw_enum);
hwmgr             395 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c static int smu8_smu_construct_toc_for_rlc_aram_save(struct pp_hwmgr *hwmgr)
hwmgr             397 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	struct smu8_smumgr *smu8_smu = hwmgr->smu_backend;
hwmgr             400 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	smu8_smu_populate_single_scratch_task(hwmgr,
hwmgr             407 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c static int smu8_smu_initialize_toc_empty_job_list(struct pp_hwmgr *hwmgr)
hwmgr             410 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	struct smu8_smumgr *smu8_smu = hwmgr->smu_backend;
hwmgr             419 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c static int smu8_smu_construct_toc_for_vddgfx_enter(struct pp_hwmgr *hwmgr)
hwmgr             421 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	struct smu8_smumgr *smu8_smu = hwmgr->smu_backend;
hwmgr             425 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	smu8_smu_populate_single_scratch_task(hwmgr,
hwmgr             429 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	smu8_smu_populate_single_scratch_task(hwmgr,
hwmgr             437 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c static int smu8_smu_construct_toc_for_vddgfx_exit(struct pp_hwmgr *hwmgr)
hwmgr             439 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	struct smu8_smumgr *smu8_smu = hwmgr->smu_backend;
hwmgr             444 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	smu8_smu_populate_single_ucode_load_task(hwmgr,
hwmgr             446 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	smu8_smu_populate_single_ucode_load_task(hwmgr,
hwmgr             448 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	smu8_smu_populate_single_ucode_load_task(hwmgr,
hwmgr             450 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	smu8_smu_populate_single_ucode_load_task(hwmgr,
hwmgr             453 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	if (hwmgr->chip_id == CHIP_STONEY)
hwmgr             454 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 		smu8_smu_populate_single_ucode_load_task(hwmgr,
hwmgr             457 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 		smu8_smu_populate_single_ucode_load_task(hwmgr,
hwmgr             460 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	smu8_smu_populate_single_ucode_load_task(hwmgr,
hwmgr             464 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	smu8_smu_populate_single_scratch_task(hwmgr,
hwmgr             468 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	smu8_smu_populate_single_scratch_task(hwmgr,
hwmgr             472 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	smu8_smu_populate_single_scratch_task(hwmgr,
hwmgr             479 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c static int smu8_smu_construct_toc_for_power_profiling(struct pp_hwmgr *hwmgr)
hwmgr             481 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	struct smu8_smumgr *smu8_smu = hwmgr->smu_backend;
hwmgr             485 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	smu8_smu_populate_single_scratch_task(hwmgr,
hwmgr             491 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c static int smu8_smu_construct_toc_for_bootup(struct pp_hwmgr *hwmgr)
hwmgr             493 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	struct smu8_smumgr *smu8_smu = hwmgr->smu_backend;
hwmgr             497 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	smu8_smu_populate_single_ucode_load_task(hwmgr,
hwmgr             499 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	if (hwmgr->chip_id != CHIP_STONEY)
hwmgr             500 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 		smu8_smu_populate_single_ucode_load_task(hwmgr,
hwmgr             502 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	smu8_smu_populate_single_ucode_load_task(hwmgr,
hwmgr             504 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	smu8_smu_populate_single_ucode_load_task(hwmgr,
hwmgr             506 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	smu8_smu_populate_single_ucode_load_task(hwmgr,
hwmgr             508 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	smu8_smu_populate_single_ucode_load_task(hwmgr,
hwmgr             510 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	if (hwmgr->chip_id != CHIP_STONEY)
hwmgr             511 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 		smu8_smu_populate_single_ucode_load_task(hwmgr,
hwmgr             513 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	smu8_smu_populate_single_ucode_load_task(hwmgr,
hwmgr             519 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c static int smu8_smu_construct_toc_for_clock_table(struct pp_hwmgr *hwmgr)
hwmgr             521 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	struct smu8_smumgr *smu8_smu = hwmgr->smu_backend;
hwmgr             525 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	smu8_smu_populate_single_scratch_task(hwmgr,
hwmgr             532 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c static int smu8_smu_construct_toc(struct pp_hwmgr *hwmgr)
hwmgr             534 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	struct smu8_smumgr *smu8_smu = hwmgr->smu_backend;
hwmgr             537 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	smu8_smu_initialize_toc_empty_job_list(hwmgr);
hwmgr             538 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	smu8_smu_construct_toc_for_rlc_aram_save(hwmgr);
hwmgr             539 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	smu8_smu_construct_toc_for_vddgfx_enter(hwmgr);
hwmgr             540 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	smu8_smu_construct_toc_for_vddgfx_exit(hwmgr);
hwmgr             541 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	smu8_smu_construct_toc_for_power_profiling(hwmgr);
hwmgr             542 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	smu8_smu_construct_toc_for_bootup(hwmgr);
hwmgr             543 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	smu8_smu_construct_toc_for_clock_table(hwmgr);
hwmgr             548 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c static int smu8_smu_populate_firmware_entries(struct pp_hwmgr *hwmgr)
hwmgr             550 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	struct smu8_smumgr *smu8_smu = hwmgr->smu_backend;
hwmgr             561 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 		firmware_type = smu8_translate_firmware_enum_to_arg(hwmgr,
hwmgr             566 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 		ret = cgs_get_firmware_info(hwmgr->device,
hwmgr             583 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 				struct pp_hwmgr *hwmgr,
hwmgr             588 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	struct smu8_smumgr *smu8_smu = hwmgr->smu_backend;
hwmgr             602 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c static int smu8_download_pptable_settings(struct pp_hwmgr *hwmgr, void **table)
hwmgr             604 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	struct smu8_smumgr *smu8_smu = hwmgr->smu_backend;
hwmgr             615 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	smu8_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             619 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	smu8_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             623 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	smu8_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ExecuteJob,
hwmgr             626 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	smu8_send_msg_to_smc(hwmgr, PPSMC_MSG_ClkTableXferToDram);
hwmgr             631 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c static int smu8_upload_pptable_settings(struct pp_hwmgr *hwmgr)
hwmgr             633 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	struct smu8_smumgr *smu8_smu = hwmgr->smu_backend;
hwmgr             642 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	smu8_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             646 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	smu8_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             650 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	smu8_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ExecuteJob,
hwmgr             653 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	smu8_send_msg_to_smc(hwmgr, PPSMC_MSG_ClkTableXferToSmu);
hwmgr             658 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c static int smu8_request_smu_load_fw(struct pp_hwmgr *hwmgr)
hwmgr             660 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	struct smu8_smumgr *smu8_smu = hwmgr->smu_backend;
hwmgr             665 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	amdgpu_ucode_init_bo(hwmgr->adev);
hwmgr             667 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	smu8_smu_populate_firmware_entries(hwmgr);
hwmgr             669 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	smu8_smu_construct_toc(hwmgr);
hwmgr             674 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	smu8_write_smc_sram_dword(hwmgr, smc_address, 0, smc_address+4);
hwmgr             676 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	smu8_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             680 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	smu8_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             684 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	smu8_send_msg_to_smc(hwmgr, PPSMC_MSG_InitJobs);
hwmgr             686 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	smu8_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             689 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	smu8_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ExecuteJob,
hwmgr             692 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	smu8_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             705 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	if (hwmgr->chip_id == CHIP_STONEY)
hwmgr             708 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	ret = smu8_check_fw_load_finish(hwmgr, fw_to_check);
hwmgr             714 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	ret = smu8_load_mec_firmware(hwmgr);
hwmgr             723 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c static int smu8_start_smu(struct pp_hwmgr *hwmgr)
hwmgr             731 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	if (hwmgr == NULL || hwmgr->device == NULL)
hwmgr             734 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	adev = hwmgr->adev;
hwmgr             736 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	cgs_write_register(hwmgr->device, mmMP0PUB_IND_INDEX, index);
hwmgr             737 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	hwmgr->smu_version = cgs_read_register(hwmgr->device, mmMP0PUB_IND_DATA);
hwmgr             739 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 		((hwmgr->smu_version >> 16) & 0xFF),
hwmgr             740 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 		((hwmgr->smu_version >> 8) & 0xFF),
hwmgr             741 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 		(hwmgr->smu_version & 0xFF));
hwmgr             742 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	adev->pm.fw_version = hwmgr->smu_version >> 8;
hwmgr             744 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	return smu8_request_smu_load_fw(hwmgr);
hwmgr             747 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c static int smu8_smu_init(struct pp_hwmgr *hwmgr)
hwmgr             756 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	hwmgr->smu_backend = smu8_smu;
hwmgr             766 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
hwmgr             776 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
hwmgr             786 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	if (0 != smu8_smu_populate_single_scratch_entry(hwmgr,
hwmgr             794 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	if (0 != smu8_smu_populate_single_scratch_entry(hwmgr,
hwmgr             801 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	if (0 != smu8_smu_populate_single_scratch_entry(hwmgr,
hwmgr             809 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	if (0 != smu8_smu_populate_single_scratch_entry(hwmgr,
hwmgr             817 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	if (0 != smu8_smu_populate_single_scratch_entry(hwmgr,
hwmgr             840 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c static int smu8_smu_fini(struct pp_hwmgr *hwmgr)
hwmgr             844 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	if (hwmgr == NULL || hwmgr->device == NULL)
hwmgr             847 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	smu8_smu = hwmgr->smu_backend;
hwmgr             861 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c static bool smu8_dpm_check_smu_features(struct pp_hwmgr *hwmgr,
hwmgr             867 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	result = smu8_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetFeatureStatus, 0);
hwmgr             869 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 		features = smum_get_argument(hwmgr);
hwmgr             877 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c static bool smu8_is_dpm_running(struct pp_hwmgr *hwmgr)
hwmgr             879 drivers/gpu/drm/amd/powerplay/smumgr/smu8_smumgr.c 	if (smu8_dpm_check_smu_features(hwmgr, SMU_EnabledFeatureScoreboard_SclkDpmOn))
hwmgr              38 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c bool smu9_is_smc_ram_running(struct pp_hwmgr *hwmgr)
hwmgr              40 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr              58 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c static uint32_t smu9_wait_for_response(struct pp_hwmgr *hwmgr)
hwmgr              60 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr              66 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c 	ret = phm_wait_for_register_unequal(hwmgr, reg,
hwmgr              81 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c static int smu9_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr,
hwmgr              84 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr              97 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c int smu9_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
hwmgr              99 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             102 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c 	smu9_wait_for_response(hwmgr);
hwmgr             106 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c 	smu9_send_msg_to_smc_without_waiting(hwmgr, msg);
hwmgr             108 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c 	ret = smu9_wait_for_response(hwmgr);
hwmgr             122 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c int smu9_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
hwmgr             125 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             128 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c 	smu9_wait_for_response(hwmgr);
hwmgr             134 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c 	smu9_send_msg_to_smc_without_waiting(hwmgr, msg);
hwmgr             136 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c 	ret = smu9_wait_for_response(hwmgr);
hwmgr             143 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c uint32_t smu9_get_argument(struct pp_hwmgr *hwmgr)
hwmgr             145 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr              26 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.h bool smu9_is_smc_ram_running(struct pp_hwmgr *hwmgr);
hwmgr              27 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.h int smu9_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg);
hwmgr              28 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.h int smu9_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
hwmgr              30 drivers/gpu/drm/amd/powerplay/smumgr/smu9_smumgr.h uint32_t smu9_get_argument(struct pp_hwmgr *hwmgr);
hwmgr              57 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c int smum_thermal_avfs_enable(struct pp_hwmgr *hwmgr)
hwmgr              59 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c 	if (NULL != hwmgr->smumgr_funcs->thermal_avfs_enable)
hwmgr              60 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c 		return hwmgr->smumgr_funcs->thermal_avfs_enable(hwmgr);
hwmgr              65 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c int smum_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
hwmgr              67 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c 	if (NULL != hwmgr->smumgr_funcs->thermal_setup_fan_table)
hwmgr              68 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c 		return hwmgr->smumgr_funcs->thermal_setup_fan_table(hwmgr);
hwmgr              73 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c int smum_update_sclk_threshold(struct pp_hwmgr *hwmgr)
hwmgr              76 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c 	if (NULL != hwmgr->smumgr_funcs->update_sclk_threshold)
hwmgr              77 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c 		return hwmgr->smumgr_funcs->update_sclk_threshold(hwmgr);
hwmgr              82 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c int smum_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
hwmgr              85 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c 	if (NULL != hwmgr->smumgr_funcs->update_smc_table)
hwmgr              86 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c 		return hwmgr->smumgr_funcs->update_smc_table(hwmgr, type);
hwmgr              91 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c uint32_t smum_get_offsetof(struct pp_hwmgr *hwmgr, uint32_t type, uint32_t member)
hwmgr              93 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c 	if (NULL != hwmgr->smumgr_funcs->get_offsetof)
hwmgr              94 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c 		return hwmgr->smumgr_funcs->get_offsetof(type, member);
hwmgr              99 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c int smum_process_firmware_header(struct pp_hwmgr *hwmgr)
hwmgr             101 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c 	if (NULL != hwmgr->smumgr_funcs->process_firmware_header)
hwmgr             102 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c 		return hwmgr->smumgr_funcs->process_firmware_header(hwmgr);
hwmgr             106 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c uint32_t smum_get_argument(struct pp_hwmgr *hwmgr)
hwmgr             108 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c 	if (NULL != hwmgr->smumgr_funcs->get_argument)
hwmgr             109 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c 		return hwmgr->smumgr_funcs->get_argument(hwmgr);
hwmgr             114 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c uint32_t smum_get_mac_definition(struct pp_hwmgr *hwmgr, uint32_t value)
hwmgr             116 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c 	if (NULL != hwmgr->smumgr_funcs->get_mac_definition)
hwmgr             117 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c 		return hwmgr->smumgr_funcs->get_mac_definition(value);
hwmgr             122 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c int smum_download_powerplay_table(struct pp_hwmgr *hwmgr, void **table)
hwmgr             124 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c 	if (NULL != hwmgr->smumgr_funcs->download_pptable_settings)
hwmgr             125 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c 		return hwmgr->smumgr_funcs->download_pptable_settings(hwmgr,
hwmgr             130 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c int smum_upload_powerplay_table(struct pp_hwmgr *hwmgr)
hwmgr             132 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c 	if (NULL != hwmgr->smumgr_funcs->upload_pptable_settings)
hwmgr             133 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c 		return hwmgr->smumgr_funcs->upload_pptable_settings(hwmgr);
hwmgr             138 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c int smum_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
hwmgr             140 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c 	if (hwmgr == NULL || hwmgr->smumgr_funcs->send_msg_to_smc == NULL)
hwmgr             143 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c 	return hwmgr->smumgr_funcs->send_msg_to_smc(hwmgr, msg);
hwmgr             146 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c int smum_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
hwmgr             149 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c 	if (hwmgr == NULL ||
hwmgr             150 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c 		hwmgr->smumgr_funcs->send_msg_to_smc_with_parameter == NULL)
hwmgr             152 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c 	return hwmgr->smumgr_funcs->send_msg_to_smc_with_parameter(
hwmgr             153 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c 						hwmgr, msg, parameter);
hwmgr             156 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c int smum_init_smc_table(struct pp_hwmgr *hwmgr)
hwmgr             158 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c 	if (NULL != hwmgr->smumgr_funcs->init_smc_table)
hwmgr             159 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c 		return hwmgr->smumgr_funcs->init_smc_table(hwmgr);
hwmgr             164 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c int smum_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
hwmgr             166 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c 	if (NULL != hwmgr->smumgr_funcs->populate_all_graphic_levels)
hwmgr             167 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c 		return hwmgr->smumgr_funcs->populate_all_graphic_levels(hwmgr);
hwmgr             172 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c int smum_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
hwmgr             174 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c 	if (NULL != hwmgr->smumgr_funcs->populate_all_memory_levels)
hwmgr             175 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c 		return hwmgr->smumgr_funcs->populate_all_memory_levels(hwmgr);
hwmgr             181 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c int smum_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
hwmgr             183 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c 	if (NULL != hwmgr->smumgr_funcs->initialize_mc_reg_table)
hwmgr             184 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c 		return hwmgr->smumgr_funcs->initialize_mc_reg_table(hwmgr);
hwmgr             189 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c bool smum_is_dpm_running(struct pp_hwmgr *hwmgr)
hwmgr             191 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c 	if (NULL != hwmgr->smumgr_funcs->is_dpm_running)
hwmgr             192 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c 		return hwmgr->smumgr_funcs->is_dpm_running(hwmgr);
hwmgr             197 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c bool smum_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
hwmgr             199 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c 	if (hwmgr->smumgr_funcs->is_hw_avfs_present)
hwmgr             200 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c 		return hwmgr->smumgr_funcs->is_hw_avfs_present(hwmgr);
hwmgr             205 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c int smum_update_dpm_settings(struct pp_hwmgr *hwmgr, void *profile_setting)
hwmgr             207 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c 	if (hwmgr->smumgr_funcs->update_dpm_settings)
hwmgr             208 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c 		return hwmgr->smumgr_funcs->update_dpm_settings(hwmgr, profile_setting);
hwmgr             213 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c int smum_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw)
hwmgr             215 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c 	if (hwmgr->smumgr_funcs->smc_table_manager)
hwmgr             216 drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c 		return hwmgr->smumgr_funcs->smc_table_manager(hwmgr, table, table_id, rw);
hwmgr              97 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_start_in_protection_mode(struct pp_hwmgr *hwmgr)
hwmgr             102 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             105 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	result = smu7_upload_smu_firmware_image(hwmgr);
hwmgr             110 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             114 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             118 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             122 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             126 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             129 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
hwmgr             135 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	smu7_send_msg_to_smc_offset(hwmgr);
hwmgr             138 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
hwmgr             142 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	if (1 != PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
hwmgr             149 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
hwmgr             155 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_start_in_non_protection_mode(struct pp_hwmgr *hwmgr)
hwmgr             160 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND,
hwmgr             164 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             168 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             171 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	result = smu7_upload_smu_firmware_image(hwmgr);
hwmgr             177 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	smu7_program_jump_on_start(hwmgr);
hwmgr             180 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             184 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             188 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
hwmgr             194 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_start_smu(struct pp_hwmgr *hwmgr)
hwmgr             196 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct tonga_smumgr *priv = hwmgr->smu_backend;
hwmgr             200 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	if (!smu7_is_smc_ram_running(hwmgr) && hwmgr->not_vf) {
hwmgr             202 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		if (0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             204 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			result = tonga_start_in_non_protection_mode(hwmgr);
hwmgr             208 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			result = tonga_start_in_protection_mode(hwmgr);
hwmgr             217 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	smu7_read_smc_sram_dword(hwmgr,
hwmgr             222 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	result = smu7_request_smu_load_fw(hwmgr);
hwmgr             227 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_smu_init(struct pp_hwmgr *hwmgr)
hwmgr             235 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	hwmgr->smu_backend = tonga_priv;
hwmgr             237 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	if (smu7_init(hwmgr)) {
hwmgr             246 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
hwmgr             251 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             253 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			   (struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr             302 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_populate_smc_vddc_table(struct pp_hwmgr *hwmgr,
hwmgr             306 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             319 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_populate_smc_vdd_gfx_table(struct pp_hwmgr *hwmgr,
hwmgr             323 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             336 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_populate_smc_vdd_ci_table(struct pp_hwmgr *hwmgr,
hwmgr             339 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             366 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
hwmgr             369 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             391 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_populate_cac_tables(struct pp_hwmgr *hwmgr,
hwmgr             396 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             398 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr             446 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
hwmgr             451 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	result = tonga_populate_smc_vddc_table(hwmgr, table);
hwmgr             456 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	result = tonga_populate_smc_vdd_ci_table(hwmgr, table);
hwmgr             461 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	result = tonga_populate_smc_vdd_gfx_table(hwmgr, table);
hwmgr             466 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	result = tonga_populate_smc_mvdd_table(hwmgr, table);
hwmgr             471 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	result = tonga_populate_cac_tables(hwmgr, table);
hwmgr             479 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_populate_ulv_level(struct pp_hwmgr *hwmgr,
hwmgr             483 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr             501 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_populate_ulv_state(struct pp_hwmgr *hwmgr,
hwmgr             504 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	return tonga_populate_ulv_level(hwmgr, &table->Ulv);
hwmgr             507 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU72_Discrete_DpmTable *table)
hwmgr             509 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             511 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
hwmgr             538 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_calculate_sclk_params(struct pp_hwmgr *hwmgr,
hwmgr             541 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             554 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock,  &dividers);
hwmgr             560 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	reference_clock = atomctrl_get_reference_clock(hwmgr);
hwmgr             581 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr             586 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		if (0 == atomctrl_get_engine_clock_spread_spectrum(hwmgr, vcoFreq, &ss_info)) {
hwmgr             616 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
hwmgr             622 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             624 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			    (struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr             627 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	result = tonga_calculate_sclk_params(hwmgr, engine_clock, graphic_level);
hwmgr             629 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	if (hwmgr->od_enabled)
hwmgr             635 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	result = tonga_get_dependency_volt_by_clk(hwmgr,
hwmgr             659 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			hwmgr->display_config->min_core_set_clock_in_sr;
hwmgr             661 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr             686 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
hwmgr             688 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             689 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
hwmgr             690 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr             711 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		result = tonga_populate_single_graphic_level(hwmgr,
hwmgr             780 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	result = smu7_copy_bytes_to_smc(hwmgr, level_array_address,
hwmgr             788 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		struct pp_hwmgr *hwmgr,
hwmgr             795 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             810 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	result = atomctrl_get_memory_pll_dividers_si(hwmgr,
hwmgr             847 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr             867 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		uint32_t reference_clock = atomctrl_get_mpll_reference_clock(hwmgr);
hwmgr             879 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		if (0 == atomctrl_get_memory_clock_spread_spectrum(hwmgr, freq_nom, &ss_info)) {
hwmgr             960 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		struct pp_hwmgr *hwmgr,
hwmgr             965 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             967 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			  (struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr             977 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	if (hwmgr->od_enabled)
hwmgr             983 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		result = tonga_get_dependency_volt_by_clk(hwmgr,
hwmgr            1016 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
hwmgr            1017 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	data->display_timing.vrefresh = hwmgr->display_config->vrefresh;
hwmgr            1022 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	    && (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL, STUTTER_ENABLE) & 0x1)
hwmgr            1048 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 					((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC7) >> 16) & 0xf)) {
hwmgr            1049 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
hwmgr            1051 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC6) >> 1) & 0x1) ? 1 : 0;
hwmgr            1060 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		dll_state_on = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
hwmgr            1063 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	result = tonga_calculate_mclk_params(hwmgr,
hwmgr            1086 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c int tonga_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
hwmgr            1088 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1090 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			(struct tonga_smumgr *)(hwmgr->smu_backend);
hwmgr            1112 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				hwmgr,
hwmgr            1136 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	result = smu7_copy_bytes_to_smc(hwmgr,
hwmgr            1143 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_populate_mvdd_value(struct pp_hwmgr *hwmgr,
hwmgr            1146 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1148 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            1173 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
hwmgr            1178 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				(struct tonga_smumgr *)(hwmgr->smu_backend);
hwmgr            1179 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1195 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr);
hwmgr            1198 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	result = atomctrl_get_engine_pll_dividers_vi(hwmgr,
hwmgr            1246 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	if (0 == tonga_populate_mvdd_value(hwmgr, 0, &voltage_level))
hwmgr            1307 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
hwmgr            1314 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1316 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            1340 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 					hwmgr,
hwmgr            1350 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
hwmgr            1367 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
hwmgr            1374 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1376 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			      (struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            1399 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
hwmgr            1413 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
hwmgr            1419 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1421 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			     (struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            1444 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
hwmgr            1458 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		struct pp_hwmgr *hwmgr,
hwmgr            1469 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
hwmgr            1475 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	dramTiming  = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
hwmgr            1476 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	dramTiming2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
hwmgr            1477 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	burstTime = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
hwmgr            1486 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
hwmgr            1488 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1490 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				(struct tonga_smumgr *)(hwmgr->smu_backend);
hwmgr            1500 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				(hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value,
hwmgr            1511 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				hwmgr,
hwmgr            1522 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
hwmgr            1526 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1528 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				(struct tonga_smumgr *)(hwmgr->smu_backend);
hwmgr            1573 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
hwmgr            1579 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				(struct tonga_smumgr *)(hwmgr->smu_backend);
hwmgr            1583 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            1587 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr            1597 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
hwmgr            1599 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	efuse2 = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
hwmgr            1644 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
hwmgr            1646 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
hwmgr            1648 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
hwmgr            1650 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, PWR_CKS_ENABLE,
hwmgr            1659 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr            1666 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
hwmgr            1698 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
hwmgr            1737 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
hwmgr            1740 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
hwmgr            1746 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_populate_vr_config(struct pp_hwmgr *hwmgr,
hwmgr            1749 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1797 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_init_arb_table_index(struct pp_hwmgr *hwmgr)
hwmgr            1799 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
hwmgr            1812 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	result = smu7_read_smc_sram_dword(hwmgr,
hwmgr            1821 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	return smu7_write_smc_sram_dword(hwmgr,
hwmgr            1826 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
hwmgr            1829 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				(struct tonga_smumgr *)(hwmgr->smu_backend);
hwmgr            1833 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            1873 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_populate_svi_load_line(struct pp_hwmgr *hwmgr)
hwmgr            1876 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				(struct tonga_smumgr *)(hwmgr->smu_backend);
hwmgr            1887 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_populate_tdc_limit(struct pp_hwmgr *hwmgr)
hwmgr            1891 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				(struct tonga_smumgr *)(hwmgr->smu_backend);
hwmgr            1894 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            1909 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
hwmgr            1912 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			(struct tonga_smumgr *)(hwmgr->smu_backend);
hwmgr            1916 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	if (smu7_read_smc_sram_dword(hwmgr,
hwmgr            1930 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
hwmgr            1934 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				(struct tonga_smumgr *)(hwmgr->smu_backend);
hwmgr            1943 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
hwmgr            1945 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
hwmgr            1947 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	if ((hwmgr->thermal_controller.advanceFanControlParameters.
hwmgr            1949 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		(hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity == 0))
hwmgr            1950 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		hwmgr->thermal_controller.advanceFanControlParameters.
hwmgr            1951 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		usFanOutputSensitivity = hwmgr->thermal_controller.
hwmgr            1955 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			PP_HOST_TO_SMC_US(hwmgr->thermal_controller.
hwmgr            1960 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
hwmgr            1964 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				(struct tonga_smumgr *)(hwmgr->smu_backend);
hwmgr            1973 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
hwmgr            1976 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				(struct tonga_smumgr *)(hwmgr->smu_backend);
hwmgr            1978 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            1994 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_populate_pm_fuses(struct pp_hwmgr *hwmgr)
hwmgr            1997 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				(struct tonga_smumgr *)(hwmgr->smu_backend);
hwmgr            2000 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            2002 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		if (smu7_read_smc_sram_dword(hwmgr,
hwmgr            2011 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		if (tonga_populate_svi_load_line(hwmgr))
hwmgr            2016 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		if (tonga_populate_tdc_limit(hwmgr))
hwmgr            2021 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		if (tonga_populate_dw8(hwmgr, pm_fuse_table_offset))
hwmgr            2027 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		if (tonga_populate_temperature_scaler(hwmgr) != 0)
hwmgr            2033 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		if (tonga_populate_fuzzy_fan(hwmgr))
hwmgr            2040 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		if (tonga_populate_gnb_lpml(hwmgr))
hwmgr            2046 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		if (tonga_populate_bapm_vddc_base_leakage_sidd(hwmgr))
hwmgr            2053 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
hwmgr            2063 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_populate_mc_reg_address(struct pp_hwmgr *hwmgr,
hwmgr            2066 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	const struct tonga_smumgr *smu_data = (struct tonga_smumgr *)hwmgr->smu_backend;
hwmgr            2107 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		struct pp_hwmgr *hwmgr,
hwmgr            2112 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
hwmgr            2132 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_convert_mc_reg_table_to_smc(struct pp_hwmgr *hwmgr,
hwmgr            2136 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            2142 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				hwmgr,
hwmgr            2154 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_update_and_upload_mc_reg_table(struct pp_hwmgr *hwmgr)
hwmgr            2156 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
hwmgr            2157 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            2167 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	result = tonga_convert_mc_reg_table_to_smc(hwmgr, &(smu_data->mc_regs));
hwmgr            2177 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			hwmgr, address,
hwmgr            2184 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_populate_initial_mc_reg_table(struct pp_hwmgr *hwmgr)
hwmgr            2187 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
hwmgr            2190 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	result = tonga_populate_mc_reg_address(hwmgr, &(smu_data->mc_regs));
hwmgr            2195 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	result = tonga_convert_mc_reg_table_to_smc(hwmgr, &smu_data->mc_regs);
hwmgr            2200 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	return smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.mc_reg_table_start,
hwmgr            2204 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static void tonga_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
hwmgr            2206 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
hwmgr            2208 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			(struct  phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            2220 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_init_smc_table(struct pp_hwmgr *hwmgr)
hwmgr            2223 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            2225 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			(struct tonga_smumgr *)(hwmgr->smu_backend);
hwmgr            2228 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            2236 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	tonga_initialize_power_tune_defaults(hwmgr);
hwmgr            2239 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		tonga_populate_smc_voltage_tables(hwmgr, table);
hwmgr            2241 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            2246 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            2253 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	i = PHM_READ_FIELD(hwmgr->device, CC_MC_MAX_CHANNEL, NOOFCHAN);
hwmgr            2259 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		result = tonga_populate_ulv_state(hwmgr, table);
hwmgr            2264 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
hwmgr            2268 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	result = tonga_populate_smc_link_level(hwmgr, table);
hwmgr            2272 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	result = tonga_populate_all_graphic_levels(hwmgr);
hwmgr            2276 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	result = tonga_populate_all_memory_levels(hwmgr);
hwmgr            2280 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	result = tonga_populate_smc_acpi_level(hwmgr, table);
hwmgr            2284 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	result = tonga_populate_smc_vce_level(hwmgr, table);
hwmgr            2288 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	result = tonga_populate_smc_acp_level(hwmgr, table);
hwmgr            2296 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	result = tonga_program_memory_timing_parameters(hwmgr);
hwmgr            2301 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	result = tonga_populate_smc_uvd_level(hwmgr, table);
hwmgr            2305 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	result = tonga_populate_smc_boot_level(hwmgr, table);
hwmgr            2309 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	tonga_populate_bapm_parameters_in_dpm_table(hwmgr);
hwmgr            2313 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            2315 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		result = tonga_populate_clock_stretcher_data_table(hwmgr);
hwmgr            2354 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	result = tonga_populate_vr_config(hwmgr, table);
hwmgr            2361 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID,
hwmgr            2364 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr            2368 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr            2372 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
hwmgr            2375 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr            2379 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr            2383 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr            2387 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr            2389 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr            2393 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	if (atomctrl_get_pp_assign_pin(hwmgr,
hwmgr            2395 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr            2401 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			(0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) &
hwmgr            2407 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            2409 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            2414 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr            2436 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			hwmgr,
hwmgr            2445 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	result = tonga_init_arb_table_index(hwmgr);
hwmgr            2449 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	tonga_populate_pm_fuses(hwmgr);
hwmgr            2453 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	result = tonga_populate_initial_mc_reg_table(hwmgr);
hwmgr            2460 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
hwmgr            2463 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			(struct tonga_smumgr *)(hwmgr->smu_backend);
hwmgr            2472 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            2476 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	if (hwmgr->thermal_controller.fanInfo.bNoFan) {
hwmgr            2477 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr            2483 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr            2488 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
hwmgr            2493 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr            2498 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin * duty100;
hwmgr            2502 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed -
hwmgr            2503 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		   hwmgr->thermal_controller.advanceFanControlParameters.usTMin;
hwmgr            2504 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh -
hwmgr            2505 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		  hwmgr->thermal_controller.advanceFanControlParameters.usTMed;
hwmgr            2507 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed -
hwmgr            2508 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		    hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin;
hwmgr            2509 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh -
hwmgr            2510 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		    hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed;
hwmgr            2515 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	fan_table.TempMin = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMin) / 100);
hwmgr            2516 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	fan_table.TempMed = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMed) / 100);
hwmgr            2517 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	fan_table.TempMax = cpu_to_be16((50 + hwmgr->thermal_controller.advanceFanControlParameters.usTMax) / 100);
hwmgr            2524 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	fan_table.HystDown = cpu_to_be16(hwmgr->thermal_controller.advanceFanControlParameters.ucTHyst);
hwmgr            2532 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	reference_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
hwmgr            2534 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	fan_table.RefreshPeriod = cpu_to_be32((hwmgr->thermal_controller.advanceFanControlParameters.ulCycleDelay * reference_clock) / 1600);
hwmgr            2538 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_MULT_THERMAL_CTRL, TEMP_SEL);
hwmgr            2542 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	res = smu7_copy_bytes_to_smc(hwmgr,
hwmgr            2552 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
hwmgr            2554 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            2558 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		return tonga_program_memory_timing_parameters(hwmgr);
hwmgr            2563 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_update_sclk_threshold(struct pp_hwmgr *hwmgr)
hwmgr            2565 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            2567 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			(struct tonga_smumgr *)(hwmgr->smu_backend);
hwmgr            2572 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            2581 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				hwmgr,
hwmgr            2590 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	result = tonga_update_and_upload_mc_reg_table(hwmgr);
hwmgr            2596 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	result = tonga_program_mem_timing_parameters(hwmgr);
hwmgr            2675 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
hwmgr            2678 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				(struct tonga_smumgr *)(hwmgr->smu_backend);
hwmgr            2681 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            2691 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
hwmgr            2695 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	cgs_write_ind_register(hwmgr->device,
hwmgr            2699 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            2701 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            2703 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            2709 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_update_vce_smc_table(struct pp_hwmgr *hwmgr)
hwmgr            2712 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				(struct tonga_smumgr *)(hwmgr->smu_backend);
hwmgr            2715 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            2725 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
hwmgr            2729 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	cgs_write_ind_register(hwmgr->device,
hwmgr            2732 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            2734 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            2740 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
hwmgr            2744 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		tonga_update_uvd_smc_table(hwmgr);
hwmgr            2747 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		tonga_update_vce_smc_table(hwmgr);
hwmgr            2755 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_process_firmware_header(struct pp_hwmgr *hwmgr)
hwmgr            2757 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            2758 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
hwmgr            2764 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	result = smu7_read_smc_sram_dword(hwmgr,
hwmgr            2774 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	result = smu7_read_smc_sram_dword(hwmgr,
hwmgr            2787 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	result = smu7_read_smc_sram_dword(hwmgr,
hwmgr            2795 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	result = smu7_read_smc_sram_dword(hwmgr,
hwmgr            2805 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	result = smu7_read_smc_sram_dword(hwmgr,
hwmgr            2815 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	result = smu7_read_smc_sram_dword(hwmgr,
hwmgr            2821 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		hwmgr->microcode_version_info.SMC = tmp;
hwmgr            2830 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static uint8_t tonga_get_memory_modile_index(struct pp_hwmgr *hwmgr)
hwmgr            2832 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16));
hwmgr            2972 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_set_mc_special_registers(struct pp_hwmgr *hwmgr,
hwmgr            2977 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            2986 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			temp_reg = cgs_read_register(hwmgr->device,
hwmgr            2999 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS);
hwmgr            3026 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1);
hwmgr            3065 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
hwmgr            3068 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct tonga_smumgr *smu_data = (struct tonga_smumgr *)(hwmgr->smu_backend);
hwmgr            3071 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	uint8_t module_index = tonga_get_memory_modile_index(hwmgr);
hwmgr            3079 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP,
hwmgr            3080 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING));
hwmgr            3081 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_CAS_TIMING_LP,
hwmgr            3082 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			cgs_read_register(hwmgr->device, mmMC_SEQ_CAS_TIMING));
hwmgr            3083 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_DLL_STBY_LP,
hwmgr            3084 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			cgs_read_register(hwmgr->device, mmMC_SEQ_DLL_STBY));
hwmgr            3085 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0_LP,
hwmgr            3086 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD0));
hwmgr            3087 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1_LP,
hwmgr            3088 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CMD1));
hwmgr            3089 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL_LP,
hwmgr            3090 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			cgs_read_register(hwmgr->device, mmMC_SEQ_G5PDX_CTRL));
hwmgr            3091 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD_LP,
hwmgr            3092 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CMD));
hwmgr            3093 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL_LP,
hwmgr            3094 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_DVS_CTL));
hwmgr            3095 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING_LP,
hwmgr            3096 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING));
hwmgr            3097 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2_LP,
hwmgr            3098 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			cgs_read_register(hwmgr->device, mmMC_SEQ_MISC_TIMING2));
hwmgr            3099 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_EMRS_LP,
hwmgr            3100 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			cgs_read_register(hwmgr->device, mmMC_PMG_CMD_EMRS));
hwmgr            3101 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS_LP,
hwmgr            3102 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS));
hwmgr            3103 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS1_LP,
hwmgr            3104 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS1));
hwmgr            3105 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0_LP,
hwmgr            3106 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D0));
hwmgr            3107 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1_LP,
hwmgr            3108 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_D1));
hwmgr            3109 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0_LP,
hwmgr            3110 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D0));
hwmgr            3111 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1_LP,
hwmgr            3112 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			cgs_read_register(hwmgr->device, mmMC_SEQ_RD_CTL_D1));
hwmgr            3113 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_TIMING_LP,
hwmgr            3114 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			cgs_read_register(hwmgr->device, mmMC_SEQ_PMG_TIMING));
hwmgr            3115 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_PMG_CMD_MRS2_LP,
hwmgr            3116 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS2));
hwmgr            3117 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	cgs_write_register(hwmgr->device, mmMC_SEQ_WR_CTL_2_LP,
hwmgr            3118 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			cgs_read_register(hwmgr->device, mmMC_SEQ_WR_CTL_2));
hwmgr            3120 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table);
hwmgr            3127 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		result = tonga_set_mc_special_registers(hwmgr, ni_table);
hwmgr            3138 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static bool tonga_is_dpm_running(struct pp_hwmgr *hwmgr)
hwmgr            3140 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
hwmgr            3145 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c static int tonga_update_dpm_settings(struct pp_hwmgr *hwmgr,
hwmgr            3148 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            3150 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			(hwmgr->smu_backend);
hwmgr            3171 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_FreezeLevel);
hwmgr            3180 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
hwmgr            3182 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
hwmgr            3194 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
hwmgr            3197 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
hwmgr            3201 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_UnfreezeLevel);
hwmgr            3206 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_FreezeLevel);
hwmgr            3215 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
hwmgr            3217 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
hwmgr            3229 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
hwmgr            3232 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 				cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
hwmgr            3236 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 			smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_UnfreezeLevel);
hwmgr              38 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c static int vega10_copy_table_from_smc(struct pp_hwmgr *hwmgr,
hwmgr              41 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c 	struct vega10_smumgr *priv = hwmgr->smu_backend;
hwmgr              42 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr              50 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c 	smu9_send_msg_to_smc_with_parameter(hwmgr,
hwmgr              53 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c 	smu9_send_msg_to_smc_with_parameter(hwmgr,
hwmgr              56 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c 	smu9_send_msg_to_smc_with_parameter(hwmgr,
hwmgr              69 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c static int vega10_copy_table_to_smc(struct pp_hwmgr *hwmgr,
hwmgr              72 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c 	struct vega10_smumgr *priv = hwmgr->smu_backend;
hwmgr              84 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c 	smu9_send_msg_to_smc_with_parameter(hwmgr,
hwmgr              87 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c 	smu9_send_msg_to_smc_with_parameter(hwmgr,
hwmgr              90 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c 	smu9_send_msg_to_smc_with_parameter(hwmgr,
hwmgr              97 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c int vega10_enable_smc_features(struct pp_hwmgr *hwmgr,
hwmgr             103 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c 	return smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             107 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c int vega10_get_enabled_smc_features(struct pp_hwmgr *hwmgr,
hwmgr             113 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c 	smu9_send_msg_to_smc(hwmgr, PPSMC_MSG_GetEnabledSmuFeatures);
hwmgr             114 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c 	*features_enabled = smu9_get_argument(hwmgr);
hwmgr             119 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c static bool vega10_is_dpm_running(struct pp_hwmgr *hwmgr)
hwmgr             123 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c 	vega10_get_enabled_smc_features(hwmgr, &features_enabled);
hwmgr             131 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c static int vega10_set_tools_address(struct pp_hwmgr *hwmgr)
hwmgr             133 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c 	struct vega10_smumgr *priv = hwmgr->smu_backend;
hwmgr             136 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c 		smu9_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             139 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c 		smu9_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             146 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c static int vega10_verify_smc_interface(struct pp_hwmgr *hwmgr)
hwmgr             149 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             153 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c 	PP_ASSERT_WITH_CODE(!smu9_send_msg_to_smc(hwmgr,
hwmgr             157 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c 	smc_driver_if_version = smu9_get_argument(hwmgr);
hwmgr             176 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c static int vega10_smu_init(struct pp_hwmgr *hwmgr)
hwmgr             183 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c 	ret = cgs_get_firmware_info(hwmgr->device,
hwmgr             194 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c 	hwmgr->smu_backend = priv;
hwmgr             197 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c 	ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
hwmgr             212 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c 	ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
hwmgr             228 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c 	ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
hwmgr             245 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c 		ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
hwmgr             260 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c 	ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
hwmgr             295 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c 	kfree(hwmgr->smu_backend);
hwmgr             300 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c static int vega10_smu_fini(struct pp_hwmgr *hwmgr)
hwmgr             302 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c 	struct vega10_smumgr *priv = hwmgr->smu_backend;
hwmgr             321 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c 		kfree(hwmgr->smu_backend);
hwmgr             322 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c 		hwmgr->smu_backend = NULL;
hwmgr             327 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c static int vega10_start_smu(struct pp_hwmgr *hwmgr)
hwmgr             329 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c 	if (!smu9_is_smc_ram_running(hwmgr))
hwmgr             332 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c 	PP_ASSERT_WITH_CODE(!vega10_verify_smc_interface(hwmgr),
hwmgr             336 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c 	vega10_set_tools_address(hwmgr);
hwmgr             341 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c static int vega10_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table,
hwmgr             347 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c 		ret = vega10_copy_table_from_smc(hwmgr, table, table_id);
hwmgr             349 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c 		ret = vega10_copy_table_to_smc(hwmgr, table, table_id);
hwmgr              45 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.h int vega10_enable_smc_features(struct pp_hwmgr *hwmgr,
hwmgr              47 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.h int vega10_get_enabled_smc_features(struct pp_hwmgr *hwmgr,
hwmgr              40 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c static int vega12_copy_table_from_smc(struct pp_hwmgr *hwmgr,
hwmgr              44 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c 			(struct vega12_smumgr *)(hwmgr->smu_backend);
hwmgr              45 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr              53 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c 	PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc_with_parameter(hwmgr,
hwmgr              57 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c 	PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc_with_parameter(hwmgr,
hwmgr              62 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c 	PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc_with_parameter(hwmgr,
hwmgr              82 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c static int vega12_copy_table_to_smc(struct pp_hwmgr *hwmgr,
hwmgr              86 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c 			(struct vega12_smumgr *)(hwmgr->smu_backend);
hwmgr              98 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c 	PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             103 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c 	PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             108 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c 	PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             117 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c int vega12_enable_smc_features(struct pp_hwmgr *hwmgr,
hwmgr             126 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c 		PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             130 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c 		PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             135 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c 		PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             139 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c 		PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             148 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c int vega12_get_enabled_smc_features(struct pp_hwmgr *hwmgr,
hwmgr             156 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c 	PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc(hwmgr,
hwmgr             160 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c 	smc_features_low = smu9_get_argument(hwmgr);
hwmgr             162 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c 	PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc(hwmgr,
hwmgr             166 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c 	smc_features_high = smu9_get_argument(hwmgr);
hwmgr             174 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c static bool vega12_is_dpm_running(struct pp_hwmgr *hwmgr)
hwmgr             178 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c 	vega12_get_enabled_smc_features(hwmgr, &features_enabled);
hwmgr             186 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c static int vega12_set_tools_address(struct pp_hwmgr *hwmgr)
hwmgr             189 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c 			(struct vega12_smumgr *)(hwmgr->smu_backend);
hwmgr             192 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c 		if (!smu9_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             195 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c 			smu9_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             202 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c static int vega12_smu_init(struct pp_hwmgr *hwmgr)
hwmgr             209 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c 	ret = cgs_get_firmware_info(hwmgr->device, CGS_UCODE_ID_SMU,
hwmgr             218 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c 	hwmgr->smu_backend = priv;
hwmgr             221 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c 	ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
hwmgr             235 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c 	ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
hwmgr             251 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c 		ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
hwmgr             266 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c 	ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
hwmgr             281 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c 	ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
hwmgr             295 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c 	ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
hwmgr             332 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c 	kfree(hwmgr->smu_backend);
hwmgr             337 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c static int vega12_smu_fini(struct pp_hwmgr *hwmgr)
hwmgr             340 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c 			(struct vega12_smumgr *)(hwmgr->smu_backend);
hwmgr             362 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c 		kfree(hwmgr->smu_backend);
hwmgr             363 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c 		hwmgr->smu_backend = NULL;
hwmgr             368 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c static int vega12_start_smu(struct pp_hwmgr *hwmgr)
hwmgr             370 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c 	PP_ASSERT_WITH_CODE(smu9_is_smc_ram_running(hwmgr),
hwmgr             374 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c 	vega12_set_tools_address(hwmgr);
hwmgr             379 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c static int vega12_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table,
hwmgr             385 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c 		ret = vega12_copy_table_from_smc(hwmgr, table, table_id);
hwmgr             387 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.c 		ret = vega12_copy_table_to_smc(hwmgr, table, table_id);
hwmgr              51 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.h int vega12_enable_smc_features(struct pp_hwmgr *hwmgr,
hwmgr              53 drivers/gpu/drm/amd/powerplay/smumgr/vega12_smumgr.h int vega12_get_enabled_smc_features(struct pp_hwmgr *hwmgr,
hwmgr              47 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c bool vega20_is_smc_ram_running(struct pp_hwmgr *hwmgr)
hwmgr              49 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr              68 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c static uint32_t vega20_wait_for_response(struct pp_hwmgr *hwmgr)
hwmgr              70 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr              75 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	phm_wait_for_register_unequal(hwmgr, reg,
hwmgr              87 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c static int vega20_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr,
hwmgr              90 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             103 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c static int vega20_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
hwmgr             105 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             108 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	vega20_wait_for_response(hwmgr);
hwmgr             112 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	vega20_send_msg_to_smc_without_waiting(hwmgr, msg);
hwmgr             114 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	ret = vega20_wait_for_response(hwmgr);
hwmgr             128 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c static int vega20_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
hwmgr             131 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             134 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	vega20_wait_for_response(hwmgr);
hwmgr             140 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	vega20_send_msg_to_smc_without_waiting(hwmgr, msg);
hwmgr             142 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	ret = vega20_wait_for_response(hwmgr);
hwmgr             149 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c static uint32_t vega20_get_argument(struct pp_hwmgr *hwmgr)
hwmgr             151 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             161 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c static int vega20_copy_table_from_smc(struct pp_hwmgr *hwmgr,
hwmgr             165 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 			(struct vega20_smumgr *)(hwmgr->smu_backend);
hwmgr             166 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             176 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             181 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             186 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             205 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c static int vega20_copy_table_to_smc(struct pp_hwmgr *hwmgr,
hwmgr             209 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 			(struct vega20_smumgr *)(hwmgr->smu_backend);
hwmgr             222 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             227 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             232 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             240 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c int vega20_set_activity_monitor_coeff(struct pp_hwmgr *hwmgr,
hwmgr             244 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 			(struct vega20_smumgr *)(hwmgr->smu_backend);
hwmgr             250 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             255 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             260 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             268 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c int vega20_get_activity_monitor_coeff(struct pp_hwmgr *hwmgr,
hwmgr             272 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 			(struct vega20_smumgr *)(hwmgr->smu_backend);
hwmgr             273 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr             276 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             281 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             286 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             301 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c int vega20_enable_smc_features(struct pp_hwmgr *hwmgr,
hwmgr             311 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 		PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             315 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 		PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             320 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 		PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             324 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 		PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             333 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c int vega20_get_enabled_smc_features(struct pp_hwmgr *hwmgr,
hwmgr             342 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc(hwmgr,
hwmgr             346 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	smc_features_low = vega20_get_argument(hwmgr);
hwmgr             347 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc(hwmgr,
hwmgr             351 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	smc_features_high = vega20_get_argument(hwmgr);
hwmgr             359 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c static int vega20_set_tools_address(struct pp_hwmgr *hwmgr)
hwmgr             362 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 			(struct vega20_smumgr *)(hwmgr->smu_backend);
hwmgr             366 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 		ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             370 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 			ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             378 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c int vega20_set_pptable_driver_address(struct pp_hwmgr *hwmgr)
hwmgr             381 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 			(struct vega20_smumgr *)(hwmgr->smu_backend);
hwmgr             384 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             389 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             398 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c static int vega20_smu_init(struct pp_hwmgr *hwmgr)
hwmgr             406 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	ret = cgs_get_firmware_info(hwmgr->device,
hwmgr             416 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	hwmgr->smu_backend = priv;
hwmgr             419 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
hwmgr             433 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
hwmgr             447 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
hwmgr             461 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
hwmgr             475 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
hwmgr             489 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
hwmgr             525 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	kfree(hwmgr->smu_backend);
hwmgr             530 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c static int vega20_smu_fini(struct pp_hwmgr *hwmgr)
hwmgr             533 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 			(struct vega20_smumgr *)(hwmgr->smu_backend);
hwmgr             554 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 		kfree(hwmgr->smu_backend);
hwmgr             555 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 		hwmgr->smu_backend = NULL;
hwmgr             560 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c static int vega20_start_smu(struct pp_hwmgr *hwmgr)
hwmgr             564 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	ret = vega20_is_smc_ram_running(hwmgr);
hwmgr             569 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	ret = vega20_set_tools_address(hwmgr);
hwmgr             577 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c static bool vega20_is_dpm_running(struct pp_hwmgr *hwmgr)
hwmgr             581 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 	vega20_get_enabled_smc_features(hwmgr, &features_enabled);
hwmgr             589 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c static int vega20_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table,
hwmgr             595 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 		ret = vega20_copy_table_from_smc(hwmgr, table, table_id);
hwmgr             597 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.c 		ret = vega20_copy_table_to_smc(hwmgr, table, table_id);
hwmgr              50 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.h int vega20_enable_smc_features(struct pp_hwmgr *hwmgr,
hwmgr              52 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.h int vega20_get_enabled_smc_features(struct pp_hwmgr *hwmgr,
hwmgr              54 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.h int vega20_set_activity_monitor_coeff(struct pp_hwmgr *hwmgr,
hwmgr              56 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.h int vega20_get_activity_monitor_coeff(struct pp_hwmgr *hwmgr,
hwmgr              58 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.h int vega20_set_pptable_driver_address(struct pp_hwmgr *hwmgr);
hwmgr              60 drivers/gpu/drm/amd/powerplay/smumgr/vega20_smumgr.h bool vega20_is_smc_ram_running(struct pp_hwmgr *hwmgr);
hwmgr              82 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_smu_init(struct pp_hwmgr *hwmgr)
hwmgr              90 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	hwmgr->smu_backend = smu_data;
hwmgr              92 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	if (smu7_init(hwmgr)) {
hwmgr             100 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
hwmgr             108 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             111 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	result = smu7_upload_smu_firmware_image(hwmgr);
hwmgr             116 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0);
hwmgr             118 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             122 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             126 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1);
hwmgr             130 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	smu7_send_msg_to_smc_offset(hwmgr);
hwmgr             135 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, SMU_STATUS, SMU_DONE, 0);
hwmgr             137 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	if (1 != PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             141 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0);
hwmgr             143 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             146 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             150 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
hwmgr             155 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr)
hwmgr             160 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0);
hwmgr             164 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             167 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             171 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	result = smu7_upload_smu_firmware_image(hwmgr);
hwmgr             176 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	smu7_program_jump_on_start(hwmgr);
hwmgr             178 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             181 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
hwmgr             186 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
hwmgr             192 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_start_smu(struct pp_hwmgr *hwmgr)
hwmgr             195 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
hwmgr             198 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	if (!smu7_is_smc_ram_running(hwmgr) && hwmgr->not_vf) {
hwmgr             199 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		smu_data->protected_mode = (uint8_t)(PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
hwmgr             202 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 				hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL));
hwmgr             206 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			result = vegam_start_smu_in_non_protection_mode(hwmgr);
hwmgr             208 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			result = vegam_start_smu_in_protection_mode(hwmgr);
hwmgr             215 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	smu7_read_smc_sram_dword(hwmgr,
hwmgr             220 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	result = smu7_request_smu_load_fw(hwmgr);
hwmgr             225 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_process_firmware_header(struct pp_hwmgr *hwmgr)
hwmgr             227 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
hwmgr             228 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             233 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	result = smu7_read_smc_sram_dword(hwmgr,
hwmgr             243 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	result = smu7_read_smc_sram_dword(hwmgr,
hwmgr             255 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	result = smu7_read_smc_sram_dword(hwmgr,
hwmgr             263 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	result = smu7_read_smc_sram_dword(hwmgr,
hwmgr             273 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	result = smu7_read_smc_sram_dword(hwmgr,
hwmgr             283 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	result = smu7_read_smc_sram_dword(hwmgr,
hwmgr             289 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		hwmgr->microcode_version_info.SMC = tmp;
hwmgr             296 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static bool vegam_is_dpm_running(struct pp_hwmgr *hwmgr)
hwmgr             298 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
hwmgr             331 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
hwmgr             333 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
hwmgr             336 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr             346 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
hwmgr             350 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	cgs_write_ind_register(hwmgr->device,
hwmgr             353 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr             355 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr             357 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             363 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_update_vce_smc_table(struct pp_hwmgr *hwmgr)
hwmgr             365 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
hwmgr             368 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr             370 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr             381 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
hwmgr             385 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	cgs_write_ind_register(hwmgr->device,
hwmgr             388 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
hwmgr             389 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr             395 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_update_bif_smc_table(struct pp_hwmgr *hwmgr)
hwmgr             397 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
hwmgr             399 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr             412 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
hwmgr             416 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		vegam_update_uvd_smc_table(hwmgr);
hwmgr             419 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		vegam_update_vce_smc_table(hwmgr);
hwmgr             422 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		vegam_update_bif_smc_table(hwmgr);
hwmgr             430 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static void vegam_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
hwmgr             432 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
hwmgr             434 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			(struct  phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr             447 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
hwmgr             450 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             474 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_populate_smc_vddci_table(struct pp_hwmgr *hwmgr,
hwmgr             478 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             499 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_populate_cac_table(struct pp_hwmgr *hwmgr,
hwmgr             504 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             506 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr             528 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
hwmgr             531 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	vegam_populate_smc_vddci_table(hwmgr, table);
hwmgr             532 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	vegam_populate_smc_mvdd_table(hwmgr, table);
hwmgr             533 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	vegam_populate_cac_table(hwmgr, table);
hwmgr             538 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_populate_ulv_level(struct pp_hwmgr *hwmgr,
hwmgr             541 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             543 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr             561 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_populate_ulv_state(struct pp_hwmgr *hwmgr,
hwmgr             564 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	return vegam_populate_ulv_level(hwmgr, &table->Ulv);
hwmgr             567 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_populate_smc_link_level(struct pp_hwmgr *hwmgr,
hwmgr             570 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             572 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			(struct vegam_smumgr *)(hwmgr->smu_backend);
hwmgr             599 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
hwmgr             605 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             666 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static void vegam_get_sclk_range_table(struct pp_hwmgr *hwmgr,
hwmgr             669 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
hwmgr             674 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	ref_clk = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
hwmgr             676 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) {
hwmgr             716 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_calculate_sclk_params(struct pp_hwmgr *hwmgr,
hwmgr             719 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
hwmgr             730 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock,  &dividers);
hwmgr             746 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	ref_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
hwmgr             806 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
hwmgr             812 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             814 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr             817 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	result = vegam_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);
hwmgr             820 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	result = vegam_get_dependency_volt_by_clk(hwmgr,
hwmgr             836 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr;
hwmgr             838 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
hwmgr             840 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 								hwmgr->display_config->min_core_set_clock_in_sr);
hwmgr             861 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
hwmgr             863 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             864 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
hwmgr             867 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr             883 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	vegam_get_sclk_range_table(hwmgr, &(smu_data->smc_state_table));
hwmgr             887 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		result = vegam_populate_single_graphic_level(hwmgr,
hwmgr             901 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr             954 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
hwmgr             960 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_calculate_mclk_params(struct pp_hwmgr *hwmgr,
hwmgr             965 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	PP_ASSERT_WITH_CODE(!atomctrl_get_memory_pll_dividers_ai(hwmgr,
hwmgr             978 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_populate_single_memory_level(struct pp_hwmgr *hwmgr,
hwmgr             981 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr             983 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr             989 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		result = vegam_get_dependency_volt_by_clk(hwmgr,
hwmgr             997 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	result = vegam_calculate_mclk_params(hwmgr, clock, mem_level);
hwmgr            1010 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
hwmgr            1011 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	data->display_timing.vrefresh = hwmgr->display_config->vrefresh;
hwmgr            1015 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		(PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
hwmgr            1031 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
hwmgr            1033 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1034 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
hwmgr            1050 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		result = vegam_populate_single_memory_level(hwmgr,
hwmgr            1076 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
hwmgr            1082 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_populate_mvdd_value(struct pp_hwmgr *hwmgr,
hwmgr            1085 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1087 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            1107 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
hwmgr            1112 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1114 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            1124 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	result = vegam_get_dependency_volt_by_clk(hwmgr,
hwmgr            1133 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	result = vegam_calculate_sclk_params(hwmgr, sclk_frequency,
hwmgr            1162 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	result = vegam_get_dependency_volt_by_clk(hwmgr,
hwmgr            1176 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		if (!vegam_populate_mvdd_value(hwmgr,
hwmgr            1182 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	if (!vegam_populate_mvdd_value(hwmgr, 0, &vol_level))
hwmgr            1203 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
hwmgr            1210 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            1213 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1239 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
hwmgr            1253 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
hwmgr            1265 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
hwmgr            1271 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
hwmgr            1272 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
hwmgr            1273 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	burst_time = cgs_read_register(hwmgr->device, mmMC_ARB_BURST_TIME);
hwmgr            1274 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	rfsh_rate = cgs_read_register(hwmgr->device, mmMC_ARB_RFSH_RATE);
hwmgr            1275 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	misc3 = cgs_read_register(hwmgr->device, mmMC_ARB_MISC3);
hwmgr            1286 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
hwmgr            1288 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1289 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
hwmgr            1298 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			result = vegam_populate_memory_timing_parameters(hwmgr,
hwmgr            1308 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			hwmgr,
hwmgr            1316 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
hwmgr            1323 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            1326 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1351 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
hwmgr            1358 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
hwmgr            1373 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
hwmgr            1377 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1405 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_populate_smc_initial_state(struct pp_hwmgr *hwmgr)
hwmgr            1407 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1408 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
hwmgr            1410 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            1442 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
hwmgr            1444 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
hwmgr            1449 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            1452 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			&hwmgr->thermal_controller.advanceFanControlParameters;
hwmgr            1490 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
hwmgr            1494 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			(struct vegam_smumgr *)(hwmgr->smu_backend);
hwmgr            1498 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            1505 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	atomctrl_read_efuse(hwmgr, STRAP_ASIC_RO_LSB, STRAP_ASIC_RO_MSB,
hwmgr            1540 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr            1547 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
hwmgr            1549 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
hwmgr            1554 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static bool vegam_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
hwmgr            1558 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
hwmgr            1568 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
hwmgr            1570 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1571 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
hwmgr            1581 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			(struct phm_ppt_v1_information *)hwmgr->pptable;
hwmgr            1585 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	if (!hwmgr->avfs_supported)
hwmgr            1588 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	result = atomctrl_get_avfs_information(hwmgr, &avfs_params);
hwmgr            1643 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		result = smu7_read_smc_sram_dword(hwmgr,
hwmgr            1647 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		smu7_copy_bytes_to_smc(hwmgr,
hwmgr            1653 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		result = smu7_read_smc_sram_dword(hwmgr,
hwmgr            1657 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		smu7_copy_bytes_to_smc(hwmgr,
hwmgr            1674 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_populate_vr_config(struct pp_hwmgr *hwmgr,
hwmgr            1677 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1679 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			(struct vegam_smumgr *)(hwmgr->smu_backend);
hwmgr            1710 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			cgs_write_ind_register(hwmgr->device,
hwmgr            1724 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		cgs_write_ind_register(hwmgr->device,
hwmgr            1737 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_populate_svi_load_line(struct pp_hwmgr *hwmgr)
hwmgr            1739 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
hwmgr            1750 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_populate_tdc_limit(struct pp_hwmgr *hwmgr)
hwmgr            1753 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
hwmgr            1755 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            1768 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
hwmgr            1770 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
hwmgr            1774 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	if (smu7_read_smc_sram_dword(hwmgr,
hwmgr            1792 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
hwmgr            1795 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
hwmgr            1804 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
hwmgr            1806 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
hwmgr            1809 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	if ((hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity & (1 << 15))
hwmgr            1810 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		|| 0 == hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity)
hwmgr            1811 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity =
hwmgr            1812 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity;
hwmgr            1815 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 				hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity);
hwmgr            1819 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
hwmgr            1822 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
hwmgr            1831 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
hwmgr            1833 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
hwmgr            1835 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            1851 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_populate_pm_fuses(struct pp_hwmgr *hwmgr)
hwmgr            1853 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
hwmgr            1856 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            1858 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		if (smu7_read_smc_sram_dword(hwmgr,
hwmgr            1866 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		if (vegam_populate_svi_load_line(hwmgr))
hwmgr            1871 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		if (vegam_populate_tdc_limit(hwmgr))
hwmgr            1875 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		if (vegam_populate_dw8(hwmgr, pm_fuse_table_offset))
hwmgr            1881 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		if (0 != vegam_populate_temperature_scaler(hwmgr))
hwmgr            1886 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		if (vegam_populate_fuzzy_fan(hwmgr))
hwmgr            1891 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		if (vegam_populate_gnb_lpml(hwmgr))
hwmgr            1896 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		if (vegam_populate_bapm_vddc_base_leakage_sidd(hwmgr))
hwmgr            1901 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
hwmgr            1912 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_enable_reconfig_cus(struct pp_hwmgr *hwmgr)
hwmgr            1914 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct amdgpu_device *adev = hwmgr->adev;
hwmgr            1916 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	smum_send_msg_to_smc_with_parameter(hwmgr,
hwmgr            1923 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_init_smc_table(struct pp_hwmgr *hwmgr)
hwmgr            1926 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            1927 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
hwmgr            1930 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			(struct phm_ppt_v1_information *)(hwmgr->pptable);
hwmgr            1938 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr            1941 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	vegam_initialize_power_tune_defaults(hwmgr);
hwmgr            1944 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		vegam_populate_smc_voltage_tables(hwmgr, table);
hwmgr            1947 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            1951 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            1959 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		result = vegam_populate_ulv_state(hwmgr, table);
hwmgr            1962 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
hwmgr            1966 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	result = vegam_populate_smc_link_level(hwmgr, table);
hwmgr            1970 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	result = vegam_populate_all_graphic_levels(hwmgr);
hwmgr            1974 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	result = vegam_populate_all_memory_levels(hwmgr);
hwmgr            1978 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	result = vegam_populate_smc_acpi_level(hwmgr, table);
hwmgr            1982 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	result = vegam_populate_smc_vce_level(hwmgr, table);
hwmgr            1990 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	result = vegam_program_memory_timing_parameters(hwmgr);
hwmgr            1994 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	result = vegam_populate_smc_uvd_level(hwmgr, table);
hwmgr            1998 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	result = vegam_populate_smc_boot_level(hwmgr, table);
hwmgr            2002 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	result = vegam_populate_smc_initial_state(hwmgr);
hwmgr            2006 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	result = vegam_populate_bapm_parameters_in_dpm_table(hwmgr);
hwmgr            2010 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            2012 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		result = vegam_populate_clock_stretcher_data_table(hwmgr);
hwmgr            2018 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	result = vegam_populate_avfs_parameters(hwmgr);
hwmgr            2048 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	result = vegam_populate_vr_config(hwmgr, table);
hwmgr            2055 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	if (atomctrl_get_pp_assign_pin(hwmgr,
hwmgr            2063 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr            2067 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	if (atomctrl_get_pp_assign_pin(hwmgr,
hwmgr            2070 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            2072 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 				!smum_send_msg_to_smc(hwmgr, PPSMC_MSG_UseNewGPIOScheme))
hwmgr            2073 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			phm_cap_set(hwmgr->platform_descriptor.platformCaps,
hwmgr            2077 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
hwmgr            2082 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	if (atomctrl_get_pp_assign_pin(hwmgr,
hwmgr            2092 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 				(0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) &
hwmgr            2097 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            2099 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            2110 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
hwmgr            2139 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	result = smu7_copy_bytes_to_smc(hwmgr,
hwmgr            2148 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	result = vegam_populate_pm_fuses(hwmgr);
hwmgr            2152 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	result = vegam_enable_reconfig_cus(hwmgr);
hwmgr            2205 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
hwmgr            2207 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            2213 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		return vegam_program_memory_timing_parameters(hwmgr);
hwmgr            2218 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_update_sclk_threshold(struct pp_hwmgr *hwmgr)
hwmgr            2220 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            2222 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			(struct vegam_smumgr *)(hwmgr->smu_backend);
hwmgr            2226 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
hwmgr            2235 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 				hwmgr,
hwmgr            2246 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	result = vegam_program_mem_timing_parameters(hwmgr);
hwmgr            2254 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c int vegam_thermal_avfs_enable(struct pp_hwmgr *hwmgr)
hwmgr            2256 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
hwmgr            2259 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	if (!hwmgr->avfs_supported)
hwmgr            2262 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAvfs);
hwmgr            2265 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 			ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ApplyAvfsCksOffVoltage);
hwmgr            2271 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c static int vegam_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
hwmgr            2273 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	PP_ASSERT_WITH_CODE(hwmgr->thermal_controller.fanInfo.bNoFan,
hwmgr            2276 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,